Documentation/devicetree/bindings/net/stmmac.txt

   1 * STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
   2
   3 Required properties:
   4 - compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac"
   5         For backwards compatibility: "st,spear600-gmac" is also supported.
   6 - reg: Address and length of the register set for the device
   7 - interrupt-parent: Should be the phandle for the interrupt controller
   8   that services interrupts for this device
   9 - interrupts: Should contain the STMMAC interrupts
  10 - interrupt-names: Should contain the interrupt names "macirq"
  11   "eth_wake_irq" if this interrupt is supported in the "interrupts"
  12   property
  13 - phy-mode: See ethernet.txt file in the same directory.
  14 - snps,reset-gpio       gpio number for phy reset.
  15 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
  16 - snps,reset-delays-us  is triplet of delays
  17         The 1st cell is reset pre-delay in micro seconds.
  18         The 2nd cell is reset pulse in micro seconds.
  19         The 3rd cell is reset post-delay in micro seconds.
  20
  21 Optional properties:
  22 - resets: Should contain a phandle to the STMMAC reset signal, if any
  23 - reset-names: Should contain the reset signal name "stmmaceth", if a
  24         reset phandle is given
  25 - max-frame-size: See ethernet.txt file in the same directory
  26 - clocks: If present, the first clock should be the GMAC main clock and
  27   the second clock should be peripheral's register interface clock. Further
  28   clocks may be specified in derived bindings.
  29 - clock-names: One name for each entry in the clocks property, the
  30   first one should be "stmmaceth" and the second one should be "pclk".
  31 - clk_ptp_ref: this is the PTP reference clock; in case of the PTP is
  32   available this clock is used for programming the Timestamp Addend Register.
  33   If not passed then the system clock will be used and this is fine on some
  34   platforms.
  35 - tx-fifo-depth: See ethernet.txt file in the same directory
  36 - rx-fifo-depth: See ethernet.txt file in the same directory
  37 - snps,pbl              Programmable Burst Length (tx and rx)
  38 - snps,txpbl            Tx Programmable Burst Length. Only for GMAC and newer.
  39                         If set, DMA tx will use this value rather than snps,pbl.
  40 - snps,rxpbl            Rx Programmable Burst Length. Only for GMAC and newer.
  41                         If set, DMA rx will use this value rather than snps,pbl.
  42 - snps,no-pbl-x8        Don't multiply the pbl/txpbl/rxpbl values by 8.
  43                         For core rev < 3.50, don't multiply the values by 4.
  44 - snps,aal              Address-Aligned Beats
  45 - snps,fixed-burst      Program the DMA to use the fixed burst mode
  46 - snps,mixed-burst      Program the DMA to use the mixed burst mode
  47 - snps,force_thresh_dma_mode    Force DMA to use the threshold mode for
  48                                 both tx and rx
  49 - snps,force_sf_dma_mode        Force DMA to use the Store and Forward
  50                                 mode for both tx and rx. This flag is
  51                                 ignored if force_thresh_dma_mode is set.
  52 - snps,multicast-filter-bins:   Number of multicast filter hash bins
  53                                 supported by this device instance
  54 - snps,perfect-filter-entries:  Number of perfect filter entries supported
  55                                 by this device instance
  56 - snps,ps-speed: port selection speed that can be passed to the core when
  57                  PCS is supported. For example, this is used in case of SGMII
  58                  and MAC2MAC connection.
  59 - snps,tso: this enables the TSO feature otherwise it will be managed by
  60                  MAC HW capability register. Only for GMAC4 and newer.
  61 - AXI BUS Mode parameters: below the list of all the parameters to program the
  62                            AXI register inside the DMA module:
  63         - snps,lpi_en: enable Low Power Interface
  64         - snps,xit_frm: unlock on WoL
  65         - snps,wr_osr_lmt: max write outstanding req. limit
  66         - snps,rd_osr_lmt: max read outstanding req. limit
  67         - snps,kbbe: do not cross 1KiB boundary.
  68         - snps,axi_all: align address
  69         - snps,blen: this is a vector of supported burst length.
  70         - snps,fb: fixed-burst
  71         - snps,mb: mixed-burst
  72         - snps,rb: rebuild INCRx Burst
  73 - mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus.
  74
  75 Examples:
  76
  77         stmmac_axi_setup: stmmac-axi-config {
  78                 snps,wr_osr_lmt = <0xf>;
  79                 snps,rd_osr_lmt = <0xf>;
  80                 snps,blen = <256 128 64 32 0 0 0>;
  81         };
  82
  83         gmac0: ethernet@e0800000 {
  84                 compatible = "st,spear600-gmac";
  85                 reg = <0xe0800000 0x8000>;
  86                 interrupt-parent = <&vic1>;
  87                 interrupts = <24 23>;
  88                 interrupt-names = "macirq", "eth_wake_irq";
  89                 mac-address = [000000000000]; /* Filled in by U-Boot */
  90                 max-frame-size = <3800>;
  91                 phy-mode = "gmii";
  92                 snps,multicast-filter-bins = <256>;
  93                 snps,perfect-filter-entries = <128>;
  94                 rx-fifo-depth = <16384>;
  95                 tx-fifo-depth = <16384>;
  96                 clocks = <&clock>;
  97                 clock-names = "stmmaceth";
  98                 snps,axi-config = <&stmmac_axi_setup>;
  99                 mdio0 {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         compatible = "snps,dwmac-mdio";
 103                         phy1: ethernet-phy@0 {
 104                         };
 105                 };
 106         };