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1 Renesas AHB to PCI bridge
2 -------------------------
3
4 This is the bridge used internally to connect the USB controllers to the
5 AHB. There is one bridge instance per USB port connected to the internal
6 OHCI and EHCI controllers.
7
8 Required properties:
9 - compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
10 "renesas,pci-r8a7791" for the R8A7791 SoC.
11 - reg: A list of physical regions to access the device: the first is
12 the operational registers for the OHCI/EHCI controllers and the
13 second is for the bridge configuration and control registers.
14 - interrupts: interrupt for the device.
15 - clocks: The reference to the device clock.
16 - bus-range: The PCI bus number range; as this is a single bus, the range
17 should be specified as the same value twice.
18 - #address-cells: must be 3.
19 - #size-cells: must be 2.
20 - #interrupt-cells: must be 1.
21 - interrupt-map: standard property used to define the mapping of the PCI
22 interrupts to the GIC interrupts.
23 - interrupt-map-mask: standard property that helps to define the interrupt
24 mapping.
25
26 Example SoC configuration:
27
28 pci0: pci@ee090000 {
29 compatible = "renesas,pci-r8a7790";
30 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
31 reg = <0x0 0xee090000 0x0 0xc00>,
32 <0x0 0xee080000 0x0 0x1100>;
33 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
34 status = "disabled";
35
36 bus-range = <0 0>;
37 #address-cells = <3>;
38 #size-cells = <2>;
39 #interrupt-cells = <1>;
40 interrupt-map-mask = <0xff00 0 0 0x7>;
41 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
42 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
43 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
44
45 pci@0,1 {
46 reg = <0x800 0 0 0 0>;
47 device_type = "pci";
48 phys = <&usbphy 0 0>;
49 phy-names = "usb";
50 };
51
52 pci@0,2 {
53 reg = <0x1000 0 0 0 0>;
54 device_type = "pci";
55 phys = <&usbphy 0 0>;
56 phy-names = "usb";
57 };
58 };
59
60 Example board setup:
61
62 &pci0 {
63 status = "okay";
64 pinctrl-0 = <&usb0_pins>;
65 pinctrl-names = "default";
66 };