Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

   1 Qualcomm QMP PHY controller
   2 ===========================
   3
   4 QMP phy controller supports physical layer functionality for a number of
   5 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
   6
   7 Required properties:
   8  - compatible: compatible list, contains:
   9                "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
  10                "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
  11
  12  - reg: offset and length of register set for PHY's common serdes block.
  13
  14  - #clock-cells: must be 1
  15     - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
  16       interface (for pipe based PHYs). These clock are then gate-controlled
  17       by gcc.
  18  - #address-cells: must be 1
  19  - #size-cells: must be 1
  20  - ranges: must be present
  21
  22  - clocks: a list of phandles and clock-specifier pairs,
  23            one for each entry in clock-names.
  24  - clock-names: "cfg_ahb" for phy config clock,
  25                 "aux" for phy aux clock,
  26                 "ref" for 19.2 MHz ref clk,
  27                 For "qcom,msm8996-qmp-pcie-phy" must contain:
  28                         "aux", "cfg_ahb", "ref".
  29                 For "qcom,msm8996-qmp-usb3-phy" must contain:
  30                         "aux", "cfg_ahb", "ref".
  31
  32  - resets: a list of phandles and reset controller specifier pairs,
  33            one for each entry in reset-names.
  34  - reset-names: "phy" for reset of phy block,
  35                 "common" for phy common block reset,
  36                 "cfg" for phy's ahb cfg block reset (Optional).
  37                 For "qcom,msm8996-qmp-pcie-phy" must contain:
  38                  "phy", "common", "cfg".
  39                 For "qcom,msm8996-qmp-usb3-phy" must contain
  40                  "phy", "common".
  41
  42  - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
  43  - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
  44
  45 Optional properties:
  46  - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
  47                         pll block.
  48
  49 Required nodes:
  50  - Each device node of QMP phy is required to have as many child nodes as
  51    the number of lanes the PHY has.
  52
  53 Required properties for child node:
  54  - reg: list of offset and length pairs of register sets for PHY blocks -
  55         tx, rx and pcs.
  56
  57  - #phy-cells: must be 0
  58
  59  - clocks: a list of phandles and clock-specifier pairs,
  60            one for each entry in clock-names.
  61  - clock-names: Must contain following for pcie and usb qmp phys:
  62                  "pipe<lane-number>" for pipe clock specific to each lane.
  63
  64  - resets: a list of phandles and reset controller specifier pairs,
  65            one for each entry in reset-names.
  66  - reset-names: Must contain following for pcie qmp phys:
  67                  "lane<lane-number>" for reset specific to each lane.
  68
  69 Example:
  70         phy@34000 {
  71                 compatible = "qcom,msm8996-qmp-pcie-phy";
  72                 reg = <0x34000 0x488>;
  73                 #clock-cells = <1>;
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77
  78                 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
  79                         <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
  80                         <&gcc GCC_PCIE_CLKREF_CLK>;
  81                 clock-names = "aux", "cfg_ahb", "ref";
  82
  83                 vdda-phy-supply = <&pm8994_l28>;
  84                 vdda-pll-supply = <&pm8994_l12>;
  85
  86                 resets = <&gcc GCC_PCIE_PHY_BCR>,
  87                         <&gcc GCC_PCIE_PHY_COM_BCR>,
  88                         <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
  89                 reset-names = "phy", "common", "cfg";
  90
  91                 pciephy_0: lane@35000 {
  92                         reg = <0x35000 0x130>,
  93                                 <0x35200 0x200>,
  94                                 <0x35400 0x1dc>;
  95                         #phy-cells = <0>;
  96
  97                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
  98                         clock-names = "pipe0";
  99                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 100                         reset-names = "lane0";
 101                 };
 102
 103                 pciephy_1: lane@36000 {
 104                 ...
 105                 ...
 106         };