Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt

   1 * Allwinner A1X Pin Controller
   2
   3 The pins controlled by sunXi pin controller are organized in banks,
   4 each bank has 32 pins.  Each pin has 7 multiplexing functions, with
   5 the first two functions being GPIO in and out. The configuration on
   6 the pins includes drive strength and pull-up.
   7
   8 Required properties:
   9 - compatible: Should be one of the followings (depending on you SoC):
  10   "allwinner,sun4i-a10-pinctrl"
  11   "allwinner,sun5i-a10s-pinctrl"
  12   "allwinner,sun5i-a13-pinctrl"
  13   "allwinner,sun6i-a31-pinctrl"
  14   "allwinner,sun6i-a31s-pinctrl"
  15   "allwinner,sun6i-a31-r-pinctrl"
  16   "allwinner,sun7i-a20-pinctrl"
  17   "allwinner,sun8i-a23-pinctrl"
  18   "allwinner,sun8i-a23-r-pinctrl"
  19   "allwinner,sun8i-a33-pinctrl"
  20   "allwinner,sun9i-a80-pinctrl"
  21   "allwinner,sun9i-a80-r-pinctrl"
  22   "allwinner,sun8i-a83t-pinctrl"
  23   "allwinner,sun8i-h3-pinctrl"
  24   "allwinner,sun8i-h3-r-pinctrl"
  25   "allwinner,sun50i-a64-pinctrl"
  26   "nextthing,gr8-pinctrl"
  27
  28 - reg: Should contain the register physical address and length for the
  29   pin controller.
  30
  31 - clocks: phandle to the clocks feeding the pin controller:
  32   - "apb": the gated APB parent clock
  33   - "hosc": the high frequency oscillator in the system
  34   - "losc": the low frequency oscillator in the system
  35
  36 Note: For backward compatibility reasons, the hosc and losc clocks are only
  37 required if you need to use the optional input-debounce property. Any new
  38 device tree should set them.
  39
  40 Optional properties:
  41   - input-debounce: Array of debouncing periods in microseconds. One period per
  42     irq bank found in the controller. 0 if no setup required.
  43
  44
  45 Please refer to pinctrl-bindings.txt in this directory for details of the
  46 common pinctrl bindings used by client devices.
  47
  48 A pinctrl node should contain at least one subnodes representing the
  49 pinctrl groups available on the machine. Each subnode will list the
  50 pins it needs, and how they should be configured, with regard to muxer
  51 configuration, drive strength and pullups. If one of these options is
  52 not set, its actual value will be unspecified.
  53
  54 This driver supports the generic pin multiplexing and configuration
  55 bindings. For details on each properties, you can refer to
  56 ./pinctrl-bindings.txt.
  57
  58 Required sub-node properties:
  59   - pins
  60   - function
  61
  62 Optional sub-node properties:
  63   - bias-disable
  64   - bias-pull-up
  65   - bias-pull-down
  66   - drive-strength
  67
  68 *** Deprecated pin configuration and multiplexing binding
  69
  70 Required subnode-properties:
  71
  72 - allwinner,pins: List of strings containing the pin name.
  73 - allwinner,function: Function to mux the pins listed above to.
  74
  75 Optional subnode-properties:
  76 - allwinner,drive: Integer. Represents the current sent to the pin
  77     0: 10 mA
  78     1: 20 mA
  79     2: 30 mA
  80     3: 40 mA
  81 - allwinner,pull: Integer.
  82     0: No resistor
  83     1: Pull-up resistor
  84     2: Pull-down resistor
  85
  86 Examples:
  87
  88 pio: pinctrl@01c20800 {
  89         compatible = "allwinner,sun5i-a13-pinctrl";
  90         reg = <0x01c20800 0x400>;
  91         #address-cells = <1>;
  92         #size-cells = <0>;
  93
  94         uart1_pins_a: uart1@0 {
  95                 allwinner,pins = "PE10", "PE11";
  96                 allwinner,function = "uart1";
  97                 allwinner,drive = <0>;
  98                 allwinner,pull = <0>;
  99         };
 100
 101         uart1_pins_b: uart1@1 {
 102                 allwinner,pins = "PG3", "PG4";
 103                 allwinner,function = "uart1";
 104                 allwinner,drive = <0>;
 105                 allwinner,pull = <0>;
 106         };
 107 };
 108
 109
 110 GPIO and interrupt controller
 111 -----------------------------
 112
 113 This hardware also acts as a GPIO controller and an interrupt
 114 controller.
 115
 116 Consumers that would want to refer to one or the other (or both)
 117 should provide through the usual *-gpios and interrupts properties a
 118 cell with 3 arguments, first the number of the bank, then the pin
 119 inside that bank, and finally the flags for the GPIO/interrupts.
 120
 121 Example:
 122
 123 xio: gpio@38 {
 124         compatible = "nxp,pcf8574a";
 125         reg = <0x38>;
 126
 127         gpio-controller;
 128         #gpio-cells = <2>;
 129
 130         interrupt-parent = <&pio>;
 131         interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
 132         interrupt-controller;
 133         #interrupt-cells = <2>;
 134 };
 135
 136 reg_usb1_vbus: usb1-vbus {
 137         compatible = "regulator-fixed";
 138         regulator-name = "usb1-vbus";
 139         regulator-min-microvolt = <5000000>;
 140         regulator-max-microvolt = <5000000>;
 141         gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
 142 };