Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Mediatek MT65xx Pin Controller Device Tree Bindings
   8
   9 maintainers:
  10   - Sean Wang <sean.wang@kernel.org>
  11
  12 description: |+
  13   The Mediatek's Pin controller is used to control SoC pins.
  14
  15 properties:
  16   compatible:
  17     enum:
  18       - mediatek,mt2701-pinctrl
  19       - mediatek,mt2712-pinctrl
  20       - mediatek,mt6397-pinctrl
  21       - mediatek,mt7623-pinctrl
  22       - mediatek,mt8127-pinctrl
  23       - mediatek,mt8135-pinctrl
  24       - mediatek,mt8167-pinctrl
  25       - mediatek,mt8173-pinctrl
  26       - mediatek,mt8516-pinctrl
  27
  28   reg:
  29     maxItems: 1
  30
  31   pins-are-numbered:
  32     $ref: /schemas/types.yaml#/definitions/flag
  33     description: |
  34       Specify the subnodes are using numbered pinmux to specify pins.
  35
  36   gpio-controller: true
  37
  38   "#gpio-cells":
  39     const: 2
  40     description: |
  41       Number of cells in GPIO specifier. Since the generic GPIO
  42       binding is used, the amount of cells must be specified as 2. See the below
  43       mentioned gpio binding representation for description of particular cells.
  44
  45   mediatek,pctl-regmap:
  46     $ref: /schemas/types.yaml#/definitions/phandle-array
  47     minItems: 1
  48     maxItems: 2
  49     description: |
  50       Should be phandles of the syscfg node.
  51
  52   interrupt-controller: true
  53
  54   interrupts:
  55     minItems: 1
  56     maxItems: 3
  57
  58   "#interrupt-cells":
  59     const: 2
  60
  61 required:
  62   - compatible
  63   - pins-are-numbered
  64   - gpio-controller
  65   - "#gpio-cells"
  66
  67 patternProperties:
  68   '-[0-9]+$':
  69     type: object
  70     additionalProperties: false
  71     patternProperties:
  72       'pins':
  73         type: object
  74         additionalProperties: false
  75         description: |
  76           A pinctrl node should contain at least one subnodes representing the
  77           pinctrl groups available on the machine. Each subnode will list the
  78           pins it needs, and how they should be configured, with regard to muxer
  79           configuration, pullups, drive strength, input enable/disable and input
  80           schmitt.
  81         $ref: "/schemas/pinctrl/pincfg-node.yaml"
  82
  83         properties:
  84           pinmux:
  85             description:
  86               integer array, represents gpio pin number and mux setting.
  87               Supported pin number and mux varies for different SoCs, and are
  88               defined as macros in <soc>-pinfunc.h directly.
  89
  90           bias-disable: true
  91
  92           bias-pull-up:
  93             description: |
  94               Besides generic pinconfig options, it can be used as the pull up
  95               settings for 2 pull resistors, R0 and R1. User can configure those
  96               special pins. Some macros have been defined for this usage, such
  97               as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
  98               valid arguments.
  99
 100           bias-pull-down: true
 101
 102           input-enable: true
 103
 104           input-disable: true
 105
 106           output-low: true
 107
 108           output-high: true
 109
 110           input-schmitt-enable: true
 111
 112           input-schmitt-disable: true
 113
 114           drive-strength:
 115             description: |
 116               Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
 117               etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
 118
 119         required:
 120           - pinmux
 121
 122 additionalProperties: false
 123
 124 examples:
 125   - |
 126     #include <dt-bindings/interrupt-controller/irq.h>
 127     #include <dt-bindings/interrupt-controller/arm-gic.h>
 128     #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
 129
 130     soc {
 131         #address-cells = <2>;
 132         #size-cells = <2>;
 133
 134         syscfg_pctl_a: syscfg-pctl-a@10005000 {
 135           compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
 136           reg = <0 0x10005000 0 0x1000>;
 137         };
 138
 139         syscfg_pctl_b: syscfg-pctl-b@1020c020 {
 140           compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
 141           reg = <0 0x1020C020 0 0x1000>;
 142         };
 143
 144         pinctrl@1c20800 {
 145           compatible = "mediatek,mt8135-pinctrl";
 146           reg = <0 0x1000B000 0 0x1000>;
 147           mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
 148           pins-are-numbered;
 149           gpio-controller;
 150           #gpio-cells = <2>;
 151           interrupt-controller;
 152           #interrupt-cells = <2>;
 153           interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 154               <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 155               <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 156
 157           i2c0_pins_a: i2c0-0 {
 158             pins1 {
 159               pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
 160                 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
 161               bias-disable;
 162             };
 163           };
 164
 165           i2c1_pins_a: i2c1-0 {
 166             pins {
 167               pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
 168                 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
 169               bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 170             };
 171           };
 172
 173           i2c2_pins_a: i2c2-0 {
 174             pins1 {
 175               pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
 176               bias-pull-down;
 177             };
 178
 179             pins2 {
 180               pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
 181               bias-pull-up;
 182             };
 183           };
 184
 185           i2c3_pins_a: i2c3-0 {
 186             pins1 {
 187               pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
 188                 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
 189               bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 190             };
 191
 192             pins2 {
 193               pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
 194                 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
 195               output-low;
 196               bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 197             };
 198
 199             pins3 {
 200               pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
 201                 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
 202               drive-strength = <32>;
 203             };
 204           };
 205         };
 206     };