Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt

   1 * Rockchip Pinmux Controller
   2
   3 The Rockchip Pinmux Controller, enables the IC
   4 to share one PAD to several functional blocks. The sharing is done by
   5 multiplexing the PAD input/output signals. For each PAD there are up to
   6 4 muxing options with option 0 being the use as a GPIO.
   7
   8 Please refer to pinctrl-bindings.txt in this directory for details of the
   9 common pinctrl bindings used by client devices, including the meaning of the
  10 phrase "pin configuration node".
  11
  12 The Rockchip pin configuration node is a node of a group of pins which can be
  13 used for a specific device or function. This node represents both mux and
  14 config of the pins in that group. The 'pins' selects the function mode(also
  15 named pin mode) this pin can work on and the 'config' configures various pad
  16 settings such as pull-up, etc.
  17
  18 The pins are grouped into up to 5 individual pin banks which need to be
  19 defined as gpio sub-nodes of the pinmux controller.
  20
  21 Required properties for iomux controller:
  22   - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
  23                        "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
  24   - rockchip,grf: phandle referencing a syscon providing the
  25          "general register files"
  26
  27 Optional properties for iomux controller:
  28   - rockchip,pmu: phandle referencing a syscon providing the pmu registers
  29          as some SoCs carry parts of the iomux controller registers there.
  30          Required for at least rk3188 and rk3288.
  31
  32 Deprecated properties for iomux controller:
  33   - reg: first element is the general register space of the iomux controller
  34          It should be large enough to contain also separate pull registers.
  35          second element is the separate pull register space of the rk3188.
  36          Use rockchip,grf and rockchip,pmu described above instead.
  37
  38 Required properties for gpio sub nodes:
  39   - compatible: "rockchip,gpio-bank", "rockchip,rk3188-gpio-bank0"
  40   - reg: register of the gpio bank (different than the iomux registerset)
  41   - interrupts: base interrupt of the gpio bank in the interrupt controller
  42   - clocks: clock that drives this bank
  43   - gpio-controller: identifies the node as a gpio controller and pin bank.
  44   - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
  45     binding is used, the amount of cells must be specified as 2. See generic
  46     GPIO binding documentation for description of particular cells.
  47   - interrupt-controller: identifies the controller node as interrupt-parent.
  48   - #interrupt-cells: the value of this property should be 2 and the interrupt
  49     cells should use the standard two-cell scheme described in
  50     bindings/interrupt-controller/interrupts.txt
  51
  52 Deprecated properties for gpio sub nodes:
  53   - reg: second element: separate pull register for rk3188 bank0, use
  54          rockchip,pmu described above instead
  55
  56 Required properties for pin configuration node:
  57   - rockchip,pins: 3 integers array, represents a group of pins mux and config
  58     setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
  59     The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
  60     The phandle of a node containing the generic pinconfig options
  61     to use, as described in pinctrl-bindings.txt in this directory.
  62
  63 Examples:
  64
  65 #include <dt-bindings/pinctrl/rockchip.h>
  66
  67 ...
  68
  69 pinctrl@20008000 {
  70         compatible = "rockchip,rk3066a-pinctrl";
  71         rockchip,grf = <&grf>;
  72
  73         #address-cells = <1>;
  74         #size-cells = <1>;
  75         ranges;
  76
  77         gpio0: gpio0@20034000 {
  78                 compatible = "rockchip,gpio-bank";
  79                 reg = <0x20034000 0x100>;
  80                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  81                 clocks = <&clk_gates8 9>;
  82
  83                 gpio-controller;
  84                 #gpio-cells = <2>;
  85
  86                 interrupt-controller;
  87                 #interrupt-cells = <2>;
  88         };
  89
  90         ...
  91
  92         pcfg_pull_default: pcfg_pull_default {
  93                 bias-pull-pin-default
  94         };
  95
  96         uart2 {
  97                 uart2_xfer: uart2-xfer {
  98                         rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
  99                                         <RK_GPIO1 9 1 &pcfg_pull_default>;
 100                 };
 101         };
 102 };
 103
 104 uart2: serial@20064000 {
 105         compatible = "snps,dw-apb-uart";
 106         reg = <0x20064000 0x400>;
 107         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 108         reg-shift = <2>;
 109         reg-io-width = <1>;
 110         clocks = <&mux_uart2>;
 111         status = "okay";
 112
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&uart2_xfer>;
 115 };
 116
 117 Example for rk3188:
 118
 119         pinctrl@20008000 {
 120                 compatible = "rockchip,rk3188-pinctrl";
 121                 rockchip,grf = <&grf>;
 122                 rockchip,pmu = <&pmu>;
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 ranges;
 126
 127                 gpio0: gpio0@0x2000a000 {
 128                         compatible = "rockchip,rk3188-gpio-bank0";
 129                         reg = <0x2000a000 0x100>;
 130                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 131                         clocks = <&clk_gates8 9>;
 132
 133                         gpio-controller;
 134                         #gpio-cells = <2>;
 135
 136                         interrupt-controller;
 137                         #interrupt-cells = <2>;
 138                 };
 139
 140                 gpio1: gpio1@0x2003c000 {
 141                         compatible = "rockchip,gpio-bank";
 142                         reg = <0x2003c000 0x100>;
 143                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 144                         clocks = <&clk_gates8 10>;
 145
 146                         gpio-controller;
 147                         #gpio-cells = <2>;
 148
 149                         interrupt-controller;
 150                         #interrupt-cells = <2>;
 151                 };
 152
 153                 ...
 154
 155         };