Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt

   1 * Pin configuration for TI IODELAY controller
   2
   3 TI dra7 based SoCs such as am57xx have a controller for setting the IO delay
   4 for each pin. For most part the IO delay values are programmed by the bootloader,
   5 but some pins need to be configured dynamically by the kernel such as the
   6 MMC pins.
   7
   8 Required Properties:
   9
  10   - compatible: Must be "ti,dra7-iodelay"
  11   - reg: Base address and length of the memory resource used
  12   - #address-cells: Number of address cells
  13   - #size-cells: Size of cells
  14   - #pinctrl-cells: Number of pinctrl cells, must be 2. See also
  15     Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
  16
  17 Example
  18 -------
  19
  20 In the SoC specific dtsi file:
  21
  22         dra7_iodelay_core: padconf@4844a000 {
  23                 compatible = "ti,dra7-iodelay";
  24                 reg = <0x4844a000 0x0d1c>;
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 #pinctrl-cells = <2>;
  28         };
  29
  30 In board-specific file:
  31
  32 &dra7_iodelay_core {
  33         mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf {
  34                 pinctrl-pin-array = <
  35                 0x18c A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_A19_IN */
  36                 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360)   /* CFG_GPMC_A20_IN */
  37                 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_A21_IN */
  38                 0x1bc A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_A22_IN */
  39                 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420)   /* CFG_GPMC_A23_IN */
  40                 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240)   /* CFG_GPMC_A24_IN */
  41                 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_IN */
  42                 0x1ec A_DELAY_PS(120) G_DELAY_PS(0)     /* CFG_GPMC_A26_IN */
  43                 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180)   /* CFG_GPMC_A27_IN */
  44                 0x360 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_CS1_IN */
  45                 >;
  46         };
  47 };