Documentation/devicetree/bindings/scsi/hisilicon-sas.txt

   1 * HiSilicon SAS controller
   2
   3 The HiSilicon SAS controller supports SAS/SATA.
   4
   5 Main node required properties:
   6   - compatible : value should be as follows:
   7         (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
   8         (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
   9         (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
  10   - sas-addr : array of 8 bytes for host SAS address
  11   - reg : Address and length of the SAS register
  12   - hisilicon,sas-syscon: phandle of syscon used for sas control
  13   - ctrl-reset-reg : offset to controller reset register in ctrl reg
  14   - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
  15   - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
  16   - queue-count : number of delivery and completion queues in the controller
  17   - phy-count : number of phys accessible by the controller
  18   - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal
  19                 sources; the interrupts are ordered in 3 groups, as follows:
  20                         - Phy interrupts
  21                         - Completion queue interrupts
  22                         - Fatal interrupts
  23                 Phy interrupts : Each phy has 3 interrupt sources:
  24                         - broadcast
  25                         - phyup
  26                         - abnormal
  27                 The phy interrupts are ordered into groups of 3 per phy
  28                 (broadcast, phyup, and abnormal) in increasing order.
  29                 Completion queue interrupts : each completion queue has 1
  30                         interrupt source.
  31                         The interrupts are ordered in increasing order.
  32                 Fatal interrupts : the fatal interrupts are ordered as follows:
  33                         - ECC
  34                         - AXI bus
  35                 For v2 hw: Interrupts for phys, Sata, and completion queues;
  36                 the interrupts are ordered in 3 groups, as follows:
  37                         - Phy interrupts
  38                         - Sata interrupts
  39                         - Completion queue interrupts
  40                 Phy interrupts : Each controller has 2 phy interrupts:
  41                         - phy up/down
  42                         - channel interrupt
  43                 Sata interrupts : Each phy on the controller has 1 Sata
  44                         interrupt. The interrupts are ordered in increasing
  45                         order.
  46                 Completion queue interrupts : each completion queue has 1
  47                         interrupt source. The interrupts are ordered in
  48                         increasing order.
  49
  50 Optional main node properties:
  51  - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the
  52                             "am-max-transmissions" limitation.
  53
  54 Example:
  55         sas0: sas@c1000000 {
  56                 compatible = "hisilicon,hip05-sas-v1";
  57                 sas-addr = [50 01 88 20 16 00 00 0a];
  58                 reg = <0x0 0xc1000000 0x0 0x10000>;
  59                 hisilicon,sas-syscon = <&pcie_sas>;
  60                 ctrl-reset-reg = <0xa60>;
  61                 ctrl-reset-sts-reg = <0x5a30>;
  62                 ctrl-clock-ena-reg = <0x338>;
  63                 queue-count = <32>;
  64                 phy-count = <8>;
  65                 dma-coherent;
  66                 interrupt-parent = <&mbigen_dsa>;
  67                 interrupts =    <259 4>,<263 4>,<264 4>,/* phy0 */
  68                                 <269 4>,<273 4>,<274 4>,/* phy1 */
  69                                 <279 4>,<283 4>,<284 4>,/* phy2 */
  70                                 <289 4>,<293 4>,<294 4>,/* phy3 */
  71                                 <299 4>,<303 4>,<304 4>,/* phy4 */
  72                                 <309 4>,<313 4>,<314 4>,/* phy5 */
  73                                 <319 4>,<323 4>,<324 4>,/* phy6 */
  74                                 <329 4>,<333 4>,<334 4>,/* phy7 */
  75                                 <336 1>,<337 1>,<338 1>,/* cq0-2 */
  76                                 <339 1>,<340 1>,<341 1>,/* cq3-5 */
  77                                 <342 1>,<343 1>,<344 1>,/* cq6-8 */
  78                                 <345 1>,<346 1>,<347 1>,/* cq9-11 */
  79                                 <348 1>,<349 1>,<350 1>,/* cq12-14 */
  80                                 <351 1>,<352 1>,<353 1>,/* cq15-17 */
  81                                 <354 1>,<355 1>,<356 1>,/* cq18-20 */
  82                                 <357 1>,<358 1>,<359 1>,/* cq21-23 */
  83                                 <360 1>,<361 1>,<362 1>,/* cq24-26 */
  84                                 <363 1>,<364 1>,<365 1>,/* cq27-29 */
  85                                 <366 1>,<367 1>/* cq30-31 */
  86                                 <376 4>,/* fatal ecc */
  87                                 <381 4>;/* fatal axi */
  88                 status = "disabled";
  89         };