1 * Allwinner A10 I2S controller
3 The I2S bus (Inter-IC sound bus) is a serial link for digital
4 audio data transfer between devices in the system.
8 - compatible: should be one of the following:
9 - "allwinner,sun4i-a10-i2s"
10 - "allwinner,sun6i-a31-i2s"
11 - "allwinner,sun8i-h3-i2s"
12 - reg: physical base address of the controller and length of memory mapped
14 - interrupts: should contain the I2S interrupt.
15 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
16 Documentation/devicetree/bindings/dma/dma.txt
17 - dma-names: should include "tx" and "rx".
18 - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
19 - clock-names: should contain the following:
20 - "apb" : clock for the I2S bus interface
21 - "mod" : module clock for the I2S controller
22 - #sound-dai-cells : Must be equal to 0
24 Required properties for the following compatibles:
25 - "allwinner,sun6i-a31-i2s"
26 - "allwinner,sun8i-h3-i2s"
27 - resets: phandle to the reset line for this codec
32 #sound-dai-cells = <0>;
33 compatible = "allwinner,sun4i-a10-i2s";
34 reg = <0x01c22400 0x400>;
35 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
36 clocks = <&apb0_gates 3>, <&i2s0_clk>;
37 clock-names = "apb", "mod";
38 dmas = <&dma SUN4I_DMA_NORMAL 3>,
39 <&dma SUN4I_DMA_NORMAL 3>;
40 dma-names = "rx", "tx";