Documentation/devicetree/bindings/spi/qcom,spi-qup.txt

   1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
   2
   3 The QUP core is an AHB slave that provides a common data path (an output FIFO
   4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
   5
   6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
   7 data path from 4 bits to 32 bits and numerous protocol variants.
   8
   9 Required properties:
  10 - compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
  11 - reg:            Should contain base register location and length
  12 - interrupts:     Interrupt number used by this controller
  13
  14 - clocks:         Should contain the core clock and the AHB clock.
  15 - clock-names:    Should be "core" for the core clock and "iface" for the
  16                   AHB clock.
  17
  18 - #address-cells: Number of cells required to define a chip select
  19                   address on the SPI bus. Should be set to 1.
  20 - #size-cells:    Should be zero.
  21
  22 Optional properties:
  23 - spi-max-frequency: Specifies maximum SPI clock frequency,
  24                      Units - Hz. Definition as per
  25                      Documentation/devicetree/bindings/spi/spi-bus.txt
  26 - num-cs:       total number of chipselects
  27 - cs-gpios:     should specify GPIOs used for chipselects.
  28                 The gpios will be referred to as reg = <index> in the SPI child
  29                 nodes.  If unspecified, a single SPI device without a chip
  30                 select can be used.
  31
  32
  33 SPI slave nodes must be children of the SPI master node and can contain
  34 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
  35
  36 Example:
  37
  38         spi_8: spi@f9964000 { /* BLSP2 QUP2 */
  39
  40                 compatible = "qcom,spi-qup-v2";
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43                 reg = <0xf9964000 0x1000>;
  44                 interrupts = <0 102 0>;
  45                 spi-max-frequency = <19200000>;
  46
  47                 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  48                 clock-names = "core", "iface";
  49
  50                 pinctrl-names = "default";
  51                 pinctrl-0 = <&spi8_default>;
  52
  53                 device@0 {
  54                         compatible = "arm,pl022-dummy";
  55                         #address-cells = <1>;
  56                         #size-cells = <1>;
  57                         reg = <0>; /* Chip select 0 */
  58                         spi-max-frequency = <19200000>;
  59                         spi-cpol;
  60                 };
  61
  62                 device@1 {
  63                         compatible = "arm,pl022-dummy";
  64                         #address-cells = <1>;
  65                         #size-cells = <1>;
  66                         reg = <1>; /* Chip select 1 */
  67                         spi-max-frequency = <9600000>;
  68                         spi-cpha;
  69                 };
  70
  71                 device@2 {
  72                         compatible = "arm,pl022-dummy";
  73                         #address-cells = <1>;
  74                         #size-cells = <1>;
  75                         reg = <2>; /* Chip select 2 */
  76                         spi-max-frequency = <19200000>;
  77                         spi-cpol;
  78                         spi-cpha;
  79                 };
  80
  81                 device@3 {
  82                         compatible = "arm,pl022-dummy";
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85                         reg = <3>; /* Chip select 3 */
  86                         spi-max-frequency = <19200000>;
  87                         spi-cpol;
  88                         spi-cpha;
  89                         spi-cs-high;
  90                 };
  91         };