Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt

   1 Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
   2
   3 Required properties:
   4 - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
   5   "jaguar2", or "amazon,alpine-dw-apb-ssi"
   6 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
   7   register set is required (named ICPU_CFG:SPI_MST)
   8 - interrupts : One interrupt, used by the controller.
   9 - #address-cells : <1>, as required by generic SPI binding.
  10 - #size-cells : <0>, also as required by generic SPI binding.
  11 - clocks : phandles for the clocks, see the description of clock-names below.
  12    The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
  13    is optional. If a single clock is specified but no clock-name, it is the
  14    "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
  15
  16 Optional properties:
  17 - clock-names : Contains the names of the clocks:
  18     "ssi_clk", for the core clock used to generate the external SPI clock.
  19     "pclk", the interface clock, required for register access. If a clock domain
  20      used to enable this clock then it should be named "pclk_clkdomain".
  21 - cs-gpios : Specifies the gpio pins to be used for chipselects.
  22 - num-cs : The number of chipselects. If omitted, this will default to 4.
  23 - reg-io-width : The I/O register width (in bytes) implemented by this
  24   device.  Supported values are 2 or 4 (the default).
  25
  26 Child nodes as per the generic SPI binding.
  27
  28 Example:
  29
  30         spi@fff00000 {
  31                 compatible = "snps,dw-apb-ssi";
  32                 reg = <0xfff00000 0x1000>;
  33                 interrupts = <0 154 4>;
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36                 clocks = <&spi_m_clk>;
  37                 num-cs = <2>;
  38                 cs-gpios = <&gpio0 13 0>,
  39                            <&gpio0 14 0>;
  40         };
  41