Documentation/devicetree/bindings/spi/spi-davinci.txt

   1 Davinci SPI controller device bindings
   2
   3 Links on DM:
   4 Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
   5 dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
   6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
   7
   8 Required properties:
   9 - #address-cells: number of cells required to define a chip select
  10         address on the SPI bus. Should be set to 1.
  11 - #size-cells: should be zero.
  12 - compatible:
  13         - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
  14         - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
  15 - reg: Offset and length of SPI controller register space
  16 - num-cs: Number of chip selects. This includes internal as well as
  17         GPIO chip selects.
  18 - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
  19         IP to the interrupt controller within the SoC. Possible values
  20         are 0 and 1. Manual says one of the two possible interrupt
  21         lines can be tied to the interrupt controller. Set this
  22         based on a specifc SoC configuration.
  23 - interrupts: interrupt number mapped to CPU.
  24 - clocks: spi clk phandle
  25
  26 Optional:
  27 - cs-gpios: gpio chip selects
  28         For example to have 3 internal CS and 2 GPIO CS, user could define
  29         cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
  30         where first three are internal CS and last two are GPIO CS.
  31
  32 Optional properties for slave devices:
  33 SPI slave nodes can contain the following properties.
  34 Not all SPI Peripherals from Texas Instruments support this.
  35 Please check SPI peripheral documentation for a device before using these.
  36
  37 - ti,spi-wdelay : delay between transmission of words
  38         (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
  39         clock periods.
  40
  41         delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period
  42
  43 Below is timing diagram which shows functional meaning of
  44 "ti,spi-wdelay" parameter.
  45
  46              +-+ +-+ +-+ +-+ +-+                           +-+ +-+ +-+
  47 SPI_CLK      | | | | | | | | | |                           | | | | | |
  48   +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
  49
  50 SPI_SOMI/SIMO+-----------------+                           +-----------
  51   +----------+ word1           +---------------------------+word2
  52              +-----------------+                           +-----------
  53                                           WDELAY
  54                                 <-------------------------->
  55
  56 Example of a NOR flash slave device (n25q032) connected to DaVinci
  57 SPI controller device over the SPI bus.
  58
  59 spi0:spi@20BF0000 {
  60         #address-cells                  = <1>;
  61         #size-cells                     = <0>;
  62         compatible                      = "ti,dm6446-spi";
  63         reg                             = <0x20BF0000 0x1000>;
  64         num-cs                          = <4>;
  65         ti,davinci-spi-intr-line        = <0>;
  66         interrupts                      = <338>;
  67         clocks                          = <&clkspi>;
  68
  69         flash: n25q032@0 {
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 compatible = "st,m25p32";
  73                 spi-max-frequency = <25000000>;
  74                 reg = <0>;
  75                 ti,spi-wdelay = <8>;
  76
  77                 partition@0 {
  78                         label = "u-boot-spl";
  79                         reg = <0x0 0x80000>;
  80                         read-only;
  81                 };
  82
  83                 partition@1 {
  84                         label = "test";
  85                         reg = <0x80000 0x380000>;
  86                 };
  87         };
  88 };