Documentation/devicetree/bindings/ufs/ufs-qcom.txt

   1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
   2
   3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
   4 Each UFS PHY node should have its own node.
   5
   6 To bind UFS PHY with UFS host controller, the controller node should
   7 contain a phandle reference to UFS PHY node.
   8
   9 Required properties:
  10 - compatible        : compatible list, contains one of the following -
  11                         "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
  12                         "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
  13                         "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
  14                          present on MSM8996 chipset.
  15 - reg               : should contain PHY register address space (mandatory),
  16 - reg-names         : indicates various resources passed to driver (via reg proptery) by name.
  17                       Required "reg-names" is "phy_mem".
  18 - #phy-cells        : This property shall be set to 0
  19 - vdda-phy-supply   : phandle to main PHY supply for analog domain
  20 - vdda-pll-supply   : phandle to PHY PLL and Power-Gen block power supply
  21 - clocks            : List of phandle and clock specifier pairs
  22 - clock-names       : List of clock input name strings sorted in the same
  23                       order as the clocks property. "ref_clk_src", "ref_clk",
  24                       "tx_iface_clk" & "rx_iface_clk" are mandatory but
  25                       "ref_clk_parent" is optional
  26
  27 Optional properties:
  28 - vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply
  29 - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
  30 - vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply
  31 - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
  32
  33 Example:
  34
  35         ufsphy1: ufsphy@0xfc597000 {
  36                 compatible = "qcom,ufs-phy-qmp-20nm";
  37                 reg = <0xfc597000 0x800>;
  38                 reg-names = "phy_mem";
  39                 #phy-cells = <0>;
  40                 vdda-phy-supply = <&pma8084_l4>;
  41                 vdda-pll-supply = <&pma8084_l12>;
  42                 vdda-phy-max-microamp = <50000>;
  43                 vdda-pll-max-microamp = <1000>;
  44                 clock-names = "ref_clk_src",
  45                         "ref_clk_parent",
  46                         "ref_clk",
  47                         "tx_iface_clk",
  48                         "rx_iface_clk";
  49                 clocks = <&clock_rpm clk_ln_bb_clk>,
  50                         <&clock_gcc clk_pcie_1_phy_ldo >,
  51                         <&clock_gcc clk_ufs_phy_ldo>,
  52                         <&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
  53                         <&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
  54         };
  55
  56         ufshc@0xfc598000 {
  57                 ...
  58                 phys = <&ufsphy1>;
  59                 phy-names = "ufsphy";
  60         };