Documentation/scsi/hptiop.rst

   1 .. SPDX-License-Identifier: GPL-2.0
   2 .. include:: <isonum.txt>
   3
   4 ======================================================
   5 Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop)
   6 ======================================================
   7
   8 Controller Register Map
   9 -----------------------
  10
  11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
  12
  13      ============== ==================================
  14      BAR0 offset    Register
  15      ============== ==================================
  16             0x11C5C Link Interface IRQ Set
  17             0x11C60 Link Interface IRQ Clear
  18      ============== ==================================
  19
  20      ============== ==================================
  21      BAR2 offset    Register
  22      ============== ==================================
  23             0x10    Inbound Message Register 0
  24             0x14    Inbound Message Register 1
  25             0x18    Outbound Message Register 0
  26             0x1C    Outbound Message Register 1
  27             0x20    Inbound Doorbell Register
  28             0x24    Inbound Interrupt Status Register
  29             0x28    Inbound Interrupt Mask Register
  30             0x30    Outbound Interrupt Status Register
  31             0x34    Outbound Interrupt Mask Register
  32             0x40    Inbound Queue Port
  33             0x44    Outbound Queue Port
  34      ============== ==================================
  35
  36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
  37
  38      ============== ==================================
  39      BAR0 offset    Register
  40      ============== ==================================
  41             0x10    Inbound Message Register 0
  42             0x14    Inbound Message Register 1
  43             0x18    Outbound Message Register 0
  44             0x1C    Outbound Message Register 1
  45             0x20    Inbound Doorbell Register
  46             0x24    Inbound Interrupt Status Register
  47             0x28    Inbound Interrupt Mask Register
  48             0x30    Outbound Interrupt Status Register
  49             0x34    Outbound Interrupt Mask Register
  50             0x40    Inbound Queue Port
  51             0x44    Outbound Queue Port
  52      ============== ==================================
  53
  54 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
  55
  56      ============== ==================================
  57      BAR0 offset    Register
  58      ============== ==================================
  59          0x20400    Inbound Doorbell Register
  60          0x20404    Inbound Interrupt Mask Register
  61          0x20408    Outbound Doorbell Register
  62          0x2040C    Outbound Interrupt Mask Register
  63      ============== ==================================
  64
  65      ============== ==================================
  66      BAR1 offset    Register
  67      ============== ==================================
  68              0x0    Inbound Queue Head Pointer
  69              0x4    Inbound Queue Tail Pointer
  70              0x8    Outbound Queue Head Pointer
  71              0xC    Outbound Queue Tail Pointer
  72             0x10    Inbound Message Register
  73             0x14    Outbound Message Register
  74      0x40-0x1040    Inbound Queue
  75      0x1040-0x2040  Outbound Queue
  76      ============== ==================================
  77
  78 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
  79
  80      ============== ==================================
  81      BAR0 offset    Register
  82      ============== ==================================
  83              0x0    IOP configuration information.
  84      ============== ==================================
  85
  86      ============== ===================================================
  87      BAR1 offset    Register
  88      ============== ===================================================
  89           0x4000    Inbound List Base Address Low
  90           0x4004    Inbound List Base Address High
  91           0x4018    Inbound List Write Pointer
  92           0x402C    Inbound List Configuration and Control
  93           0x4050    Outbound List Base Address Low
  94           0x4054    Outbound List Base Address High
  95           0x4058    Outbound List Copy Pointer Shadow Base Address Low
  96           0x405C    Outbound List Copy Pointer Shadow Base Address High
  97           0x4088    Outbound List Interrupt Cause
  98           0x408C    Outbound List Interrupt Enable
  99          0x1020C    PCIe Function 0 Interrupt Enable
 100          0x10400    PCIe Function 0 to CPU Message A
 101          0x10420    CPU to PCIe Function 0 Message A
 102          0x10480    CPU to PCIe Function 0 Doorbell
 103          0x10484    CPU to PCIe Function 0 Doorbell Enable
 104      ============== ===================================================
 105
 106
 107 I/O Request Workflow of Not Marvell Frey
 108 ----------------------------------------
 109
 110 All queued requests are handled via inbound/outbound queue port.
 111 A request packet can be allocated in either IOP or host memory.
 112
 113 To send a request to the controller:
 114
 115     - Get a free request packet by reading the inbound queue port or
 116       allocate a free request in host DMA coherent memory.
 117
 118       The value returned from the inbound queue port is an offset
 119       relative to the IOP BAR0.
 120
 121       Requests allocated in host memory must be aligned on 32-bytes boundary.
 122
 123     - Fill the packet.
 124
 125     - Post the packet to IOP by writing it to inbound queue. For requests
 126       allocated in IOP memory, write the offset to inbound queue port. For
 127       requests allocated in host memory, write (0x80000000|(bus_addr>>5))
 128       to the inbound queue port.
 129
 130     - The IOP process the request. When the request is completed, it
 131       will be put into outbound queue. An outbound interrupt will be
 132       generated.
 133
 134       For requests allocated in IOP memory, the request offset is posted to
 135       outbound queue.
 136
 137       For requests allocated in host memory, (0x80000000|(bus_addr>>5))
 138       is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT
 139       flag is set in the request, the low 32-bit context value will be
 140       posted instead.
 141
 142     - The host read the outbound queue and complete the request.
 143
 144       For requests allocated in IOP memory, the host driver free the request
 145       by writing it to the outbound queue.
 146
 147 Non-queued requests (reset/flush etc) can be sent via inbound message
 148 register 0. An outbound message with the same value indicates the completion
 149 of an inbound message.
 150
 151
 152 I/O Request Workflow of Marvell Frey
 153 ------------------------------------
 154
 155 All queued requests are handled via inbound/outbound list.
 156
 157 To send a request to the controller:
 158
 159     - Allocate a free request in host DMA coherent memory.
 160
 161       Requests allocated in host memory must be aligned on 32-bytes boundary.
 162
 163     - Fill the request with index of the request in the flag.
 164
 165       Fill a free inbound list unit with the physical address and the size of
 166       the request.
 167
 168       Set up the inbound list write pointer with the index of previous unit,
 169       round to 0 if the index reaches the supported count of requests.
 170
 171     - Post the inbound list writer pointer to IOP.
 172
 173     - The IOP process the request. When the request is completed, the flag of
 174       the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a
 175       free outbound list unit and the index of the outbound list unit will be
 176       put into the copy pointer shadow register. An outbound interrupt will be
 177       generated.
 178
 179     - The host read the outbound list copy pointer shadow register and compare
 180       with previous saved read pointer N. If they are different, the host will
 181       read the (N+1)th outbound list unit.
 182
 183       The host get the index of the request from the (N+1)th outbound list
 184       unit and complete the request.
 185
 186 Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe
 187 Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register
 188 with the same value indicates the completion of message.
 189
 190
 191 User-level Interface
 192 ---------------------
 193
 194 The driver exposes following sysfs attributes:
 195
 196      ==================   ===    ========================
 197      NAME                 R/W    Description
 198      ==================   ===    ========================
 199      driver-version        R     driver version string
 200      firmware-version      R     firmware version string
 201      ==================   ===    ========================
 202
 203
 204 -----------------------------------------------------------------------------
 205
 206 Copyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.
 207
 208   This file is distributed in the hope that it will be useful,
 209   but WITHOUT ANY WARRANTY; without even the implied warranty of
 210   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 211   GNU General Public License for more details.
 212
 213   linux@highpoint-tech.com
 214
 215   http://www.highpoint-tech.com