2 * Common CPU TLB handling
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
22 #include "hw/core/tcg-cpu-ops.h"
23 #include "exec/exec-all.h"
24 #include "exec/memory.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/cputlb.h"
27 #include "exec/memory-internal.h"
28 #include "exec/ram_addr.h"
30 #include "qemu/error-report.h"
32 #include "exec/helper-proto-common.h"
33 #include "qemu/atomic.h"
34 #include "qemu/atomic128.h"
35 #include "exec/translate-all.h"
40 #include "qemu/plugin-memory.h"
42 #include "tcg/tcg-ldst.h"
43 #include "tcg/oversized-guest.h"
45 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
46 /* #define DEBUG_TLB */
47 /* #define DEBUG_TLB_LOG */
50 # define DEBUG_TLB_GATE 1
52 # define DEBUG_TLB_LOG_GATE 1
54 # define DEBUG_TLB_LOG_GATE 0
57 # define DEBUG_TLB_GATE 0
58 # define DEBUG_TLB_LOG_GATE 0
61 #define tlb_debug(fmt, ...) do { \
62 if (DEBUG_TLB_LOG_GATE) { \
63 qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
65 } else if (DEBUG_TLB_GATE) { \
66 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
70 #define assert_cpu_is_self(cpu) do { \
71 if (DEBUG_TLB_GATE) { \
72 g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \
76 /* run_on_cpu_data.target_ptr should always be big enough for a
77 * vaddr even on 32 bit builds
79 QEMU_BUILD_BUG_ON(sizeof(vaddr
) > sizeof(run_on_cpu_data
));
81 /* We currently can't handle more than 16 bits in the MMUIDX bitmask.
83 QEMU_BUILD_BUG_ON(NB_MMU_MODES
> 16);
84 #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
86 static inline size_t tlb_n_entries(CPUTLBDescFast
*fast
)
88 return (fast
->mask
>> CPU_TLB_ENTRY_BITS
) + 1;
91 static inline size_t sizeof_tlb(CPUTLBDescFast
*fast
)
93 return fast
->mask
+ (1 << CPU_TLB_ENTRY_BITS
);
96 static void tlb_window_reset(CPUTLBDesc
*desc
, int64_t ns
,
99 desc
->window_begin_ns
= ns
;
100 desc
->window_max_entries
= max_entries
;
103 static void tb_jmp_cache_clear_page(CPUState
*cpu
, vaddr page_addr
)
105 CPUJumpCache
*jc
= cpu
->tb_jmp_cache
;
112 i0
= tb_jmp_cache_hash_page(page_addr
);
113 for (i
= 0; i
< TB_JMP_PAGE_SIZE
; i
++) {
114 qatomic_set(&jc
->array
[i0
+ i
].tb
, NULL
);
119 * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
120 * @desc: The CPUTLBDesc portion of the TLB
121 * @fast: The CPUTLBDescFast portion of the same TLB
123 * Called with tlb_lock_held.
125 * We have two main constraints when resizing a TLB: (1) we only resize it
126 * on a TLB flush (otherwise we'd have to take a perf hit by either rehashing
127 * the array or unnecessarily flushing it), which means we do not control how
128 * frequently the resizing can occur; (2) we don't have access to the guest's
129 * future scheduling decisions, and therefore have to decide the magnitude of
130 * the resize based on past observations.
132 * In general, a memory-hungry process can benefit greatly from an appropriately
133 * sized TLB, since a guest TLB miss is very expensive. This doesn't mean that
134 * we just have to make the TLB as large as possible; while an oversized TLB
135 * results in minimal TLB miss rates, it also takes longer to be flushed
136 * (flushes can be _very_ frequent), and the reduced locality can also hurt
139 * To achieve near-optimal performance for all kinds of workloads, we:
141 * 1. Aggressively increase the size of the TLB when the use rate of the
142 * TLB being flushed is high, since it is likely that in the near future this
143 * memory-hungry process will execute again, and its memory hungriness will
144 * probably be similar.
146 * 2. Slowly reduce the size of the TLB as the use rate declines over a
147 * reasonably large time window. The rationale is that if in such a time window
148 * we have not observed a high TLB use rate, it is likely that we won't observe
149 * it in the near future. In that case, once a time window expires we downsize
150 * the TLB to match the maximum use rate observed in the window.
152 * 3. Try to keep the maximum use rate in a time window in the 30-70% range,
153 * since in that range performance is likely near-optimal. Recall that the TLB
154 * is direct mapped, so we want the use rate to be low (or at least not too
155 * high), since otherwise we are likely to have a significant amount of
158 static void tlb_mmu_resize_locked(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
,
161 size_t old_size
= tlb_n_entries(fast
);
163 size_t new_size
= old_size
;
164 int64_t window_len_ms
= 100;
165 int64_t window_len_ns
= window_len_ms
* 1000 * 1000;
166 bool window_expired
= now
> desc
->window_begin_ns
+ window_len_ns
;
168 if (desc
->n_used_entries
> desc
->window_max_entries
) {
169 desc
->window_max_entries
= desc
->n_used_entries
;
171 rate
= desc
->window_max_entries
* 100 / old_size
;
174 new_size
= MIN(old_size
<< 1, 1 << CPU_TLB_DYN_MAX_BITS
);
175 } else if (rate
< 30 && window_expired
) {
176 size_t ceil
= pow2ceil(desc
->window_max_entries
);
177 size_t expected_rate
= desc
->window_max_entries
* 100 / ceil
;
180 * Avoid undersizing when the max number of entries seen is just below
181 * a pow2. For instance, if max_entries == 1025, the expected use rate
182 * would be 1025/2048==50%. However, if max_entries == 1023, we'd get
183 * 1023/1024==99.9% use rate, so we'd likely end up doubling the size
184 * later. Thus, make sure that the expected use rate remains below 70%.
185 * (and since we double the size, that means the lowest rate we'd
186 * expect to get is 35%, which is still in the 30-70% range where
187 * we consider that the size is appropriate.)
189 if (expected_rate
> 70) {
192 new_size
= MAX(ceil
, 1 << CPU_TLB_DYN_MIN_BITS
);
195 if (new_size
== old_size
) {
196 if (window_expired
) {
197 tlb_window_reset(desc
, now
, desc
->n_used_entries
);
203 g_free(desc
->fulltlb
);
205 tlb_window_reset(desc
, now
, 0);
206 /* desc->n_used_entries is cleared by the caller */
207 fast
->mask
= (new_size
- 1) << CPU_TLB_ENTRY_BITS
;
208 fast
->table
= g_try_new(CPUTLBEntry
, new_size
);
209 desc
->fulltlb
= g_try_new(CPUTLBEntryFull
, new_size
);
212 * If the allocations fail, try smaller sizes. We just freed some
213 * memory, so going back to half of new_size has a good chance of working.
214 * Increased memory pressure elsewhere in the system might cause the
215 * allocations to fail though, so we progressively reduce the allocation
216 * size, aborting if we cannot even allocate the smallest TLB we support.
218 while (fast
->table
== NULL
|| desc
->fulltlb
== NULL
) {
219 if (new_size
== (1 << CPU_TLB_DYN_MIN_BITS
)) {
220 error_report("%s: %s", __func__
, strerror(errno
));
223 new_size
= MAX(new_size
>> 1, 1 << CPU_TLB_DYN_MIN_BITS
);
224 fast
->mask
= (new_size
- 1) << CPU_TLB_ENTRY_BITS
;
227 g_free(desc
->fulltlb
);
228 fast
->table
= g_try_new(CPUTLBEntry
, new_size
);
229 desc
->fulltlb
= g_try_new(CPUTLBEntryFull
, new_size
);
233 static void tlb_mmu_flush_locked(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
)
235 desc
->n_used_entries
= 0;
236 desc
->large_page_addr
= -1;
237 desc
->large_page_mask
= -1;
239 memset(fast
->table
, -1, sizeof_tlb(fast
));
240 memset(desc
->vtable
, -1, sizeof(desc
->vtable
));
243 static void tlb_flush_one_mmuidx_locked(CPUArchState
*env
, int mmu_idx
,
246 CPUTLBDesc
*desc
= &env_tlb(env
)->d
[mmu_idx
];
247 CPUTLBDescFast
*fast
= &env_tlb(env
)->f
[mmu_idx
];
249 tlb_mmu_resize_locked(desc
, fast
, now
);
250 tlb_mmu_flush_locked(desc
, fast
);
253 static void tlb_mmu_init(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
, int64_t now
)
255 size_t n_entries
= 1 << CPU_TLB_DYN_DEFAULT_BITS
;
257 tlb_window_reset(desc
, now
, 0);
258 desc
->n_used_entries
= 0;
259 fast
->mask
= (n_entries
- 1) << CPU_TLB_ENTRY_BITS
;
260 fast
->table
= g_new(CPUTLBEntry
, n_entries
);
261 desc
->fulltlb
= g_new(CPUTLBEntryFull
, n_entries
);
262 tlb_mmu_flush_locked(desc
, fast
);
265 static inline void tlb_n_used_entries_inc(CPUArchState
*env
, uintptr_t mmu_idx
)
267 env_tlb(env
)->d
[mmu_idx
].n_used_entries
++;
270 static inline void tlb_n_used_entries_dec(CPUArchState
*env
, uintptr_t mmu_idx
)
272 env_tlb(env
)->d
[mmu_idx
].n_used_entries
--;
275 void tlb_init(CPUState
*cpu
)
277 CPUArchState
*env
= cpu
->env_ptr
;
278 int64_t now
= get_clock_realtime();
281 qemu_spin_init(&env_tlb(env
)->c
.lock
);
283 /* All tlbs are initialized flushed. */
284 env_tlb(env
)->c
.dirty
= 0;
286 for (i
= 0; i
< NB_MMU_MODES
; i
++) {
287 tlb_mmu_init(&env_tlb(env
)->d
[i
], &env_tlb(env
)->f
[i
], now
);
291 void tlb_destroy(CPUState
*cpu
)
293 CPUArchState
*env
= cpu
->env_ptr
;
296 qemu_spin_destroy(&env_tlb(env
)->c
.lock
);
297 for (i
= 0; i
< NB_MMU_MODES
; i
++) {
298 CPUTLBDesc
*desc
= &env_tlb(env
)->d
[i
];
299 CPUTLBDescFast
*fast
= &env_tlb(env
)->f
[i
];
302 g_free(desc
->fulltlb
);
306 /* flush_all_helper: run fn across all cpus
308 * If the wait flag is set then the src cpu's helper will be queued as
309 * "safe" work and the loop exited creating a synchronisation point
310 * where all queued work will be finished before execution starts
313 static void flush_all_helper(CPUState
*src
, run_on_cpu_func fn
,
320 async_run_on_cpu(cpu
, fn
, d
);
325 void tlb_flush_counts(size_t *pfull
, size_t *ppart
, size_t *pelide
)
328 size_t full
= 0, part
= 0, elide
= 0;
331 CPUArchState
*env
= cpu
->env_ptr
;
333 full
+= qatomic_read(&env_tlb(env
)->c
.full_flush_count
);
334 part
+= qatomic_read(&env_tlb(env
)->c
.part_flush_count
);
335 elide
+= qatomic_read(&env_tlb(env
)->c
.elide_flush_count
);
342 static void tlb_flush_by_mmuidx_async_work(CPUState
*cpu
, run_on_cpu_data data
)
344 CPUArchState
*env
= cpu
->env_ptr
;
345 uint16_t asked
= data
.host_int
;
346 uint16_t all_dirty
, work
, to_clean
;
347 int64_t now
= get_clock_realtime();
349 assert_cpu_is_self(cpu
);
351 tlb_debug("mmu_idx:0x%04" PRIx16
"\n", asked
);
353 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
355 all_dirty
= env_tlb(env
)->c
.dirty
;
356 to_clean
= asked
& all_dirty
;
357 all_dirty
&= ~to_clean
;
358 env_tlb(env
)->c
.dirty
= all_dirty
;
360 for (work
= to_clean
; work
!= 0; work
&= work
- 1) {
361 int mmu_idx
= ctz32(work
);
362 tlb_flush_one_mmuidx_locked(env
, mmu_idx
, now
);
365 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
367 tcg_flush_jmp_cache(cpu
);
369 if (to_clean
== ALL_MMUIDX_BITS
) {
370 qatomic_set(&env_tlb(env
)->c
.full_flush_count
,
371 env_tlb(env
)->c
.full_flush_count
+ 1);
373 qatomic_set(&env_tlb(env
)->c
.part_flush_count
,
374 env_tlb(env
)->c
.part_flush_count
+ ctpop16(to_clean
));
375 if (to_clean
!= asked
) {
376 qatomic_set(&env_tlb(env
)->c
.elide_flush_count
,
377 env_tlb(env
)->c
.elide_flush_count
+
378 ctpop16(asked
& ~to_clean
));
383 void tlb_flush_by_mmuidx(CPUState
*cpu
, uint16_t idxmap
)
385 tlb_debug("mmu_idx: 0x%" PRIx16
"\n", idxmap
);
387 if (cpu
->created
&& !qemu_cpu_is_self(cpu
)) {
388 async_run_on_cpu(cpu
, tlb_flush_by_mmuidx_async_work
,
389 RUN_ON_CPU_HOST_INT(idxmap
));
391 tlb_flush_by_mmuidx_async_work(cpu
, RUN_ON_CPU_HOST_INT(idxmap
));
395 void tlb_flush(CPUState
*cpu
)
397 tlb_flush_by_mmuidx(cpu
, ALL_MMUIDX_BITS
);
400 void tlb_flush_by_mmuidx_all_cpus(CPUState
*src_cpu
, uint16_t idxmap
)
402 const run_on_cpu_func fn
= tlb_flush_by_mmuidx_async_work
;
404 tlb_debug("mmu_idx: 0x%"PRIx16
"\n", idxmap
);
406 flush_all_helper(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
407 fn(src_cpu
, RUN_ON_CPU_HOST_INT(idxmap
));
410 void tlb_flush_all_cpus(CPUState
*src_cpu
)
412 tlb_flush_by_mmuidx_all_cpus(src_cpu
, ALL_MMUIDX_BITS
);
415 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
, uint16_t idxmap
)
417 const run_on_cpu_func fn
= tlb_flush_by_mmuidx_async_work
;
419 tlb_debug("mmu_idx: 0x%"PRIx16
"\n", idxmap
);
421 flush_all_helper(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
422 async_safe_run_on_cpu(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
425 void tlb_flush_all_cpus_synced(CPUState
*src_cpu
)
427 tlb_flush_by_mmuidx_all_cpus_synced(src_cpu
, ALL_MMUIDX_BITS
);
430 static bool tlb_hit_page_mask_anyprot(CPUTLBEntry
*tlb_entry
,
431 vaddr page
, vaddr mask
)
434 mask
&= TARGET_PAGE_MASK
| TLB_INVALID_MASK
;
436 return (page
== (tlb_entry
->addr_read
& mask
) ||
437 page
== (tlb_addr_write(tlb_entry
) & mask
) ||
438 page
== (tlb_entry
->addr_code
& mask
));
441 static inline bool tlb_hit_page_anyprot(CPUTLBEntry
*tlb_entry
, vaddr page
)
443 return tlb_hit_page_mask_anyprot(tlb_entry
, page
, -1);
447 * tlb_entry_is_empty - return true if the entry is not in use
448 * @te: pointer to CPUTLBEntry
450 static inline bool tlb_entry_is_empty(const CPUTLBEntry
*te
)
452 return te
->addr_read
== -1 && te
->addr_write
== -1 && te
->addr_code
== -1;
455 /* Called with tlb_c.lock held */
456 static bool tlb_flush_entry_mask_locked(CPUTLBEntry
*tlb_entry
,
460 if (tlb_hit_page_mask_anyprot(tlb_entry
, page
, mask
)) {
461 memset(tlb_entry
, -1, sizeof(*tlb_entry
));
467 static inline bool tlb_flush_entry_locked(CPUTLBEntry
*tlb_entry
, vaddr page
)
469 return tlb_flush_entry_mask_locked(tlb_entry
, page
, -1);
472 /* Called with tlb_c.lock held */
473 static void tlb_flush_vtlb_page_mask_locked(CPUArchState
*env
, int mmu_idx
,
477 CPUTLBDesc
*d
= &env_tlb(env
)->d
[mmu_idx
];
480 assert_cpu_is_self(env_cpu(env
));
481 for (k
= 0; k
< CPU_VTLB_SIZE
; k
++) {
482 if (tlb_flush_entry_mask_locked(&d
->vtable
[k
], page
, mask
)) {
483 tlb_n_used_entries_dec(env
, mmu_idx
);
488 static inline void tlb_flush_vtlb_page_locked(CPUArchState
*env
, int mmu_idx
,
491 tlb_flush_vtlb_page_mask_locked(env
, mmu_idx
, page
, -1);
494 static void tlb_flush_page_locked(CPUArchState
*env
, int midx
, vaddr page
)
496 vaddr lp_addr
= env_tlb(env
)->d
[midx
].large_page_addr
;
497 vaddr lp_mask
= env_tlb(env
)->d
[midx
].large_page_mask
;
499 /* Check if we need to flush due to large pages. */
500 if ((page
& lp_mask
) == lp_addr
) {
501 tlb_debug("forcing full flush midx %d (%016"
502 VADDR_PRIx
"/%016" VADDR_PRIx
")\n",
503 midx
, lp_addr
, lp_mask
);
504 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
506 if (tlb_flush_entry_locked(tlb_entry(env
, midx
, page
), page
)) {
507 tlb_n_used_entries_dec(env
, midx
);
509 tlb_flush_vtlb_page_locked(env
, midx
, page
);
514 * tlb_flush_page_by_mmuidx_async_0:
515 * @cpu: cpu on which to flush
516 * @addr: page of virtual address to flush
517 * @idxmap: set of mmu_idx to flush
519 * Helper for tlb_flush_page_by_mmuidx and friends, flush one page
520 * at @addr from the tlbs indicated by @idxmap from @cpu.
522 static void tlb_flush_page_by_mmuidx_async_0(CPUState
*cpu
,
526 CPUArchState
*env
= cpu
->env_ptr
;
529 assert_cpu_is_self(cpu
);
531 tlb_debug("page addr: %016" VADDR_PRIx
" mmu_map:0x%x\n", addr
, idxmap
);
533 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
534 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
535 if ((idxmap
>> mmu_idx
) & 1) {
536 tlb_flush_page_locked(env
, mmu_idx
, addr
);
539 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
542 * Discard jump cache entries for any tb which might potentially
543 * overlap the flushed page, which includes the previous.
545 tb_jmp_cache_clear_page(cpu
, addr
- TARGET_PAGE_SIZE
);
546 tb_jmp_cache_clear_page(cpu
, addr
);
550 * tlb_flush_page_by_mmuidx_async_1:
551 * @cpu: cpu on which to flush
552 * @data: encoded addr + idxmap
554 * Helper for tlb_flush_page_by_mmuidx and friends, called through
555 * async_run_on_cpu. The idxmap parameter is encoded in the page
556 * offset of the target_ptr field. This limits the set of mmu_idx
557 * that can be passed via this method.
559 static void tlb_flush_page_by_mmuidx_async_1(CPUState
*cpu
,
560 run_on_cpu_data data
)
562 vaddr addr_and_idxmap
= data
.target_ptr
;
563 vaddr addr
= addr_and_idxmap
& TARGET_PAGE_MASK
;
564 uint16_t idxmap
= addr_and_idxmap
& ~TARGET_PAGE_MASK
;
566 tlb_flush_page_by_mmuidx_async_0(cpu
, addr
, idxmap
);
572 } TLBFlushPageByMMUIdxData
;
575 * tlb_flush_page_by_mmuidx_async_2:
576 * @cpu: cpu on which to flush
577 * @data: allocated addr + idxmap
579 * Helper for tlb_flush_page_by_mmuidx and friends, called through
580 * async_run_on_cpu. The addr+idxmap parameters are stored in a
581 * TLBFlushPageByMMUIdxData structure that has been allocated
582 * specifically for this helper. Free the structure when done.
584 static void tlb_flush_page_by_mmuidx_async_2(CPUState
*cpu
,
585 run_on_cpu_data data
)
587 TLBFlushPageByMMUIdxData
*d
= data
.host_ptr
;
589 tlb_flush_page_by_mmuidx_async_0(cpu
, d
->addr
, d
->idxmap
);
593 void tlb_flush_page_by_mmuidx(CPUState
*cpu
, vaddr addr
, uint16_t idxmap
)
595 tlb_debug("addr: %016" VADDR_PRIx
" mmu_idx:%" PRIx16
"\n", addr
, idxmap
);
597 /* This should already be page aligned */
598 addr
&= TARGET_PAGE_MASK
;
600 if (qemu_cpu_is_self(cpu
)) {
601 tlb_flush_page_by_mmuidx_async_0(cpu
, addr
, idxmap
);
602 } else if (idxmap
< TARGET_PAGE_SIZE
) {
604 * Most targets have only a few mmu_idx. In the case where
605 * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid
606 * allocating memory for this operation.
608 async_run_on_cpu(cpu
, tlb_flush_page_by_mmuidx_async_1
,
609 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
611 TLBFlushPageByMMUIdxData
*d
= g_new(TLBFlushPageByMMUIdxData
, 1);
613 /* Otherwise allocate a structure, freed by the worker. */
616 async_run_on_cpu(cpu
, tlb_flush_page_by_mmuidx_async_2
,
617 RUN_ON_CPU_HOST_PTR(d
));
621 void tlb_flush_page(CPUState
*cpu
, vaddr addr
)
623 tlb_flush_page_by_mmuidx(cpu
, addr
, ALL_MMUIDX_BITS
);
626 void tlb_flush_page_by_mmuidx_all_cpus(CPUState
*src_cpu
, vaddr addr
,
629 tlb_debug("addr: %016" VADDR_PRIx
" mmu_idx:%"PRIx16
"\n", addr
, idxmap
);
631 /* This should already be page aligned */
632 addr
&= TARGET_PAGE_MASK
;
635 * Allocate memory to hold addr+idxmap only when needed.
636 * See tlb_flush_page_by_mmuidx for details.
638 if (idxmap
< TARGET_PAGE_SIZE
) {
639 flush_all_helper(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
640 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
644 /* Allocate a separate data block for each destination cpu. */
645 CPU_FOREACH(dst_cpu
) {
646 if (dst_cpu
!= src_cpu
) {
647 TLBFlushPageByMMUIdxData
*d
648 = g_new(TLBFlushPageByMMUIdxData
, 1);
652 async_run_on_cpu(dst_cpu
, tlb_flush_page_by_mmuidx_async_2
,
653 RUN_ON_CPU_HOST_PTR(d
));
658 tlb_flush_page_by_mmuidx_async_0(src_cpu
, addr
, idxmap
);
661 void tlb_flush_page_all_cpus(CPUState
*src
, vaddr addr
)
663 tlb_flush_page_by_mmuidx_all_cpus(src
, addr
, ALL_MMUIDX_BITS
);
666 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
670 tlb_debug("addr: %016" VADDR_PRIx
" mmu_idx:%"PRIx16
"\n", addr
, idxmap
);
672 /* This should already be page aligned */
673 addr
&= TARGET_PAGE_MASK
;
676 * Allocate memory to hold addr+idxmap only when needed.
677 * See tlb_flush_page_by_mmuidx for details.
679 if (idxmap
< TARGET_PAGE_SIZE
) {
680 flush_all_helper(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
681 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
682 async_safe_run_on_cpu(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
683 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
686 TLBFlushPageByMMUIdxData
*d
;
688 /* Allocate a separate data block for each destination cpu. */
689 CPU_FOREACH(dst_cpu
) {
690 if (dst_cpu
!= src_cpu
) {
691 d
= g_new(TLBFlushPageByMMUIdxData
, 1);
694 async_run_on_cpu(dst_cpu
, tlb_flush_page_by_mmuidx_async_2
,
695 RUN_ON_CPU_HOST_PTR(d
));
699 d
= g_new(TLBFlushPageByMMUIdxData
, 1);
702 async_safe_run_on_cpu(src_cpu
, tlb_flush_page_by_mmuidx_async_2
,
703 RUN_ON_CPU_HOST_PTR(d
));
707 void tlb_flush_page_all_cpus_synced(CPUState
*src
, vaddr addr
)
709 tlb_flush_page_by_mmuidx_all_cpus_synced(src
, addr
, ALL_MMUIDX_BITS
);
712 static void tlb_flush_range_locked(CPUArchState
*env
, int midx
,
713 vaddr addr
, vaddr len
,
716 CPUTLBDesc
*d
= &env_tlb(env
)->d
[midx
];
717 CPUTLBDescFast
*f
= &env_tlb(env
)->f
[midx
];
718 vaddr mask
= MAKE_64BIT_MASK(0, bits
);
721 * If @bits is smaller than the tlb size, there may be multiple entries
722 * within the TLB; otherwise all addresses that match under @mask hit
723 * the same TLB entry.
724 * TODO: Perhaps allow bits to be a few bits less than the size.
725 * For now, just flush the entire TLB.
727 * If @len is larger than the tlb size, then it will take longer to
728 * test all of the entries in the TLB than it will to flush it all.
730 if (mask
< f
->mask
|| len
> f
->mask
) {
731 tlb_debug("forcing full flush midx %d ("
732 "%016" VADDR_PRIx
"/%016" VADDR_PRIx
"+%016" VADDR_PRIx
")\n",
733 midx
, addr
, mask
, len
);
734 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
739 * Check if we need to flush due to large pages.
740 * Because large_page_mask contains all 1's from the msb,
741 * we only need to test the end of the range.
743 if (((addr
+ len
- 1) & d
->large_page_mask
) == d
->large_page_addr
) {
744 tlb_debug("forcing full flush midx %d ("
745 "%016" VADDR_PRIx
"/%016" VADDR_PRIx
")\n",
746 midx
, d
->large_page_addr
, d
->large_page_mask
);
747 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
751 for (vaddr i
= 0; i
< len
; i
+= TARGET_PAGE_SIZE
) {
752 vaddr page
= addr
+ i
;
753 CPUTLBEntry
*entry
= tlb_entry(env
, midx
, page
);
755 if (tlb_flush_entry_mask_locked(entry
, page
, mask
)) {
756 tlb_n_used_entries_dec(env
, midx
);
758 tlb_flush_vtlb_page_mask_locked(env
, midx
, page
, mask
);
769 static void tlb_flush_range_by_mmuidx_async_0(CPUState
*cpu
,
772 CPUArchState
*env
= cpu
->env_ptr
;
775 assert_cpu_is_self(cpu
);
777 tlb_debug("range: %016" VADDR_PRIx
"/%u+%016" VADDR_PRIx
" mmu_map:0x%x\n",
778 d
.addr
, d
.bits
, d
.len
, d
.idxmap
);
780 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
781 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
782 if ((d
.idxmap
>> mmu_idx
) & 1) {
783 tlb_flush_range_locked(env
, mmu_idx
, d
.addr
, d
.len
, d
.bits
);
786 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
789 * If the length is larger than the jump cache size, then it will take
790 * longer to clear each entry individually than it will to clear it all.
792 if (d
.len
>= (TARGET_PAGE_SIZE
* TB_JMP_CACHE_SIZE
)) {
793 tcg_flush_jmp_cache(cpu
);
798 * Discard jump cache entries for any tb which might potentially
799 * overlap the flushed pages, which includes the previous.
801 d
.addr
-= TARGET_PAGE_SIZE
;
802 for (vaddr i
= 0, n
= d
.len
/ TARGET_PAGE_SIZE
+ 1; i
< n
; i
++) {
803 tb_jmp_cache_clear_page(cpu
, d
.addr
);
804 d
.addr
+= TARGET_PAGE_SIZE
;
808 static void tlb_flush_range_by_mmuidx_async_1(CPUState
*cpu
,
809 run_on_cpu_data data
)
811 TLBFlushRangeData
*d
= data
.host_ptr
;
812 tlb_flush_range_by_mmuidx_async_0(cpu
, *d
);
816 void tlb_flush_range_by_mmuidx(CPUState
*cpu
, vaddr addr
,
817 vaddr len
, uint16_t idxmap
,
823 * If all bits are significant, and len is small,
824 * this devolves to tlb_flush_page.
826 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
827 tlb_flush_page_by_mmuidx(cpu
, addr
, idxmap
);
830 /* If no page bits are significant, this devolves to tlb_flush. */
831 if (bits
< TARGET_PAGE_BITS
) {
832 tlb_flush_by_mmuidx(cpu
, idxmap
);
836 /* This should already be page aligned */
837 d
.addr
= addr
& TARGET_PAGE_MASK
;
842 if (qemu_cpu_is_self(cpu
)) {
843 tlb_flush_range_by_mmuidx_async_0(cpu
, d
);
845 /* Otherwise allocate a structure, freed by the worker. */
846 TLBFlushRangeData
*p
= g_memdup(&d
, sizeof(d
));
847 async_run_on_cpu(cpu
, tlb_flush_range_by_mmuidx_async_1
,
848 RUN_ON_CPU_HOST_PTR(p
));
852 void tlb_flush_page_bits_by_mmuidx(CPUState
*cpu
, vaddr addr
,
853 uint16_t idxmap
, unsigned bits
)
855 tlb_flush_range_by_mmuidx(cpu
, addr
, TARGET_PAGE_SIZE
, idxmap
, bits
);
858 void tlb_flush_range_by_mmuidx_all_cpus(CPUState
*src_cpu
,
859 vaddr addr
, vaddr len
,
860 uint16_t idxmap
, unsigned bits
)
866 * If all bits are significant, and len is small,
867 * this devolves to tlb_flush_page.
869 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
870 tlb_flush_page_by_mmuidx_all_cpus(src_cpu
, addr
, idxmap
);
873 /* If no page bits are significant, this devolves to tlb_flush. */
874 if (bits
< TARGET_PAGE_BITS
) {
875 tlb_flush_by_mmuidx_all_cpus(src_cpu
, idxmap
);
879 /* This should already be page aligned */
880 d
.addr
= addr
& TARGET_PAGE_MASK
;
885 /* Allocate a separate data block for each destination cpu. */
886 CPU_FOREACH(dst_cpu
) {
887 if (dst_cpu
!= src_cpu
) {
888 TLBFlushRangeData
*p
= g_memdup(&d
, sizeof(d
));
889 async_run_on_cpu(dst_cpu
,
890 tlb_flush_range_by_mmuidx_async_1
,
891 RUN_ON_CPU_HOST_PTR(p
));
895 tlb_flush_range_by_mmuidx_async_0(src_cpu
, d
);
898 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState
*src_cpu
,
899 vaddr addr
, uint16_t idxmap
,
902 tlb_flush_range_by_mmuidx_all_cpus(src_cpu
, addr
, TARGET_PAGE_SIZE
,
906 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
912 TLBFlushRangeData d
, *p
;
916 * If all bits are significant, and len is small,
917 * this devolves to tlb_flush_page.
919 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
920 tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu
, addr
, idxmap
);
923 /* If no page bits are significant, this devolves to tlb_flush. */
924 if (bits
< TARGET_PAGE_BITS
) {
925 tlb_flush_by_mmuidx_all_cpus_synced(src_cpu
, idxmap
);
929 /* This should already be page aligned */
930 d
.addr
= addr
& TARGET_PAGE_MASK
;
935 /* Allocate a separate data block for each destination cpu. */
936 CPU_FOREACH(dst_cpu
) {
937 if (dst_cpu
!= src_cpu
) {
938 p
= g_memdup(&d
, sizeof(d
));
939 async_run_on_cpu(dst_cpu
, tlb_flush_range_by_mmuidx_async_1
,
940 RUN_ON_CPU_HOST_PTR(p
));
944 p
= g_memdup(&d
, sizeof(d
));
945 async_safe_run_on_cpu(src_cpu
, tlb_flush_range_by_mmuidx_async_1
,
946 RUN_ON_CPU_HOST_PTR(p
));
949 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
954 tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu
, addr
, TARGET_PAGE_SIZE
,
958 /* update the TLBs so that writes to code in the virtual page 'addr'
960 void tlb_protect_code(ram_addr_t ram_addr
)
962 cpu_physical_memory_test_and_clear_dirty(ram_addr
& TARGET_PAGE_MASK
,
967 /* update the TLB so that writes in physical page 'phys_addr' are no longer
968 tested for self modifying code */
969 void tlb_unprotect_code(ram_addr_t ram_addr
)
971 cpu_physical_memory_set_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
);
976 * Dirty write flag handling
978 * When the TCG code writes to a location it looks up the address in
979 * the TLB and uses that data to compute the final address. If any of
980 * the lower bits of the address are set then the slow path is forced.
981 * There are a number of reasons to do this but for normal RAM the
982 * most usual is detecting writes to code regions which may invalidate
985 * Other vCPUs might be reading their TLBs during guest execution, so we update
986 * te->addr_write with qatomic_set. We don't need to worry about this for
987 * oversized guests as MTTCG is disabled for them.
989 * Called with tlb_c.lock held.
991 static void tlb_reset_dirty_range_locked(CPUTLBEntry
*tlb_entry
,
992 uintptr_t start
, uintptr_t length
)
994 uintptr_t addr
= tlb_entry
->addr_write
;
996 if ((addr
& (TLB_INVALID_MASK
| TLB_MMIO
|
997 TLB_DISCARD_WRITE
| TLB_NOTDIRTY
)) == 0) {
998 addr
&= TARGET_PAGE_MASK
;
999 addr
+= tlb_entry
->addend
;
1000 if ((addr
- start
) < length
) {
1001 #if TARGET_LONG_BITS == 32
1002 uint32_t *ptr_write
= (uint32_t *)&tlb_entry
->addr_write
;
1003 ptr_write
+= HOST_BIG_ENDIAN
;
1004 qatomic_set(ptr_write
, *ptr_write
| TLB_NOTDIRTY
);
1005 #elif TCG_OVERSIZED_GUEST
1006 tlb_entry
->addr_write
|= TLB_NOTDIRTY
;
1008 qatomic_set(&tlb_entry
->addr_write
,
1009 tlb_entry
->addr_write
| TLB_NOTDIRTY
);
1016 * Called with tlb_c.lock held.
1017 * Called only from the vCPU context, i.e. the TLB's owner thread.
1019 static inline void copy_tlb_helper_locked(CPUTLBEntry
*d
, const CPUTLBEntry
*s
)
1024 /* This is a cross vCPU call (i.e. another vCPU resetting the flags of
1026 * We must take tlb_c.lock to avoid racing with another vCPU update. The only
1027 * thing actually updated is the target TLB entry ->addr_write flags.
1029 void tlb_reset_dirty(CPUState
*cpu
, ram_addr_t start1
, ram_addr_t length
)
1036 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1037 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1039 unsigned int n
= tlb_n_entries(&env_tlb(env
)->f
[mmu_idx
]);
1041 for (i
= 0; i
< n
; i
++) {
1042 tlb_reset_dirty_range_locked(&env_tlb(env
)->f
[mmu_idx
].table
[i
],
1046 for (i
= 0; i
< CPU_VTLB_SIZE
; i
++) {
1047 tlb_reset_dirty_range_locked(&env_tlb(env
)->d
[mmu_idx
].vtable
[i
],
1051 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1054 /* Called with tlb_c.lock held */
1055 static inline void tlb_set_dirty1_locked(CPUTLBEntry
*tlb_entry
,
1058 if (tlb_entry
->addr_write
== (addr
| TLB_NOTDIRTY
)) {
1059 tlb_entry
->addr_write
= addr
;
1063 /* update the TLB corresponding to virtual page vaddr
1064 so that it is no longer dirty */
1065 void tlb_set_dirty(CPUState
*cpu
, vaddr addr
)
1067 CPUArchState
*env
= cpu
->env_ptr
;
1070 assert_cpu_is_self(cpu
);
1072 addr
&= TARGET_PAGE_MASK
;
1073 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1074 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1075 tlb_set_dirty1_locked(tlb_entry(env
, mmu_idx
, addr
), addr
);
1078 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1080 for (k
= 0; k
< CPU_VTLB_SIZE
; k
++) {
1081 tlb_set_dirty1_locked(&env_tlb(env
)->d
[mmu_idx
].vtable
[k
], addr
);
1084 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1087 /* Our TLB does not support large pages, so remember the area covered by
1088 large pages and trigger a full TLB flush if these are invalidated. */
1089 static void tlb_add_large_page(CPUArchState
*env
, int mmu_idx
,
1090 vaddr addr
, uint64_t size
)
1092 vaddr lp_addr
= env_tlb(env
)->d
[mmu_idx
].large_page_addr
;
1093 vaddr lp_mask
= ~(size
- 1);
1095 if (lp_addr
== (vaddr
)-1) {
1096 /* No previous large page. */
1099 /* Extend the existing region to include the new page.
1100 This is a compromise between unnecessary flushes and
1101 the cost of maintaining a full variable size TLB. */
1102 lp_mask
&= env_tlb(env
)->d
[mmu_idx
].large_page_mask
;
1103 while (((lp_addr
^ addr
) & lp_mask
) != 0) {
1107 env_tlb(env
)->d
[mmu_idx
].large_page_addr
= lp_addr
& lp_mask
;
1108 env_tlb(env
)->d
[mmu_idx
].large_page_mask
= lp_mask
;
1111 static inline void tlb_set_compare(CPUTLBEntryFull
*full
, CPUTLBEntry
*ent
,
1112 vaddr address
, int flags
,
1113 MMUAccessType access_type
, bool enable
)
1116 address
|= flags
& TLB_FLAGS_MASK
;
1117 flags
&= TLB_SLOW_FLAGS_MASK
;
1119 address
|= TLB_FORCE_SLOW
;
1125 ent
->addr_idx
[access_type
] = address
;
1126 full
->slow_flags
[access_type
] = flags
;
1130 * Add a new TLB entry. At most one entry for a given virtual address
1131 * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
1132 * supplied size is only used by tlb_flush_page.
1134 * Called from TCG-generated code, which is under an RCU read-side
1137 void tlb_set_page_full(CPUState
*cpu
, int mmu_idx
,
1138 vaddr addr
, CPUTLBEntryFull
*full
)
1140 CPUArchState
*env
= cpu
->env_ptr
;
1141 CPUTLB
*tlb
= env_tlb(env
);
1142 CPUTLBDesc
*desc
= &tlb
->d
[mmu_idx
];
1143 MemoryRegionSection
*section
;
1144 unsigned int index
, read_flags
, write_flags
;
1146 CPUTLBEntry
*te
, tn
;
1147 hwaddr iotlb
, xlat
, sz
, paddr_page
;
1149 int asidx
, wp_flags
, prot
;
1150 bool is_ram
, is_romd
;
1152 assert_cpu_is_self(cpu
);
1154 if (full
->lg_page_size
<= TARGET_PAGE_BITS
) {
1155 sz
= TARGET_PAGE_SIZE
;
1157 sz
= (hwaddr
)1 << full
->lg_page_size
;
1158 tlb_add_large_page(env
, mmu_idx
, addr
, sz
);
1160 addr_page
= addr
& TARGET_PAGE_MASK
;
1161 paddr_page
= full
->phys_addr
& TARGET_PAGE_MASK
;
1164 asidx
= cpu_asidx_from_attrs(cpu
, full
->attrs
);
1165 section
= address_space_translate_for_iotlb(cpu
, asidx
, paddr_page
,
1166 &xlat
, &sz
, full
->attrs
, &prot
);
1167 assert(sz
>= TARGET_PAGE_SIZE
);
1169 tlb_debug("vaddr=%016" VADDR_PRIx
" paddr=0x" HWADDR_FMT_plx
1170 " prot=%x idx=%d\n",
1171 addr
, full
->phys_addr
, prot
, mmu_idx
);
1174 if (full
->lg_page_size
< TARGET_PAGE_BITS
) {
1175 /* Repeat the MMU check and TLB fill on every access. */
1176 read_flags
|= TLB_INVALID_MASK
;
1178 if (full
->attrs
.byte_swap
) {
1179 read_flags
|= TLB_BSWAP
;
1182 is_ram
= memory_region_is_ram(section
->mr
);
1183 is_romd
= memory_region_is_romd(section
->mr
);
1185 if (is_ram
|| is_romd
) {
1186 /* RAM and ROMD both have associated host memory. */
1187 addend
= (uintptr_t)memory_region_get_ram_ptr(section
->mr
) + xlat
;
1189 /* I/O does not; force the host address to NULL. */
1193 write_flags
= read_flags
;
1195 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1196 assert(!(iotlb
& ~TARGET_PAGE_MASK
));
1198 * Computing is_clean is expensive; avoid all that unless
1199 * the page is actually writable.
1201 if (prot
& PAGE_WRITE
) {
1202 if (section
->readonly
) {
1203 write_flags
|= TLB_DISCARD_WRITE
;
1204 } else if (cpu_physical_memory_is_clean(iotlb
)) {
1205 write_flags
|= TLB_NOTDIRTY
;
1210 iotlb
= memory_region_section_get_iotlb(cpu
, section
) + xlat
;
1212 * Writes to romd devices must go through MMIO to enable write.
1213 * Reads to romd devices go through the ram_ptr found above,
1214 * but of course reads to I/O must go through MMIO.
1216 write_flags
|= TLB_MMIO
;
1218 read_flags
= write_flags
;
1222 wp_flags
= cpu_watchpoint_address_matches(cpu
, addr_page
,
1225 index
= tlb_index(env
, mmu_idx
, addr_page
);
1226 te
= tlb_entry(env
, mmu_idx
, addr_page
);
1229 * Hold the TLB lock for the rest of the function. We could acquire/release
1230 * the lock several times in the function, but it is faster to amortize the
1231 * acquisition cost by acquiring it just once. Note that this leads to
1232 * a longer critical section, but this is not a concern since the TLB lock
1233 * is unlikely to be contended.
1235 qemu_spin_lock(&tlb
->c
.lock
);
1237 /* Note that the tlb is no longer clean. */
1238 tlb
->c
.dirty
|= 1 << mmu_idx
;
1240 /* Make sure there's no cached translation for the new page. */
1241 tlb_flush_vtlb_page_locked(env
, mmu_idx
, addr_page
);
1244 * Only evict the old entry to the victim tlb if it's for a
1245 * different page; otherwise just overwrite the stale data.
1247 if (!tlb_hit_page_anyprot(te
, addr_page
) && !tlb_entry_is_empty(te
)) {
1248 unsigned vidx
= desc
->vindex
++ % CPU_VTLB_SIZE
;
1249 CPUTLBEntry
*tv
= &desc
->vtable
[vidx
];
1251 /* Evict the old entry into the victim tlb. */
1252 copy_tlb_helper_locked(tv
, te
);
1253 desc
->vfulltlb
[vidx
] = desc
->fulltlb
[index
];
1254 tlb_n_used_entries_dec(env
, mmu_idx
);
1257 /* refill the tlb */
1259 * When memory region is ram, iotlb contains a TARGET_PAGE_BITS
1260 * aligned ram_addr_t of the page base of the target RAM.
1261 * Otherwise, iotlb contains
1262 * - a physical section number in the lower TARGET_PAGE_BITS
1263 * - the offset within section->mr of the page base (I/O, ROMD) with the
1264 * TARGET_PAGE_BITS masked off.
1265 * We subtract addr_page (which is page aligned and thus won't
1266 * disturb the low bits) to give an offset which can be added to the
1267 * (non-page-aligned) vaddr of the eventual memory access to get
1268 * the MemoryRegion offset for the access. Note that the vaddr we
1269 * subtract here is that of the page base, and not the same as the
1270 * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
1272 desc
->fulltlb
[index
] = *full
;
1273 full
= &desc
->fulltlb
[index
];
1274 full
->xlat_section
= iotlb
- addr_page
;
1275 full
->phys_addr
= paddr_page
;
1277 /* Now calculate the new entry */
1278 tn
.addend
= addend
- addr_page
;
1280 tlb_set_compare(full
, &tn
, addr_page
, read_flags
,
1281 MMU_INST_FETCH
, prot
& PAGE_EXEC
);
1283 if (wp_flags
& BP_MEM_READ
) {
1284 read_flags
|= TLB_WATCHPOINT
;
1286 tlb_set_compare(full
, &tn
, addr_page
, read_flags
,
1287 MMU_DATA_LOAD
, prot
& PAGE_READ
);
1289 if (prot
& PAGE_WRITE_INV
) {
1290 write_flags
|= TLB_INVALID_MASK
;
1292 if (wp_flags
& BP_MEM_WRITE
) {
1293 write_flags
|= TLB_WATCHPOINT
;
1295 tlb_set_compare(full
, &tn
, addr_page
, write_flags
,
1296 MMU_DATA_STORE
, prot
& PAGE_WRITE
);
1298 copy_tlb_helper_locked(te
, &tn
);
1299 tlb_n_used_entries_inc(env
, mmu_idx
);
1300 qemu_spin_unlock(&tlb
->c
.lock
);
1303 void tlb_set_page_with_attrs(CPUState
*cpu
, vaddr addr
,
1304 hwaddr paddr
, MemTxAttrs attrs
, int prot
,
1305 int mmu_idx
, uint64_t size
)
1307 CPUTLBEntryFull full
= {
1311 .lg_page_size
= ctz64(size
)
1314 assert(is_power_of_2(size
));
1315 tlb_set_page_full(cpu
, mmu_idx
, addr
, &full
);
1318 void tlb_set_page(CPUState
*cpu
, vaddr addr
,
1319 hwaddr paddr
, int prot
,
1320 int mmu_idx
, uint64_t size
)
1322 tlb_set_page_with_attrs(cpu
, addr
, paddr
, MEMTXATTRS_UNSPECIFIED
,
1323 prot
, mmu_idx
, size
);
1327 * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
1328 * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
1329 * be discarded and looked up again (e.g. via tlb_entry()).
1331 static void tlb_fill(CPUState
*cpu
, vaddr addr
, int size
,
1332 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
1337 * This is not a probe, so only valid return is success; failure
1338 * should result in exception + longjmp to the cpu loop.
1340 ok
= cpu
->cc
->tcg_ops
->tlb_fill(cpu
, addr
, size
,
1341 access_type
, mmu_idx
, false, retaddr
);
1345 static inline void cpu_unaligned_access(CPUState
*cpu
, vaddr addr
,
1346 MMUAccessType access_type
,
1347 int mmu_idx
, uintptr_t retaddr
)
1349 cpu
->cc
->tcg_ops
->do_unaligned_access(cpu
, addr
, access_type
,
1353 static inline void cpu_transaction_failed(CPUState
*cpu
, hwaddr physaddr
,
1354 vaddr addr
, unsigned size
,
1355 MMUAccessType access_type
,
1356 int mmu_idx
, MemTxAttrs attrs
,
1357 MemTxResult response
,
1360 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
1362 if (!cpu
->ignore_memory_transaction_failures
&&
1363 cc
->tcg_ops
->do_transaction_failed
) {
1364 cc
->tcg_ops
->do_transaction_failed(cpu
, physaddr
, addr
, size
,
1365 access_type
, mmu_idx
, attrs
,
1370 static uint64_t io_readx(CPUArchState
*env
, CPUTLBEntryFull
*full
,
1371 int mmu_idx
, vaddr addr
, uintptr_t retaddr
,
1372 MMUAccessType access_type
, MemOp op
)
1374 CPUState
*cpu
= env_cpu(env
);
1376 MemoryRegionSection
*section
;
1381 section
= iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1383 mr_offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1384 cpu
->mem_io_pc
= retaddr
;
1385 if (!cpu
->can_do_io
) {
1386 cpu_io_recompile(cpu
, retaddr
);
1390 QEMU_IOTHREAD_LOCK_GUARD();
1391 r
= memory_region_dispatch_read(mr
, mr_offset
, &val
, op
, full
->attrs
);
1394 if (r
!= MEMTX_OK
) {
1395 hwaddr physaddr
= mr_offset
+
1396 section
->offset_within_address_space
-
1397 section
->offset_within_region
;
1399 cpu_transaction_failed(cpu
, physaddr
, addr
, memop_size(op
), access_type
,
1400 mmu_idx
, full
->attrs
, r
, retaddr
);
1405 static void io_writex(CPUArchState
*env
, CPUTLBEntryFull
*full
,
1406 int mmu_idx
, uint64_t val
, vaddr addr
,
1407 uintptr_t retaddr
, MemOp op
)
1409 CPUState
*cpu
= env_cpu(env
);
1411 MemoryRegionSection
*section
;
1415 section
= iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1417 mr_offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1418 if (!cpu
->can_do_io
) {
1419 cpu_io_recompile(cpu
, retaddr
);
1421 cpu
->mem_io_pc
= retaddr
;
1424 QEMU_IOTHREAD_LOCK_GUARD();
1425 r
= memory_region_dispatch_write(mr
, mr_offset
, val
, op
, full
->attrs
);
1428 if (r
!= MEMTX_OK
) {
1429 hwaddr physaddr
= mr_offset
+
1430 section
->offset_within_address_space
-
1431 section
->offset_within_region
;
1433 cpu_transaction_failed(cpu
, physaddr
, addr
, memop_size(op
),
1434 MMU_DATA_STORE
, mmu_idx
, full
->attrs
, r
,
1439 /* Return true if ADDR is present in the victim tlb, and has been copied
1440 back to the main tlb. */
1441 static bool victim_tlb_hit(CPUArchState
*env
, size_t mmu_idx
, size_t index
,
1442 MMUAccessType access_type
, vaddr page
)
1446 assert_cpu_is_self(env_cpu(env
));
1447 for (vidx
= 0; vidx
< CPU_VTLB_SIZE
; ++vidx
) {
1448 CPUTLBEntry
*vtlb
= &env_tlb(env
)->d
[mmu_idx
].vtable
[vidx
];
1449 uint64_t cmp
= tlb_read_idx(vtlb
, access_type
);
1452 /* Found entry in victim tlb, swap tlb and iotlb. */
1453 CPUTLBEntry tmptlb
, *tlb
= &env_tlb(env
)->f
[mmu_idx
].table
[index
];
1455 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1456 copy_tlb_helper_locked(&tmptlb
, tlb
);
1457 copy_tlb_helper_locked(tlb
, vtlb
);
1458 copy_tlb_helper_locked(vtlb
, &tmptlb
);
1459 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1461 CPUTLBEntryFull
*f1
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1462 CPUTLBEntryFull
*f2
= &env_tlb(env
)->d
[mmu_idx
].vfulltlb
[vidx
];
1463 CPUTLBEntryFull tmpf
;
1464 tmpf
= *f1
; *f1
= *f2
; *f2
= tmpf
;
1471 static void notdirty_write(CPUState
*cpu
, vaddr mem_vaddr
, unsigned size
,
1472 CPUTLBEntryFull
*full
, uintptr_t retaddr
)
1474 ram_addr_t ram_addr
= mem_vaddr
+ full
->xlat_section
;
1476 trace_memory_notdirty_write_access(mem_vaddr
, ram_addr
, size
);
1478 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
1479 tb_invalidate_phys_range_fast(ram_addr
, size
, retaddr
);
1483 * Set both VGA and migration bits for simplicity and to remove
1484 * the notdirty callback faster.
1486 cpu_physical_memory_set_dirty_range(ram_addr
, size
, DIRTY_CLIENTS_NOCODE
);
1488 /* We remove the notdirty callback only if the code has been flushed. */
1489 if (!cpu_physical_memory_is_clean(ram_addr
)) {
1490 trace_memory_notdirty_set_dirty(mem_vaddr
);
1491 tlb_set_dirty(cpu
, mem_vaddr
);
1495 static int probe_access_internal(CPUArchState
*env
, vaddr addr
,
1496 int fault_size
, MMUAccessType access_type
,
1497 int mmu_idx
, bool nonfault
,
1498 void **phost
, CPUTLBEntryFull
**pfull
,
1499 uintptr_t retaddr
, bool check_mem_cbs
)
1501 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1502 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
1503 uint64_t tlb_addr
= tlb_read_idx(entry
, access_type
);
1504 vaddr page_addr
= addr
& TARGET_PAGE_MASK
;
1505 int flags
= TLB_FLAGS_MASK
& ~TLB_FORCE_SLOW
;
1506 bool force_mmio
= check_mem_cbs
&& cpu_plugin_mem_cbs_enabled(env_cpu(env
));
1507 CPUTLBEntryFull
*full
;
1509 if (!tlb_hit_page(tlb_addr
, page_addr
)) {
1510 if (!victim_tlb_hit(env
, mmu_idx
, index
, access_type
, page_addr
)) {
1511 CPUState
*cs
= env_cpu(env
);
1513 if (!cs
->cc
->tcg_ops
->tlb_fill(cs
, addr
, fault_size
, access_type
,
1514 mmu_idx
, nonfault
, retaddr
)) {
1515 /* Non-faulting page table read failed. */
1518 return TLB_INVALID_MASK
;
1521 /* TLB resize via tlb_fill may have moved the entry. */
1522 index
= tlb_index(env
, mmu_idx
, addr
);
1523 entry
= tlb_entry(env
, mmu_idx
, addr
);
1526 * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
1527 * to force the next access through tlb_fill. We've just
1528 * called tlb_fill, so we know that this entry *is* valid.
1530 flags
&= ~TLB_INVALID_MASK
;
1532 tlb_addr
= tlb_read_idx(entry
, access_type
);
1536 *pfull
= full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1537 flags
|= full
->slow_flags
[access_type
];
1539 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
1540 if (unlikely(flags
& ~(TLB_WATCHPOINT
| TLB_NOTDIRTY
))
1542 (access_type
!= MMU_INST_FETCH
&& force_mmio
)) {
1547 /* Everything else is RAM. */
1548 *phost
= (void *)((uintptr_t)addr
+ entry
->addend
);
1552 int probe_access_full(CPUArchState
*env
, vaddr addr
, int size
,
1553 MMUAccessType access_type
, int mmu_idx
,
1554 bool nonfault
, void **phost
, CPUTLBEntryFull
**pfull
,
1557 int flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1558 nonfault
, phost
, pfull
, retaddr
, true);
1560 /* Handle clean RAM pages. */
1561 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1562 notdirty_write(env_cpu(env
), addr
, 1, *pfull
, retaddr
);
1563 flags
&= ~TLB_NOTDIRTY
;
1569 int probe_access_full_mmu(CPUArchState
*env
, vaddr addr
, int size
,
1570 MMUAccessType access_type
, int mmu_idx
,
1571 void **phost
, CPUTLBEntryFull
**pfull
)
1573 void *discard_phost
;
1574 CPUTLBEntryFull
*discard_tlb
;
1576 /* privately handle users that don't need full results */
1577 phost
= phost
? phost
: &discard_phost
;
1578 pfull
= pfull
? pfull
: &discard_tlb
;
1580 int flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1581 true, phost
, pfull
, 0, false);
1583 /* Handle clean RAM pages. */
1584 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1585 notdirty_write(env_cpu(env
), addr
, 1, *pfull
, 0);
1586 flags
&= ~TLB_NOTDIRTY
;
1592 int probe_access_flags(CPUArchState
*env
, vaddr addr
, int size
,
1593 MMUAccessType access_type
, int mmu_idx
,
1594 bool nonfault
, void **phost
, uintptr_t retaddr
)
1596 CPUTLBEntryFull
*full
;
1599 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
1601 flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1602 nonfault
, phost
, &full
, retaddr
, true);
1604 /* Handle clean RAM pages. */
1605 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1606 notdirty_write(env_cpu(env
), addr
, 1, full
, retaddr
);
1607 flags
&= ~TLB_NOTDIRTY
;
1613 void *probe_access(CPUArchState
*env
, vaddr addr
, int size
,
1614 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
1616 CPUTLBEntryFull
*full
;
1620 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
1622 flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1623 false, &host
, &full
, retaddr
, true);
1625 /* Per the interface, size == 0 merely faults the access. */
1630 if (unlikely(flags
& (TLB_NOTDIRTY
| TLB_WATCHPOINT
))) {
1631 /* Handle watchpoints. */
1632 if (flags
& TLB_WATCHPOINT
) {
1633 int wp_access
= (access_type
== MMU_DATA_STORE
1634 ? BP_MEM_WRITE
: BP_MEM_READ
);
1635 cpu_check_watchpoint(env_cpu(env
), addr
, size
,
1636 full
->attrs
, wp_access
, retaddr
);
1639 /* Handle clean RAM pages. */
1640 if (flags
& TLB_NOTDIRTY
) {
1641 notdirty_write(env_cpu(env
), addr
, 1, full
, retaddr
);
1648 void *tlb_vaddr_to_host(CPUArchState
*env
, abi_ptr addr
,
1649 MMUAccessType access_type
, int mmu_idx
)
1651 CPUTLBEntryFull
*full
;
1655 flags
= probe_access_internal(env
, addr
, 0, access_type
,
1656 mmu_idx
, true, &host
, &full
, 0, false);
1658 /* No combination of flags are expected by the caller. */
1659 return flags
? NULL
: host
;
1663 * Return a ram_addr_t for the virtual address for execution.
1665 * Return -1 if we can't translate and execute from an entire page
1666 * of RAM. This will force us to execute by loading and translating
1667 * one insn at a time, without caching.
1669 * NOTE: This function will trigger an exception if the page is
1672 tb_page_addr_t
get_page_addr_code_hostp(CPUArchState
*env
, vaddr addr
,
1675 CPUTLBEntryFull
*full
;
1678 (void)probe_access_internal(env
, addr
, 1, MMU_INST_FETCH
,
1679 cpu_mmu_index(env
, true), false,
1680 &p
, &full
, 0, false);
1685 if (full
->lg_page_size
< TARGET_PAGE_BITS
) {
1692 return qemu_ram_addr_from_host_nofail(p
);
1695 /* Load/store with atomicity primitives. */
1696 #include "ldst_atomicity.c.inc"
1698 #ifdef CONFIG_PLUGIN
1700 * Perform a TLB lookup and populate the qemu_plugin_hwaddr structure.
1701 * This should be a hot path as we will have just looked this path up
1702 * in the softmmu lookup code (or helper). We don't handle re-fills or
1703 * checking the victim table. This is purely informational.
1705 * The one corner case is i/o write, which can cause changes to the
1706 * address space. Those changes, and the corresponding tlb flush,
1707 * should be delayed until the next TB, so even then this ought not fail.
1708 * But check, Just in Case.
1710 bool tlb_plugin_lookup(CPUState
*cpu
, vaddr addr
, int mmu_idx
,
1711 bool is_store
, struct qemu_plugin_hwaddr
*data
)
1713 CPUArchState
*env
= cpu
->env_ptr
;
1714 CPUTLBEntry
*tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1715 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1716 MMUAccessType access_type
= is_store
? MMU_DATA_STORE
: MMU_DATA_LOAD
;
1717 uint64_t tlb_addr
= tlb_read_idx(tlbe
, access_type
);
1719 if (unlikely(!tlb_hit(tlb_addr
, addr
))) {
1723 /* We must have an iotlb entry for MMIO */
1724 if (tlb_addr
& TLB_MMIO
) {
1725 CPUTLBEntryFull
*full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1726 hwaddr xlat
= full
->xlat_section
;
1729 data
->v
.io
.offset
= (xlat
& TARGET_PAGE_MASK
) + addr
;
1730 data
->v
.io
.section
=
1731 iotlb_to_section(cpu
, xlat
& ~TARGET_PAGE_MASK
, full
->attrs
);
1733 data
->is_io
= false;
1734 data
->v
.ram
.hostaddr
= (void *)((uintptr_t)addr
+ tlbe
->addend
);
1741 * Probe for a load/store operation.
1742 * Return the host address and into @flags.
1745 typedef struct MMULookupPageData
{
1746 CPUTLBEntryFull
*full
;
1751 } MMULookupPageData
;
1753 typedef struct MMULookupLocals
{
1754 MMULookupPageData page
[2];
1760 * mmu_lookup1: translate one page
1762 * @data: lookup parameters
1763 * @mmu_idx: virtual address context
1764 * @access_type: load/store/code
1765 * @ra: return address into tcg generated code, or 0
1767 * Resolve the translation for the one page at @data.addr, filling in
1768 * the rest of @data with the results. If the translation fails,
1769 * tlb_fill will longjmp out. Return true if the softmmu tlb for
1770 * @mmu_idx may have resized.
1772 static bool mmu_lookup1(CPUArchState
*env
, MMULookupPageData
*data
,
1773 int mmu_idx
, MMUAccessType access_type
, uintptr_t ra
)
1775 vaddr addr
= data
->addr
;
1776 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1777 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
1778 uint64_t tlb_addr
= tlb_read_idx(entry
, access_type
);
1779 bool maybe_resized
= false;
1780 CPUTLBEntryFull
*full
;
1783 /* If the TLB entry is for a different page, reload and try again. */
1784 if (!tlb_hit(tlb_addr
, addr
)) {
1785 if (!victim_tlb_hit(env
, mmu_idx
, index
, access_type
,
1786 addr
& TARGET_PAGE_MASK
)) {
1787 tlb_fill(env_cpu(env
), addr
, data
->size
, access_type
, mmu_idx
, ra
);
1788 maybe_resized
= true;
1789 index
= tlb_index(env
, mmu_idx
, addr
);
1790 entry
= tlb_entry(env
, mmu_idx
, addr
);
1792 tlb_addr
= tlb_read_idx(entry
, access_type
) & ~TLB_INVALID_MASK
;
1795 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1796 flags
= tlb_addr
& (TLB_FLAGS_MASK
& ~TLB_FORCE_SLOW
);
1797 flags
|= full
->slow_flags
[access_type
];
1800 data
->flags
= flags
;
1801 /* Compute haddr speculatively; depending on flags it might be invalid. */
1802 data
->haddr
= (void *)((uintptr_t)addr
+ entry
->addend
);
1804 return maybe_resized
;
1808 * mmu_watch_or_dirty
1810 * @data: lookup parameters
1811 * @access_type: load/store/code
1812 * @ra: return address into tcg generated code, or 0
1814 * Trigger watchpoints for @data.addr:@data.size;
1815 * record writes to protected clean pages.
1817 static void mmu_watch_or_dirty(CPUArchState
*env
, MMULookupPageData
*data
,
1818 MMUAccessType access_type
, uintptr_t ra
)
1820 CPUTLBEntryFull
*full
= data
->full
;
1821 vaddr addr
= data
->addr
;
1822 int flags
= data
->flags
;
1823 int size
= data
->size
;
1825 /* On watchpoint hit, this will longjmp out. */
1826 if (flags
& TLB_WATCHPOINT
) {
1827 int wp
= access_type
== MMU_DATA_STORE
? BP_MEM_WRITE
: BP_MEM_READ
;
1828 cpu_check_watchpoint(env_cpu(env
), addr
, size
, full
->attrs
, wp
, ra
);
1829 flags
&= ~TLB_WATCHPOINT
;
1832 /* Note that notdirty is only set for writes. */
1833 if (flags
& TLB_NOTDIRTY
) {
1834 notdirty_write(env_cpu(env
), addr
, size
, full
, ra
);
1835 flags
&= ~TLB_NOTDIRTY
;
1837 data
->flags
= flags
;
1841 * mmu_lookup: translate page(s)
1843 * @addr: virtual address
1844 * @oi: combined mmu_idx and MemOp
1845 * @ra: return address into tcg generated code, or 0
1846 * @access_type: load/store/code
1849 * Resolve the translation for the page(s) beginning at @addr, for MemOp.size
1850 * bytes. Return true if the lookup crosses a page boundary.
1852 static bool mmu_lookup(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
1853 uintptr_t ra
, MMUAccessType type
, MMULookupLocals
*l
)
1859 l
->memop
= get_memop(oi
);
1860 l
->mmu_idx
= get_mmuidx(oi
);
1862 tcg_debug_assert(l
->mmu_idx
< NB_MMU_MODES
);
1864 /* Handle CPU specific unaligned behaviour */
1865 a_bits
= get_alignment_bits(l
->memop
);
1866 if (addr
& ((1 << a_bits
) - 1)) {
1867 cpu_unaligned_access(env_cpu(env
), addr
, type
, l
->mmu_idx
, ra
);
1870 l
->page
[0].addr
= addr
;
1871 l
->page
[0].size
= memop_size(l
->memop
);
1872 l
->page
[1].addr
= (addr
+ l
->page
[0].size
- 1) & TARGET_PAGE_MASK
;
1873 l
->page
[1].size
= 0;
1874 crosspage
= (addr
^ l
->page
[1].addr
) & TARGET_PAGE_MASK
;
1876 if (likely(!crosspage
)) {
1877 mmu_lookup1(env
, &l
->page
[0], l
->mmu_idx
, type
, ra
);
1879 flags
= l
->page
[0].flags
;
1880 if (unlikely(flags
& (TLB_WATCHPOINT
| TLB_NOTDIRTY
))) {
1881 mmu_watch_or_dirty(env
, &l
->page
[0], type
, ra
);
1883 if (unlikely(flags
& TLB_BSWAP
)) {
1884 l
->memop
^= MO_BSWAP
;
1887 /* Finish compute of page crossing. */
1888 int size0
= l
->page
[1].addr
- addr
;
1889 l
->page
[1].size
= l
->page
[0].size
- size0
;
1890 l
->page
[0].size
= size0
;
1893 * Lookup both pages, recognizing exceptions from either. If the
1894 * second lookup potentially resized, refresh first CPUTLBEntryFull.
1896 mmu_lookup1(env
, &l
->page
[0], l
->mmu_idx
, type
, ra
);
1897 if (mmu_lookup1(env
, &l
->page
[1], l
->mmu_idx
, type
, ra
)) {
1898 uintptr_t index
= tlb_index(env
, l
->mmu_idx
, addr
);
1899 l
->page
[0].full
= &env_tlb(env
)->d
[l
->mmu_idx
].fulltlb
[index
];
1902 flags
= l
->page
[0].flags
| l
->page
[1].flags
;
1903 if (unlikely(flags
& (TLB_WATCHPOINT
| TLB_NOTDIRTY
))) {
1904 mmu_watch_or_dirty(env
, &l
->page
[0], type
, ra
);
1905 mmu_watch_or_dirty(env
, &l
->page
[1], type
, ra
);
1909 * Since target/sparc is the only user of TLB_BSWAP, and all
1910 * Sparc accesses are aligned, any treatment across two pages
1911 * would be arbitrary. Refuse it until there's a use.
1913 tcg_debug_assert((flags
& TLB_BSWAP
) == 0);
1920 * Probe for an atomic operation. Do not allow unaligned operations,
1921 * or io operations to proceed. Return the host address.
1923 static void *atomic_mmu_lookup(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
1924 int size
, uintptr_t retaddr
)
1926 uintptr_t mmu_idx
= get_mmuidx(oi
);
1927 MemOp mop
= get_memop(oi
);
1928 int a_bits
= get_alignment_bits(mop
);
1933 CPUTLBEntryFull
*full
;
1935 tcg_debug_assert(mmu_idx
< NB_MMU_MODES
);
1937 /* Adjust the given return address. */
1938 retaddr
-= GETPC_ADJ
;
1940 /* Enforce guest required alignment. */
1941 if (unlikely(a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)))) {
1942 /* ??? Maybe indicate atomic op to cpu_unaligned_access */
1943 cpu_unaligned_access(env_cpu(env
), addr
, MMU_DATA_STORE
,
1947 /* Enforce qemu required alignment. */
1948 if (unlikely(addr
& (size
- 1))) {
1949 /* We get here if guest alignment was not requested,
1950 or was not enforced by cpu_unaligned_access above.
1951 We might widen the access and emulate, but for now
1952 mark an exception and exit the cpu loop. */
1953 goto stop_the_world
;
1956 index
= tlb_index(env
, mmu_idx
, addr
);
1957 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1959 /* Check TLB entry and enforce page permissions. */
1960 tlb_addr
= tlb_addr_write(tlbe
);
1961 if (!tlb_hit(tlb_addr
, addr
)) {
1962 if (!victim_tlb_hit(env
, mmu_idx
, index
, MMU_DATA_STORE
,
1963 addr
& TARGET_PAGE_MASK
)) {
1964 tlb_fill(env_cpu(env
), addr
, size
,
1965 MMU_DATA_STORE
, mmu_idx
, retaddr
);
1966 index
= tlb_index(env
, mmu_idx
, addr
);
1967 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1969 tlb_addr
= tlb_addr_write(tlbe
) & ~TLB_INVALID_MASK
;
1973 * Let the guest notice RMW on a write-only page.
1974 * We have just verified that the page is writable.
1975 * Subpage lookups may have left TLB_INVALID_MASK set,
1976 * but addr_read will only be -1 if PAGE_READ was unset.
1978 if (unlikely(tlbe
->addr_read
== -1)) {
1979 tlb_fill(env_cpu(env
), addr
, size
, MMU_DATA_LOAD
, mmu_idx
, retaddr
);
1981 * Since we don't support reads and writes to different
1982 * addresses, and we do have the proper page loaded for
1983 * write, this shouldn't ever return. But just in case,
1984 * handle via stop-the-world.
1986 goto stop_the_world
;
1988 /* Collect tlb flags for read. */
1989 tlb_addr
|= tlbe
->addr_read
;
1991 /* Notice an IO access or a needs-MMU-lookup access */
1992 if (unlikely(tlb_addr
& (TLB_MMIO
| TLB_DISCARD_WRITE
))) {
1993 /* There's really nothing that can be done to
1994 support this apart from stop-the-world. */
1995 goto stop_the_world
;
1998 hostaddr
= (void *)((uintptr_t)addr
+ tlbe
->addend
);
1999 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
2001 if (unlikely(tlb_addr
& TLB_NOTDIRTY
)) {
2002 notdirty_write(env_cpu(env
), addr
, size
, full
, retaddr
);
2005 if (unlikely(tlb_addr
& TLB_FORCE_SLOW
)) {
2008 if (full
->slow_flags
[MMU_DATA_STORE
] & TLB_WATCHPOINT
) {
2009 wp_flags
|= BP_MEM_WRITE
;
2011 if (full
->slow_flags
[MMU_DATA_LOAD
] & TLB_WATCHPOINT
) {
2012 wp_flags
|= BP_MEM_READ
;
2015 cpu_check_watchpoint(env_cpu(env
), addr
, size
,
2016 full
->attrs
, wp_flags
, retaddr
);
2023 cpu_loop_exit_atomic(env_cpu(env
), retaddr
);
2029 * We support two different access types. SOFTMMU_CODE_ACCESS is
2030 * specifically for reading instructions from system memory. It is
2031 * called by the translation loop and in some helpers where the code
2032 * is disassembled. It shouldn't be called directly by guest code.
2034 * For the benefit of TCG generated code, we want to avoid the
2035 * complication of ABI-specific return type promotion and always
2036 * return a value extended to the register size of the host. This is
2037 * tcg_target_long, except in the case of a 32-bit host and 64-bit
2038 * data, and for that we always have uint64_t.
2040 * We don't bother with this widened value for SOFTMMU_CODE_ACCESS.
2046 * @full: page parameters
2047 * @ret_be: accumulated data
2048 * @addr: virtual address
2049 * @size: number of bytes
2050 * @mmu_idx: virtual address context
2051 * @ra: return address into tcg generated code, or 0
2052 * Context: iothread lock held
2054 * Load @size bytes from @addr, which is memory-mapped i/o.
2055 * The bytes are concatenated in big-endian order with @ret_be.
2057 static uint64_t do_ld_mmio_beN(CPUArchState
*env
, CPUTLBEntryFull
*full
,
2058 uint64_t ret_be
, vaddr addr
, int size
,
2059 int mmu_idx
, MMUAccessType type
, uintptr_t ra
)
2063 tcg_debug_assert(size
> 0 && size
<= 8);
2065 /* Read aligned pieces up to 8 bytes. */
2066 switch ((size
| (int)addr
) & 7) {
2071 t
= io_readx(env
, full
, mmu_idx
, addr
, ra
, type
, MO_UB
);
2072 ret_be
= (ret_be
<< 8) | t
;
2078 t
= io_readx(env
, full
, mmu_idx
, addr
, ra
, type
, MO_BEUW
);
2079 ret_be
= (ret_be
<< 16) | t
;
2084 t
= io_readx(env
, full
, mmu_idx
, addr
, ra
, type
, MO_BEUL
);
2085 ret_be
= (ret_be
<< 32) | t
;
2090 return io_readx(env
, full
, mmu_idx
, addr
, ra
, type
, MO_BEUQ
);
2092 qemu_build_not_reached();
2100 * @p: translation parameters
2101 * @ret_be: accumulated data
2103 * Load @p->size bytes from @p->haddr, which is RAM.
2104 * The bytes to concatenated in big-endian order with @ret_be.
2106 static uint64_t do_ld_bytes_beN(MMULookupPageData
*p
, uint64_t ret_be
)
2108 uint8_t *haddr
= p
->haddr
;
2109 int i
, size
= p
->size
;
2111 for (i
= 0; i
< size
; i
++) {
2112 ret_be
= (ret_be
<< 8) | haddr
[i
];
2119 * @p: translation parameters
2120 * @ret_be: accumulated data
2122 * As do_ld_bytes_beN, but atomically on each aligned part.
2124 static uint64_t do_ld_parts_beN(MMULookupPageData
*p
, uint64_t ret_be
)
2126 void *haddr
= p
->haddr
;
2134 * Find minimum of alignment and size.
2135 * This is slightly stronger than required by MO_ATOM_SUBALIGN, which
2136 * would have only checked the low bits of addr|size once at the start,
2137 * but is just as easy.
2139 switch (((uintptr_t)haddr
| size
) & 7) {
2141 x
= cpu_to_be32(load_atomic4(haddr
));
2142 ret_be
= (ret_be
<< 32) | x
;
2147 x
= cpu_to_be16(load_atomic2(haddr
));
2148 ret_be
= (ret_be
<< 16) | x
;
2152 x
= *(uint8_t *)haddr
;
2153 ret_be
= (ret_be
<< 8) | x
;
2157 g_assert_not_reached();
2161 } while (size
!= 0);
2167 * @p: translation parameters
2168 * @ret_be: accumulated data
2170 * As do_ld_bytes_beN, but with one atomic load.
2171 * Four aligned bytes are guaranteed to cover the load.
2173 static uint64_t do_ld_whole_be4(MMULookupPageData
*p
, uint64_t ret_be
)
2175 int o
= p
->addr
& 3;
2176 uint32_t x
= load_atomic4(p
->haddr
- o
);
2180 x
>>= (4 - p
->size
) * 8;
2181 return (ret_be
<< (p
->size
* 8)) | x
;
2186 * @p: translation parameters
2187 * @ret_be: accumulated data
2189 * As do_ld_bytes_beN, but with one atomic load.
2190 * Eight aligned bytes are guaranteed to cover the load.
2192 static uint64_t do_ld_whole_be8(CPUArchState
*env
, uintptr_t ra
,
2193 MMULookupPageData
*p
, uint64_t ret_be
)
2195 int o
= p
->addr
& 7;
2196 uint64_t x
= load_atomic8_or_exit(env
, ra
, p
->haddr
- o
);
2200 x
>>= (8 - p
->size
) * 8;
2201 return (ret_be
<< (p
->size
* 8)) | x
;
2206 * @p: translation parameters
2207 * @ret_be: accumulated data
2209 * As do_ld_bytes_beN, but with one atomic load.
2210 * 16 aligned bytes are guaranteed to cover the load.
2212 static Int128
do_ld_whole_be16(CPUArchState
*env
, uintptr_t ra
,
2213 MMULookupPageData
*p
, uint64_t ret_be
)
2215 int o
= p
->addr
& 15;
2216 Int128 x
, y
= load_atomic16_or_exit(env
, ra
, p
->haddr
- o
);
2219 if (!HOST_BIG_ENDIAN
) {
2222 y
= int128_lshift(y
, o
* 8);
2223 y
= int128_urshift(y
, (16 - size
) * 8);
2224 x
= int128_make64(ret_be
);
2225 x
= int128_lshift(x
, size
* 8);
2226 return int128_or(x
, y
);
2230 * Wrapper for the above.
2232 static uint64_t do_ld_beN(CPUArchState
*env
, MMULookupPageData
*p
,
2233 uint64_t ret_be
, int mmu_idx
, MMUAccessType type
,
2234 MemOp mop
, uintptr_t ra
)
2237 unsigned tmp
, half_size
;
2239 if (unlikely(p
->flags
& TLB_MMIO
)) {
2240 QEMU_IOTHREAD_LOCK_GUARD();
2241 return do_ld_mmio_beN(env
, p
->full
, ret_be
, p
->addr
, p
->size
,
2246 * It is a given that we cross a page and therefore there is no
2247 * atomicity for the load as a whole, but subobjects may need attention.
2249 atom
= mop
& MO_ATOM_MASK
;
2251 case MO_ATOM_SUBALIGN
:
2252 return do_ld_parts_beN(p
, ret_be
);
2254 case MO_ATOM_IFALIGN_PAIR
:
2255 case MO_ATOM_WITHIN16_PAIR
:
2256 tmp
= mop
& MO_SIZE
;
2257 tmp
= tmp
? tmp
- 1 : 0;
2258 half_size
= 1 << tmp
;
2259 if (atom
== MO_ATOM_IFALIGN_PAIR
2260 ? p
->size
== half_size
2261 : p
->size
>= half_size
) {
2262 if (!HAVE_al8_fast
&& p
->size
< 4) {
2263 return do_ld_whole_be4(p
, ret_be
);
2265 return do_ld_whole_be8(env
, ra
, p
, ret_be
);
2270 case MO_ATOM_IFALIGN
:
2271 case MO_ATOM_WITHIN16
:
2273 return do_ld_bytes_beN(p
, ret_be
);
2276 g_assert_not_reached();
2281 * Wrapper for the above, for 8 < size < 16.
2283 static Int128
do_ld16_beN(CPUArchState
*env
, MMULookupPageData
*p
,
2284 uint64_t a
, int mmu_idx
, MemOp mop
, uintptr_t ra
)
2290 if (unlikely(p
->flags
& TLB_MMIO
)) {
2291 QEMU_IOTHREAD_LOCK_GUARD();
2292 a
= do_ld_mmio_beN(env
, p
->full
, a
, p
->addr
, size
- 8,
2293 mmu_idx
, MMU_DATA_LOAD
, ra
);
2294 b
= do_ld_mmio_beN(env
, p
->full
, 0, p
->addr
+ 8, 8,
2295 mmu_idx
, MMU_DATA_LOAD
, ra
);
2296 return int128_make128(b
, a
);
2300 * It is a given that we cross a page and therefore there is no
2301 * atomicity for the load as a whole, but subobjects may need attention.
2303 atom
= mop
& MO_ATOM_MASK
;
2305 case MO_ATOM_SUBALIGN
:
2307 a
= do_ld_parts_beN(p
, a
);
2308 p
->haddr
+= size
- 8;
2310 b
= do_ld_parts_beN(p
, 0);
2313 case MO_ATOM_WITHIN16_PAIR
:
2314 /* Since size > 8, this is the half that must be atomic. */
2315 return do_ld_whole_be16(env
, ra
, p
, a
);
2317 case MO_ATOM_IFALIGN_PAIR
:
2319 * Since size > 8, both halves are misaligned,
2320 * and so neither is atomic.
2322 case MO_ATOM_IFALIGN
:
2323 case MO_ATOM_WITHIN16
:
2326 a
= do_ld_bytes_beN(p
, a
);
2327 b
= ldq_be_p(p
->haddr
+ size
- 8);
2331 g_assert_not_reached();
2334 return int128_make128(b
, a
);
2337 static uint8_t do_ld_1(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2338 MMUAccessType type
, uintptr_t ra
)
2340 if (unlikely(p
->flags
& TLB_MMIO
)) {
2341 return io_readx(env
, p
->full
, mmu_idx
, p
->addr
, ra
, type
, MO_UB
);
2343 return *(uint8_t *)p
->haddr
;
2347 static uint16_t do_ld_2(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2348 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2352 if (unlikely(p
->flags
& TLB_MMIO
)) {
2353 QEMU_IOTHREAD_LOCK_GUARD();
2354 ret
= do_ld_mmio_beN(env
, p
->full
, 0, p
->addr
, 2, mmu_idx
, type
, ra
);
2355 if ((memop
& MO_BSWAP
) == MO_LE
) {
2359 /* Perform the load host endian, then swap if necessary. */
2360 ret
= load_atom_2(env
, ra
, p
->haddr
, memop
);
2361 if (memop
& MO_BSWAP
) {
2368 static uint32_t do_ld_4(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2369 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2373 if (unlikely(p
->flags
& TLB_MMIO
)) {
2374 QEMU_IOTHREAD_LOCK_GUARD();
2375 ret
= do_ld_mmio_beN(env
, p
->full
, 0, p
->addr
, 4, mmu_idx
, type
, ra
);
2376 if ((memop
& MO_BSWAP
) == MO_LE
) {
2380 /* Perform the load host endian. */
2381 ret
= load_atom_4(env
, ra
, p
->haddr
, memop
);
2382 if (memop
& MO_BSWAP
) {
2389 static uint64_t do_ld_8(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2390 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2394 if (unlikely(p
->flags
& TLB_MMIO
)) {
2395 QEMU_IOTHREAD_LOCK_GUARD();
2396 ret
= do_ld_mmio_beN(env
, p
->full
, 0, p
->addr
, 8, mmu_idx
, type
, ra
);
2397 if ((memop
& MO_BSWAP
) == MO_LE
) {
2401 /* Perform the load host endian. */
2402 ret
= load_atom_8(env
, ra
, p
->haddr
, memop
);
2403 if (memop
& MO_BSWAP
) {
2410 static uint8_t do_ld1_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2411 uintptr_t ra
, MMUAccessType access_type
)
2416 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2417 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2418 tcg_debug_assert(!crosspage
);
2420 return do_ld_1(env
, &l
.page
[0], l
.mmu_idx
, access_type
, ra
);
2423 tcg_target_ulong
helper_ldub_mmu(CPUArchState
*env
, uint64_t addr
,
2424 MemOpIdx oi
, uintptr_t retaddr
)
2426 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_8
);
2427 return do_ld1_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2430 static uint16_t do_ld2_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2431 uintptr_t ra
, MMUAccessType access_type
)
2438 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2439 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2440 if (likely(!crosspage
)) {
2441 return do_ld_2(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2444 a
= do_ld_1(env
, &l
.page
[0], l
.mmu_idx
, access_type
, ra
);
2445 b
= do_ld_1(env
, &l
.page
[1], l
.mmu_idx
, access_type
, ra
);
2447 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2455 tcg_target_ulong
helper_lduw_mmu(CPUArchState
*env
, uint64_t addr
,
2456 MemOpIdx oi
, uintptr_t retaddr
)
2458 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2459 return do_ld2_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2462 static uint32_t do_ld4_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2463 uintptr_t ra
, MMUAccessType access_type
)
2469 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2470 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2471 if (likely(!crosspage
)) {
2472 return do_ld_4(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2475 ret
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2476 ret
= do_ld_beN(env
, &l
.page
[1], ret
, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2477 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2483 tcg_target_ulong
helper_ldul_mmu(CPUArchState
*env
, uint64_t addr
,
2484 MemOpIdx oi
, uintptr_t retaddr
)
2486 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2487 return do_ld4_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2490 static uint64_t do_ld8_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2491 uintptr_t ra
, MMUAccessType access_type
)
2497 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2498 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2499 if (likely(!crosspage
)) {
2500 return do_ld_8(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2503 ret
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2504 ret
= do_ld_beN(env
, &l
.page
[1], ret
, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2505 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2511 uint64_t helper_ldq_mmu(CPUArchState
*env
, uint64_t addr
,
2512 MemOpIdx oi
, uintptr_t retaddr
)
2514 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
2515 return do_ld8_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2519 * Provide signed versions of the load routines as well. We can of course
2520 * avoid this for 64-bit data, or for 32-bit data on 32-bit host.
2523 tcg_target_ulong
helper_ldsb_mmu(CPUArchState
*env
, uint64_t addr
,
2524 MemOpIdx oi
, uintptr_t retaddr
)
2526 return (int8_t)helper_ldub_mmu(env
, addr
, oi
, retaddr
);
2529 tcg_target_ulong
helper_ldsw_mmu(CPUArchState
*env
, uint64_t addr
,
2530 MemOpIdx oi
, uintptr_t retaddr
)
2532 return (int16_t)helper_lduw_mmu(env
, addr
, oi
, retaddr
);
2535 tcg_target_ulong
helper_ldsl_mmu(CPUArchState
*env
, uint64_t addr
,
2536 MemOpIdx oi
, uintptr_t retaddr
)
2538 return (int32_t)helper_ldul_mmu(env
, addr
, oi
, retaddr
);
2541 static Int128
do_ld16_mmu(CPUArchState
*env
, vaddr addr
,
2542 MemOpIdx oi
, uintptr_t ra
)
2550 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2551 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_LOAD
, &l
);
2552 if (likely(!crosspage
)) {
2553 if (unlikely(l
.page
[0].flags
& TLB_MMIO
)) {
2554 QEMU_IOTHREAD_LOCK_GUARD();
2555 a
= do_ld_mmio_beN(env
, l
.page
[0].full
, 0, addr
, 8,
2556 l
.mmu_idx
, MMU_DATA_LOAD
, ra
);
2557 b
= do_ld_mmio_beN(env
, l
.page
[0].full
, 0, addr
+ 8, 8,
2558 l
.mmu_idx
, MMU_DATA_LOAD
, ra
);
2559 ret
= int128_make128(b
, a
);
2560 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2561 ret
= bswap128(ret
);
2564 /* Perform the load host endian. */
2565 ret
= load_atom_16(env
, ra
, l
.page
[0].haddr
, l
.memop
);
2566 if (l
.memop
& MO_BSWAP
) {
2567 ret
= bswap128(ret
);
2573 first
= l
.page
[0].size
;
2575 MemOp mop8
= (l
.memop
& ~MO_SIZE
) | MO_64
;
2577 a
= do_ld_8(env
, &l
.page
[0], l
.mmu_idx
, MMU_DATA_LOAD
, mop8
, ra
);
2578 b
= do_ld_8(env
, &l
.page
[1], l
.mmu_idx
, MMU_DATA_LOAD
, mop8
, ra
);
2579 if ((mop8
& MO_BSWAP
) == MO_LE
) {
2580 ret
= int128_make128(a
, b
);
2582 ret
= int128_make128(b
, a
);
2588 a
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
,
2589 MMU_DATA_LOAD
, l
.memop
, ra
);
2590 ret
= do_ld16_beN(env
, &l
.page
[1], a
, l
.mmu_idx
, l
.memop
, ra
);
2592 ret
= do_ld16_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, l
.memop
, ra
);
2593 b
= int128_getlo(ret
);
2594 ret
= int128_lshift(ret
, l
.page
[1].size
* 8);
2595 a
= int128_gethi(ret
);
2596 b
= do_ld_beN(env
, &l
.page
[1], b
, l
.mmu_idx
,
2597 MMU_DATA_LOAD
, l
.memop
, ra
);
2598 ret
= int128_make128(b
, a
);
2600 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2601 ret
= bswap128(ret
);
2606 Int128
helper_ld16_mmu(CPUArchState
*env
, uint64_t addr
,
2607 uint32_t oi
, uintptr_t retaddr
)
2609 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
2610 return do_ld16_mmu(env
, addr
, oi
, retaddr
);
2613 Int128
helper_ld_i128(CPUArchState
*env
, uint64_t addr
, uint32_t oi
)
2615 return helper_ld16_mmu(env
, addr
, oi
, GETPC());
2619 * Load helpers for cpu_ldst.h.
2622 static void plugin_load_cb(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
)
2624 qemu_plugin_vcpu_mem_cb(env_cpu(env
), addr
, oi
, QEMU_PLUGIN_MEM_R
);
2627 uint8_t cpu_ldb_mmu(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
, uintptr_t ra
)
2631 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_UB
);
2632 ret
= do_ld1_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2633 plugin_load_cb(env
, addr
, oi
);
2637 uint16_t cpu_ldw_mmu(CPUArchState
*env
, abi_ptr addr
,
2638 MemOpIdx oi
, uintptr_t ra
)
2642 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2643 ret
= do_ld2_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2644 plugin_load_cb(env
, addr
, oi
);
2648 uint32_t cpu_ldl_mmu(CPUArchState
*env
, abi_ptr addr
,
2649 MemOpIdx oi
, uintptr_t ra
)
2653 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2654 ret
= do_ld4_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2655 plugin_load_cb(env
, addr
, oi
);
2659 uint64_t cpu_ldq_mmu(CPUArchState
*env
, abi_ptr addr
,
2660 MemOpIdx oi
, uintptr_t ra
)
2664 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
2665 ret
= do_ld8_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2666 plugin_load_cb(env
, addr
, oi
);
2670 Int128
cpu_ld16_mmu(CPUArchState
*env
, abi_ptr addr
,
2671 MemOpIdx oi
, uintptr_t ra
)
2675 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
2676 ret
= do_ld16_mmu(env
, addr
, oi
, ra
);
2677 plugin_load_cb(env
, addr
, oi
);
2688 * @full: page parameters
2689 * @val_le: data to store
2690 * @addr: virtual address
2691 * @size: number of bytes
2692 * @mmu_idx: virtual address context
2693 * @ra: return address into tcg generated code, or 0
2694 * Context: iothread lock held
2696 * Store @size bytes at @addr, which is memory-mapped i/o.
2697 * The bytes to store are extracted in little-endian order from @val_le;
2698 * return the bytes of @val_le beyond @p->size that have not been stored.
2700 static uint64_t do_st_mmio_leN(CPUArchState
*env
, CPUTLBEntryFull
*full
,
2701 uint64_t val_le
, vaddr addr
, int size
,
2702 int mmu_idx
, uintptr_t ra
)
2704 tcg_debug_assert(size
> 0 && size
<= 8);
2707 /* Store aligned pieces up to 8 bytes. */
2708 switch ((size
| (int)addr
) & 7) {
2713 io_writex(env
, full
, mmu_idx
, val_le
, addr
, ra
, MO_UB
);
2720 io_writex(env
, full
, mmu_idx
, val_le
, addr
, ra
, MO_LEUW
);
2726 io_writex(env
, full
, mmu_idx
, val_le
, addr
, ra
, MO_LEUL
);
2732 io_writex(env
, full
, mmu_idx
, val_le
, addr
, ra
, MO_LEUQ
);
2735 qemu_build_not_reached();
2743 * Wrapper for the above.
2745 static uint64_t do_st_leN(CPUArchState
*env
, MMULookupPageData
*p
,
2746 uint64_t val_le
, int mmu_idx
,
2747 MemOp mop
, uintptr_t ra
)
2750 unsigned tmp
, half_size
;
2752 if (unlikely(p
->flags
& TLB_MMIO
)) {
2753 QEMU_IOTHREAD_LOCK_GUARD();
2754 return do_st_mmio_leN(env
, p
->full
, val_le
, p
->addr
,
2755 p
->size
, mmu_idx
, ra
);
2756 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2757 return val_le
>> (p
->size
* 8);
2761 * It is a given that we cross a page and therefore there is no atomicity
2762 * for the store as a whole, but subobjects may need attention.
2764 atom
= mop
& MO_ATOM_MASK
;
2766 case MO_ATOM_SUBALIGN
:
2767 return store_parts_leN(p
->haddr
, p
->size
, val_le
);
2769 case MO_ATOM_IFALIGN_PAIR
:
2770 case MO_ATOM_WITHIN16_PAIR
:
2771 tmp
= mop
& MO_SIZE
;
2772 tmp
= tmp
? tmp
- 1 : 0;
2773 half_size
= 1 << tmp
;
2774 if (atom
== MO_ATOM_IFALIGN_PAIR
2775 ? p
->size
== half_size
2776 : p
->size
>= half_size
) {
2777 if (!HAVE_al8_fast
&& p
->size
<= 4) {
2778 return store_whole_le4(p
->haddr
, p
->size
, val_le
);
2779 } else if (HAVE_al8
) {
2780 return store_whole_le8(p
->haddr
, p
->size
, val_le
);
2782 cpu_loop_exit_atomic(env_cpu(env
), ra
);
2787 case MO_ATOM_IFALIGN
:
2788 case MO_ATOM_WITHIN16
:
2790 return store_bytes_leN(p
->haddr
, p
->size
, val_le
);
2793 g_assert_not_reached();
2798 * Wrapper for the above, for 8 < size < 16.
2800 static uint64_t do_st16_leN(CPUArchState
*env
, MMULookupPageData
*p
,
2801 Int128 val_le
, int mmu_idx
,
2802 MemOp mop
, uintptr_t ra
)
2807 if (unlikely(p
->flags
& TLB_MMIO
)) {
2808 QEMU_IOTHREAD_LOCK_GUARD();
2809 do_st_mmio_leN(env
, p
->full
, int128_getlo(val_le
),
2810 p
->addr
, 8, mmu_idx
, ra
);
2811 return do_st_mmio_leN(env
, p
->full
, int128_gethi(val_le
),
2812 p
->addr
+ 8, size
- 8, mmu_idx
, ra
);
2813 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2814 return int128_gethi(val_le
) >> ((size
- 8) * 8);
2818 * It is a given that we cross a page and therefore there is no atomicity
2819 * for the store as a whole, but subobjects may need attention.
2821 atom
= mop
& MO_ATOM_MASK
;
2823 case MO_ATOM_SUBALIGN
:
2824 store_parts_leN(p
->haddr
, 8, int128_getlo(val_le
));
2825 return store_parts_leN(p
->haddr
+ 8, p
->size
- 8,
2826 int128_gethi(val_le
));
2828 case MO_ATOM_WITHIN16_PAIR
:
2829 /* Since size > 8, this is the half that must be atomic. */
2830 if (!HAVE_ATOMIC128_RW
) {
2831 cpu_loop_exit_atomic(env_cpu(env
), ra
);
2833 return store_whole_le16(p
->haddr
, p
->size
, val_le
);
2835 case MO_ATOM_IFALIGN_PAIR
:
2837 * Since size > 8, both halves are misaligned,
2838 * and so neither is atomic.
2840 case MO_ATOM_IFALIGN
:
2841 case MO_ATOM_WITHIN16
:
2843 stq_le_p(p
->haddr
, int128_getlo(val_le
));
2844 return store_bytes_leN(p
->haddr
+ 8, p
->size
- 8,
2845 int128_gethi(val_le
));
2848 g_assert_not_reached();
2852 static void do_st_1(CPUArchState
*env
, MMULookupPageData
*p
, uint8_t val
,
2853 int mmu_idx
, uintptr_t ra
)
2855 if (unlikely(p
->flags
& TLB_MMIO
)) {
2856 io_writex(env
, p
->full
, mmu_idx
, val
, p
->addr
, ra
, MO_UB
);
2857 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2860 *(uint8_t *)p
->haddr
= val
;
2864 static void do_st_2(CPUArchState
*env
, MMULookupPageData
*p
, uint16_t val
,
2865 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2867 if (unlikely(p
->flags
& TLB_MMIO
)) {
2868 if ((memop
& MO_BSWAP
) != MO_LE
) {
2871 QEMU_IOTHREAD_LOCK_GUARD();
2872 do_st_mmio_leN(env
, p
->full
, val
, p
->addr
, 2, mmu_idx
, ra
);
2873 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2876 /* Swap to host endian if necessary, then store. */
2877 if (memop
& MO_BSWAP
) {
2880 store_atom_2(env
, ra
, p
->haddr
, memop
, val
);
2884 static void do_st_4(CPUArchState
*env
, MMULookupPageData
*p
, uint32_t val
,
2885 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2887 if (unlikely(p
->flags
& TLB_MMIO
)) {
2888 if ((memop
& MO_BSWAP
) != MO_LE
) {
2891 QEMU_IOTHREAD_LOCK_GUARD();
2892 do_st_mmio_leN(env
, p
->full
, val
, p
->addr
, 4, mmu_idx
, ra
);
2893 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2896 /* Swap to host endian if necessary, then store. */
2897 if (memop
& MO_BSWAP
) {
2900 store_atom_4(env
, ra
, p
->haddr
, memop
, val
);
2904 static void do_st_8(CPUArchState
*env
, MMULookupPageData
*p
, uint64_t val
,
2905 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2907 if (unlikely(p
->flags
& TLB_MMIO
)) {
2908 if ((memop
& MO_BSWAP
) != MO_LE
) {
2911 QEMU_IOTHREAD_LOCK_GUARD();
2912 do_st_mmio_leN(env
, p
->full
, val
, p
->addr
, 8, mmu_idx
, ra
);
2913 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2916 /* Swap to host endian if necessary, then store. */
2917 if (memop
& MO_BSWAP
) {
2920 store_atom_8(env
, ra
, p
->haddr
, memop
, val
);
2924 void helper_stb_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
2925 MemOpIdx oi
, uintptr_t ra
)
2930 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_8
);
2931 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
2932 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2933 tcg_debug_assert(!crosspage
);
2935 do_st_1(env
, &l
.page
[0], val
, l
.mmu_idx
, ra
);
2938 static void do_st2_mmu(CPUArchState
*env
, vaddr addr
, uint16_t val
,
2939 MemOpIdx oi
, uintptr_t ra
)
2945 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
2946 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2947 if (likely(!crosspage
)) {
2948 do_st_2(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2952 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2953 a
= val
, b
= val
>> 8;
2955 b
= val
, a
= val
>> 8;
2957 do_st_1(env
, &l
.page
[0], a
, l
.mmu_idx
, ra
);
2958 do_st_1(env
, &l
.page
[1], b
, l
.mmu_idx
, ra
);
2961 void helper_stw_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
2962 MemOpIdx oi
, uintptr_t retaddr
)
2964 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2965 do_st2_mmu(env
, addr
, val
, oi
, retaddr
);
2968 static void do_st4_mmu(CPUArchState
*env
, vaddr addr
, uint32_t val
,
2969 MemOpIdx oi
, uintptr_t ra
)
2974 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
2975 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2976 if (likely(!crosspage
)) {
2977 do_st_4(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2981 /* Swap to little endian for simplicity, then store by bytes. */
2982 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
2985 val
= do_st_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2986 (void) do_st_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
2989 void helper_stl_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
2990 MemOpIdx oi
, uintptr_t retaddr
)
2992 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2993 do_st4_mmu(env
, addr
, val
, oi
, retaddr
);
2996 static void do_st8_mmu(CPUArchState
*env
, vaddr addr
, uint64_t val
,
2997 MemOpIdx oi
, uintptr_t ra
)
3002 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
3003 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
3004 if (likely(!crosspage
)) {
3005 do_st_8(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
3009 /* Swap to little endian for simplicity, then store by bytes. */
3010 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
3013 val
= do_st_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
3014 (void) do_st_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
3017 void helper_stq_mmu(CPUArchState
*env
, uint64_t addr
, uint64_t val
,
3018 MemOpIdx oi
, uintptr_t retaddr
)
3020 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
3021 do_st8_mmu(env
, addr
, val
, oi
, retaddr
);
3024 static void do_st16_mmu(CPUArchState
*env
, vaddr addr
, Int128 val
,
3025 MemOpIdx oi
, uintptr_t ra
)
3032 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
3033 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
3034 if (likely(!crosspage
)) {
3035 if (unlikely(l
.page
[0].flags
& TLB_MMIO
)) {
3036 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
3037 val
= bswap128(val
);
3039 a
= int128_getlo(val
);
3040 b
= int128_gethi(val
);
3041 QEMU_IOTHREAD_LOCK_GUARD();
3042 do_st_mmio_leN(env
, l
.page
[0].full
, a
, addr
, 8, l
.mmu_idx
, ra
);
3043 do_st_mmio_leN(env
, l
.page
[0].full
, b
, addr
+ 8, 8, l
.mmu_idx
, ra
);
3044 } else if (unlikely(l
.page
[0].flags
& TLB_DISCARD_WRITE
)) {
3047 /* Swap to host endian if necessary, then store. */
3048 if (l
.memop
& MO_BSWAP
) {
3049 val
= bswap128(val
);
3051 store_atom_16(env
, ra
, l
.page
[0].haddr
, l
.memop
, val
);
3056 first
= l
.page
[0].size
;
3058 MemOp mop8
= (l
.memop
& ~(MO_SIZE
| MO_BSWAP
)) | MO_64
;
3060 if (l
.memop
& MO_BSWAP
) {
3061 val
= bswap128(val
);
3063 if (HOST_BIG_ENDIAN
) {
3064 b
= int128_getlo(val
), a
= int128_gethi(val
);
3066 a
= int128_getlo(val
), b
= int128_gethi(val
);
3068 do_st_8(env
, &l
.page
[0], a
, l
.mmu_idx
, mop8
, ra
);
3069 do_st_8(env
, &l
.page
[1], b
, l
.mmu_idx
, mop8
, ra
);
3073 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
3074 val
= bswap128(val
);
3077 do_st_leN(env
, &l
.page
[0], int128_getlo(val
), l
.mmu_idx
, l
.memop
, ra
);
3078 val
= int128_urshift(val
, first
* 8);
3079 do_st16_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
3081 b
= do_st16_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
3082 do_st_leN(env
, &l
.page
[1], b
, l
.mmu_idx
, l
.memop
, ra
);
3086 void helper_st16_mmu(CPUArchState
*env
, uint64_t addr
, Int128 val
,
3087 MemOpIdx oi
, uintptr_t retaddr
)
3089 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
3090 do_st16_mmu(env
, addr
, val
, oi
, retaddr
);
3093 void helper_st_i128(CPUArchState
*env
, uint64_t addr
, Int128 val
, MemOpIdx oi
)
3095 helper_st16_mmu(env
, addr
, val
, oi
, GETPC());
3099 * Store Helpers for cpu_ldst.h
3102 static void plugin_store_cb(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
)
3104 qemu_plugin_vcpu_mem_cb(env_cpu(env
), addr
, oi
, QEMU_PLUGIN_MEM_W
);
3107 void cpu_stb_mmu(CPUArchState
*env
, abi_ptr addr
, uint8_t val
,
3108 MemOpIdx oi
, uintptr_t retaddr
)
3110 helper_stb_mmu(env
, addr
, val
, oi
, retaddr
);
3111 plugin_store_cb(env
, addr
, oi
);
3114 void cpu_stw_mmu(CPUArchState
*env
, abi_ptr addr
, uint16_t val
,
3115 MemOpIdx oi
, uintptr_t retaddr
)
3117 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
3118 do_st2_mmu(env
, addr
, val
, oi
, retaddr
);
3119 plugin_store_cb(env
, addr
, oi
);
3122 void cpu_stl_mmu(CPUArchState
*env
, abi_ptr addr
, uint32_t val
,
3123 MemOpIdx oi
, uintptr_t retaddr
)
3125 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
3126 do_st4_mmu(env
, addr
, val
, oi
, retaddr
);
3127 plugin_store_cb(env
, addr
, oi
);
3130 void cpu_stq_mmu(CPUArchState
*env
, abi_ptr addr
, uint64_t val
,
3131 MemOpIdx oi
, uintptr_t retaddr
)
3133 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
3134 do_st8_mmu(env
, addr
, val
, oi
, retaddr
);
3135 plugin_store_cb(env
, addr
, oi
);
3138 void cpu_st16_mmu(CPUArchState
*env
, abi_ptr addr
, Int128 val
,
3139 MemOpIdx oi
, uintptr_t retaddr
)
3141 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
3142 do_st16_mmu(env
, addr
, val
, oi
, retaddr
);
3143 plugin_store_cb(env
, addr
, oi
);
3146 #include "ldst_common.c.inc"
3149 * First set of functions passes in OI and RETADDR.
3150 * This makes them callable from other helpers.
3153 #define ATOMIC_NAME(X) \
3154 glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
3156 #define ATOMIC_MMU_CLEANUP
3158 #include "atomic_common.c.inc"
3161 #include "atomic_template.h"
3164 #include "atomic_template.h"
3167 #include "atomic_template.h"
3169 #ifdef CONFIG_ATOMIC64
3171 #include "atomic_template.h"
3174 #if defined(CONFIG_ATOMIC128) || HAVE_CMPXCHG128
3175 #define DATA_SIZE 16
3176 #include "atomic_template.h"
3179 /* Code access functions. */
3181 uint32_t cpu_ldub_code(CPUArchState
*env
, abi_ptr addr
)
3183 MemOpIdx oi
= make_memop_idx(MO_UB
, cpu_mmu_index(env
, true));
3184 return do_ld1_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3187 uint32_t cpu_lduw_code(CPUArchState
*env
, abi_ptr addr
)
3189 MemOpIdx oi
= make_memop_idx(MO_TEUW
, cpu_mmu_index(env
, true));
3190 return do_ld2_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3193 uint32_t cpu_ldl_code(CPUArchState
*env
, abi_ptr addr
)
3195 MemOpIdx oi
= make_memop_idx(MO_TEUL
, cpu_mmu_index(env
, true));
3196 return do_ld4_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3199 uint64_t cpu_ldq_code(CPUArchState
*env
, abi_ptr addr
)
3201 MemOpIdx oi
= make_memop_idx(MO_TEUQ
, cpu_mmu_index(env
, true));
3202 return do_ld8_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3205 uint8_t cpu_ldb_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3206 MemOpIdx oi
, uintptr_t retaddr
)
3208 return do_ld1_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3211 uint16_t cpu_ldw_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3212 MemOpIdx oi
, uintptr_t retaddr
)
3214 return do_ld2_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3217 uint32_t cpu_ldl_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3218 MemOpIdx oi
, uintptr_t retaddr
)
3220 return do_ld4_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3223 uint64_t cpu_ldq_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3224 MemOpIdx oi
, uintptr_t retaddr
)
3226 return do_ld8_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);