2 * Common CPU TLB handling
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
22 #include "hw/core/tcg-cpu-ops.h"
23 #include "exec/exec-all.h"
24 #include "exec/memory.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/cputlb.h"
27 #include "exec/memory-internal.h"
28 #include "exec/ram_addr.h"
30 #include "qemu/error-report.h"
32 #include "exec/helper-proto-common.h"
33 #include "qemu/atomic.h"
34 #include "qemu/atomic128.h"
35 #include "exec/translate-all.h"
40 #include "qemu/plugin-memory.h"
42 #include "tcg/tcg-ldst.h"
43 #include "tcg/oversized-guest.h"
45 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
46 /* #define DEBUG_TLB */
47 /* #define DEBUG_TLB_LOG */
50 # define DEBUG_TLB_GATE 1
52 # define DEBUG_TLB_LOG_GATE 1
54 # define DEBUG_TLB_LOG_GATE 0
57 # define DEBUG_TLB_GATE 0
58 # define DEBUG_TLB_LOG_GATE 0
61 #define tlb_debug(fmt, ...) do { \
62 if (DEBUG_TLB_LOG_GATE) { \
63 qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
65 } else if (DEBUG_TLB_GATE) { \
66 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
70 #define assert_cpu_is_self(cpu) do { \
71 if (DEBUG_TLB_GATE) { \
72 g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \
76 /* run_on_cpu_data.target_ptr should always be big enough for a
77 * target_ulong even on 32 bit builds */
78 QEMU_BUILD_BUG_ON(sizeof(target_ulong
) > sizeof(run_on_cpu_data
));
80 /* We currently can't handle more than 16 bits in the MMUIDX bitmask.
82 QEMU_BUILD_BUG_ON(NB_MMU_MODES
> 16);
83 #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
85 static inline size_t tlb_n_entries(CPUTLBDescFast
*fast
)
87 return (fast
->mask
>> CPU_TLB_ENTRY_BITS
) + 1;
90 static inline size_t sizeof_tlb(CPUTLBDescFast
*fast
)
92 return fast
->mask
+ (1 << CPU_TLB_ENTRY_BITS
);
95 static void tlb_window_reset(CPUTLBDesc
*desc
, int64_t ns
,
98 desc
->window_begin_ns
= ns
;
99 desc
->window_max_entries
= max_entries
;
102 static void tb_jmp_cache_clear_page(CPUState
*cpu
, target_ulong page_addr
)
104 CPUJumpCache
*jc
= cpu
->tb_jmp_cache
;
111 i0
= tb_jmp_cache_hash_page(page_addr
);
112 for (i
= 0; i
< TB_JMP_PAGE_SIZE
; i
++) {
113 qatomic_set(&jc
->array
[i0
+ i
].tb
, NULL
);
118 * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
119 * @desc: The CPUTLBDesc portion of the TLB
120 * @fast: The CPUTLBDescFast portion of the same TLB
122 * Called with tlb_lock_held.
124 * We have two main constraints when resizing a TLB: (1) we only resize it
125 * on a TLB flush (otherwise we'd have to take a perf hit by either rehashing
126 * the array or unnecessarily flushing it), which means we do not control how
127 * frequently the resizing can occur; (2) we don't have access to the guest's
128 * future scheduling decisions, and therefore have to decide the magnitude of
129 * the resize based on past observations.
131 * In general, a memory-hungry process can benefit greatly from an appropriately
132 * sized TLB, since a guest TLB miss is very expensive. This doesn't mean that
133 * we just have to make the TLB as large as possible; while an oversized TLB
134 * results in minimal TLB miss rates, it also takes longer to be flushed
135 * (flushes can be _very_ frequent), and the reduced locality can also hurt
138 * To achieve near-optimal performance for all kinds of workloads, we:
140 * 1. Aggressively increase the size of the TLB when the use rate of the
141 * TLB being flushed is high, since it is likely that in the near future this
142 * memory-hungry process will execute again, and its memory hungriness will
143 * probably be similar.
145 * 2. Slowly reduce the size of the TLB as the use rate declines over a
146 * reasonably large time window. The rationale is that if in such a time window
147 * we have not observed a high TLB use rate, it is likely that we won't observe
148 * it in the near future. In that case, once a time window expires we downsize
149 * the TLB to match the maximum use rate observed in the window.
151 * 3. Try to keep the maximum use rate in a time window in the 30-70% range,
152 * since in that range performance is likely near-optimal. Recall that the TLB
153 * is direct mapped, so we want the use rate to be low (or at least not too
154 * high), since otherwise we are likely to have a significant amount of
157 static void tlb_mmu_resize_locked(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
,
160 size_t old_size
= tlb_n_entries(fast
);
162 size_t new_size
= old_size
;
163 int64_t window_len_ms
= 100;
164 int64_t window_len_ns
= window_len_ms
* 1000 * 1000;
165 bool window_expired
= now
> desc
->window_begin_ns
+ window_len_ns
;
167 if (desc
->n_used_entries
> desc
->window_max_entries
) {
168 desc
->window_max_entries
= desc
->n_used_entries
;
170 rate
= desc
->window_max_entries
* 100 / old_size
;
173 new_size
= MIN(old_size
<< 1, 1 << CPU_TLB_DYN_MAX_BITS
);
174 } else if (rate
< 30 && window_expired
) {
175 size_t ceil
= pow2ceil(desc
->window_max_entries
);
176 size_t expected_rate
= desc
->window_max_entries
* 100 / ceil
;
179 * Avoid undersizing when the max number of entries seen is just below
180 * a pow2. For instance, if max_entries == 1025, the expected use rate
181 * would be 1025/2048==50%. However, if max_entries == 1023, we'd get
182 * 1023/1024==99.9% use rate, so we'd likely end up doubling the size
183 * later. Thus, make sure that the expected use rate remains below 70%.
184 * (and since we double the size, that means the lowest rate we'd
185 * expect to get is 35%, which is still in the 30-70% range where
186 * we consider that the size is appropriate.)
188 if (expected_rate
> 70) {
191 new_size
= MAX(ceil
, 1 << CPU_TLB_DYN_MIN_BITS
);
194 if (new_size
== old_size
) {
195 if (window_expired
) {
196 tlb_window_reset(desc
, now
, desc
->n_used_entries
);
202 g_free(desc
->fulltlb
);
204 tlb_window_reset(desc
, now
, 0);
205 /* desc->n_used_entries is cleared by the caller */
206 fast
->mask
= (new_size
- 1) << CPU_TLB_ENTRY_BITS
;
207 fast
->table
= g_try_new(CPUTLBEntry
, new_size
);
208 desc
->fulltlb
= g_try_new(CPUTLBEntryFull
, new_size
);
211 * If the allocations fail, try smaller sizes. We just freed some
212 * memory, so going back to half of new_size has a good chance of working.
213 * Increased memory pressure elsewhere in the system might cause the
214 * allocations to fail though, so we progressively reduce the allocation
215 * size, aborting if we cannot even allocate the smallest TLB we support.
217 while (fast
->table
== NULL
|| desc
->fulltlb
== NULL
) {
218 if (new_size
== (1 << CPU_TLB_DYN_MIN_BITS
)) {
219 error_report("%s: %s", __func__
, strerror(errno
));
222 new_size
= MAX(new_size
>> 1, 1 << CPU_TLB_DYN_MIN_BITS
);
223 fast
->mask
= (new_size
- 1) << CPU_TLB_ENTRY_BITS
;
226 g_free(desc
->fulltlb
);
227 fast
->table
= g_try_new(CPUTLBEntry
, new_size
);
228 desc
->fulltlb
= g_try_new(CPUTLBEntryFull
, new_size
);
232 static void tlb_mmu_flush_locked(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
)
234 desc
->n_used_entries
= 0;
235 desc
->large_page_addr
= -1;
236 desc
->large_page_mask
= -1;
238 memset(fast
->table
, -1, sizeof_tlb(fast
));
239 memset(desc
->vtable
, -1, sizeof(desc
->vtable
));
242 static void tlb_flush_one_mmuidx_locked(CPUArchState
*env
, int mmu_idx
,
245 CPUTLBDesc
*desc
= &env_tlb(env
)->d
[mmu_idx
];
246 CPUTLBDescFast
*fast
= &env_tlb(env
)->f
[mmu_idx
];
248 tlb_mmu_resize_locked(desc
, fast
, now
);
249 tlb_mmu_flush_locked(desc
, fast
);
252 static void tlb_mmu_init(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
, int64_t now
)
254 size_t n_entries
= 1 << CPU_TLB_DYN_DEFAULT_BITS
;
256 tlb_window_reset(desc
, now
, 0);
257 desc
->n_used_entries
= 0;
258 fast
->mask
= (n_entries
- 1) << CPU_TLB_ENTRY_BITS
;
259 fast
->table
= g_new(CPUTLBEntry
, n_entries
);
260 desc
->fulltlb
= g_new(CPUTLBEntryFull
, n_entries
);
261 tlb_mmu_flush_locked(desc
, fast
);
264 static inline void tlb_n_used_entries_inc(CPUArchState
*env
, uintptr_t mmu_idx
)
266 env_tlb(env
)->d
[mmu_idx
].n_used_entries
++;
269 static inline void tlb_n_used_entries_dec(CPUArchState
*env
, uintptr_t mmu_idx
)
271 env_tlb(env
)->d
[mmu_idx
].n_used_entries
--;
274 void tlb_init(CPUState
*cpu
)
276 CPUArchState
*env
= cpu
->env_ptr
;
277 int64_t now
= get_clock_realtime();
280 qemu_spin_init(&env_tlb(env
)->c
.lock
);
282 /* All tlbs are initialized flushed. */
283 env_tlb(env
)->c
.dirty
= 0;
285 for (i
= 0; i
< NB_MMU_MODES
; i
++) {
286 tlb_mmu_init(&env_tlb(env
)->d
[i
], &env_tlb(env
)->f
[i
], now
);
290 void tlb_destroy(CPUState
*cpu
)
292 CPUArchState
*env
= cpu
->env_ptr
;
295 qemu_spin_destroy(&env_tlb(env
)->c
.lock
);
296 for (i
= 0; i
< NB_MMU_MODES
; i
++) {
297 CPUTLBDesc
*desc
= &env_tlb(env
)->d
[i
];
298 CPUTLBDescFast
*fast
= &env_tlb(env
)->f
[i
];
301 g_free(desc
->fulltlb
);
305 /* flush_all_helper: run fn across all cpus
307 * If the wait flag is set then the src cpu's helper will be queued as
308 * "safe" work and the loop exited creating a synchronisation point
309 * where all queued work will be finished before execution starts
312 static void flush_all_helper(CPUState
*src
, run_on_cpu_func fn
,
319 async_run_on_cpu(cpu
, fn
, d
);
324 void tlb_flush_counts(size_t *pfull
, size_t *ppart
, size_t *pelide
)
327 size_t full
= 0, part
= 0, elide
= 0;
330 CPUArchState
*env
= cpu
->env_ptr
;
332 full
+= qatomic_read(&env_tlb(env
)->c
.full_flush_count
);
333 part
+= qatomic_read(&env_tlb(env
)->c
.part_flush_count
);
334 elide
+= qatomic_read(&env_tlb(env
)->c
.elide_flush_count
);
341 static void tlb_flush_by_mmuidx_async_work(CPUState
*cpu
, run_on_cpu_data data
)
343 CPUArchState
*env
= cpu
->env_ptr
;
344 uint16_t asked
= data
.host_int
;
345 uint16_t all_dirty
, work
, to_clean
;
346 int64_t now
= get_clock_realtime();
348 assert_cpu_is_self(cpu
);
350 tlb_debug("mmu_idx:0x%04" PRIx16
"\n", asked
);
352 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
354 all_dirty
= env_tlb(env
)->c
.dirty
;
355 to_clean
= asked
& all_dirty
;
356 all_dirty
&= ~to_clean
;
357 env_tlb(env
)->c
.dirty
= all_dirty
;
359 for (work
= to_clean
; work
!= 0; work
&= work
- 1) {
360 int mmu_idx
= ctz32(work
);
361 tlb_flush_one_mmuidx_locked(env
, mmu_idx
, now
);
364 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
366 tcg_flush_jmp_cache(cpu
);
368 if (to_clean
== ALL_MMUIDX_BITS
) {
369 qatomic_set(&env_tlb(env
)->c
.full_flush_count
,
370 env_tlb(env
)->c
.full_flush_count
+ 1);
372 qatomic_set(&env_tlb(env
)->c
.part_flush_count
,
373 env_tlb(env
)->c
.part_flush_count
+ ctpop16(to_clean
));
374 if (to_clean
!= asked
) {
375 qatomic_set(&env_tlb(env
)->c
.elide_flush_count
,
376 env_tlb(env
)->c
.elide_flush_count
+
377 ctpop16(asked
& ~to_clean
));
382 void tlb_flush_by_mmuidx(CPUState
*cpu
, uint16_t idxmap
)
384 tlb_debug("mmu_idx: 0x%" PRIx16
"\n", idxmap
);
386 if (cpu
->created
&& !qemu_cpu_is_self(cpu
)) {
387 async_run_on_cpu(cpu
, tlb_flush_by_mmuidx_async_work
,
388 RUN_ON_CPU_HOST_INT(idxmap
));
390 tlb_flush_by_mmuidx_async_work(cpu
, RUN_ON_CPU_HOST_INT(idxmap
));
394 void tlb_flush(CPUState
*cpu
)
396 tlb_flush_by_mmuidx(cpu
, ALL_MMUIDX_BITS
);
399 void tlb_flush_by_mmuidx_all_cpus(CPUState
*src_cpu
, uint16_t idxmap
)
401 const run_on_cpu_func fn
= tlb_flush_by_mmuidx_async_work
;
403 tlb_debug("mmu_idx: 0x%"PRIx16
"\n", idxmap
);
405 flush_all_helper(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
406 fn(src_cpu
, RUN_ON_CPU_HOST_INT(idxmap
));
409 void tlb_flush_all_cpus(CPUState
*src_cpu
)
411 tlb_flush_by_mmuidx_all_cpus(src_cpu
, ALL_MMUIDX_BITS
);
414 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
, uint16_t idxmap
)
416 const run_on_cpu_func fn
= tlb_flush_by_mmuidx_async_work
;
418 tlb_debug("mmu_idx: 0x%"PRIx16
"\n", idxmap
);
420 flush_all_helper(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
421 async_safe_run_on_cpu(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
424 void tlb_flush_all_cpus_synced(CPUState
*src_cpu
)
426 tlb_flush_by_mmuidx_all_cpus_synced(src_cpu
, ALL_MMUIDX_BITS
);
429 static bool tlb_hit_page_mask_anyprot(CPUTLBEntry
*tlb_entry
,
430 vaddr page
, vaddr mask
)
433 mask
&= TARGET_PAGE_MASK
| TLB_INVALID_MASK
;
435 return (page
== (tlb_entry
->addr_read
& mask
) ||
436 page
== (tlb_addr_write(tlb_entry
) & mask
) ||
437 page
== (tlb_entry
->addr_code
& mask
));
440 static inline bool tlb_hit_page_anyprot(CPUTLBEntry
*tlb_entry
, vaddr page
)
442 return tlb_hit_page_mask_anyprot(tlb_entry
, page
, -1);
446 * tlb_entry_is_empty - return true if the entry is not in use
447 * @te: pointer to CPUTLBEntry
449 static inline bool tlb_entry_is_empty(const CPUTLBEntry
*te
)
451 return te
->addr_read
== -1 && te
->addr_write
== -1 && te
->addr_code
== -1;
454 /* Called with tlb_c.lock held */
455 static bool tlb_flush_entry_mask_locked(CPUTLBEntry
*tlb_entry
,
459 if (tlb_hit_page_mask_anyprot(tlb_entry
, page
, mask
)) {
460 memset(tlb_entry
, -1, sizeof(*tlb_entry
));
466 static inline bool tlb_flush_entry_locked(CPUTLBEntry
*tlb_entry
, vaddr page
)
468 return tlb_flush_entry_mask_locked(tlb_entry
, page
, -1);
471 /* Called with tlb_c.lock held */
472 static void tlb_flush_vtlb_page_mask_locked(CPUArchState
*env
, int mmu_idx
,
476 CPUTLBDesc
*d
= &env_tlb(env
)->d
[mmu_idx
];
479 assert_cpu_is_self(env_cpu(env
));
480 for (k
= 0; k
< CPU_VTLB_SIZE
; k
++) {
481 if (tlb_flush_entry_mask_locked(&d
->vtable
[k
], page
, mask
)) {
482 tlb_n_used_entries_dec(env
, mmu_idx
);
487 static inline void tlb_flush_vtlb_page_locked(CPUArchState
*env
, int mmu_idx
,
490 tlb_flush_vtlb_page_mask_locked(env
, mmu_idx
, page
, -1);
493 static void tlb_flush_page_locked(CPUArchState
*env
, int midx
, vaddr page
)
495 vaddr lp_addr
= env_tlb(env
)->d
[midx
].large_page_addr
;
496 vaddr lp_mask
= env_tlb(env
)->d
[midx
].large_page_mask
;
498 /* Check if we need to flush due to large pages. */
499 if ((page
& lp_mask
) == lp_addr
) {
500 tlb_debug("forcing full flush midx %d (%"
501 VADDR_PRIx
"/%" VADDR_PRIx
")\n",
502 midx
, lp_addr
, lp_mask
);
503 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
505 if (tlb_flush_entry_locked(tlb_entry(env
, midx
, page
), page
)) {
506 tlb_n_used_entries_dec(env
, midx
);
508 tlb_flush_vtlb_page_locked(env
, midx
, page
);
513 * tlb_flush_page_by_mmuidx_async_0:
514 * @cpu: cpu on which to flush
515 * @addr: page of virtual address to flush
516 * @idxmap: set of mmu_idx to flush
518 * Helper for tlb_flush_page_by_mmuidx and friends, flush one page
519 * at @addr from the tlbs indicated by @idxmap from @cpu.
521 static void tlb_flush_page_by_mmuidx_async_0(CPUState
*cpu
,
525 CPUArchState
*env
= cpu
->env_ptr
;
528 assert_cpu_is_self(cpu
);
530 tlb_debug("page addr: %" VADDR_PRIx
" mmu_map:0x%x\n", addr
, idxmap
);
532 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
533 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
534 if ((idxmap
>> mmu_idx
) & 1) {
535 tlb_flush_page_locked(env
, mmu_idx
, addr
);
538 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
541 * Discard jump cache entries for any tb which might potentially
542 * overlap the flushed page, which includes the previous.
544 tb_jmp_cache_clear_page(cpu
, addr
- TARGET_PAGE_SIZE
);
545 tb_jmp_cache_clear_page(cpu
, addr
);
549 * tlb_flush_page_by_mmuidx_async_1:
550 * @cpu: cpu on which to flush
551 * @data: encoded addr + idxmap
553 * Helper for tlb_flush_page_by_mmuidx and friends, called through
554 * async_run_on_cpu. The idxmap parameter is encoded in the page
555 * offset of the target_ptr field. This limits the set of mmu_idx
556 * that can be passed via this method.
558 static void tlb_flush_page_by_mmuidx_async_1(CPUState
*cpu
,
559 run_on_cpu_data data
)
561 vaddr addr_and_idxmap
= data
.target_ptr
;
562 vaddr addr
= addr_and_idxmap
& TARGET_PAGE_MASK
;
563 uint16_t idxmap
= addr_and_idxmap
& ~TARGET_PAGE_MASK
;
565 tlb_flush_page_by_mmuidx_async_0(cpu
, addr
, idxmap
);
571 } TLBFlushPageByMMUIdxData
;
574 * tlb_flush_page_by_mmuidx_async_2:
575 * @cpu: cpu on which to flush
576 * @data: allocated addr + idxmap
578 * Helper for tlb_flush_page_by_mmuidx and friends, called through
579 * async_run_on_cpu. The addr+idxmap parameters are stored in a
580 * TLBFlushPageByMMUIdxData structure that has been allocated
581 * specifically for this helper. Free the structure when done.
583 static void tlb_flush_page_by_mmuidx_async_2(CPUState
*cpu
,
584 run_on_cpu_data data
)
586 TLBFlushPageByMMUIdxData
*d
= data
.host_ptr
;
588 tlb_flush_page_by_mmuidx_async_0(cpu
, d
->addr
, d
->idxmap
);
592 void tlb_flush_page_by_mmuidx(CPUState
*cpu
, vaddr addr
, uint16_t idxmap
)
594 tlb_debug("addr: %" VADDR_PRIx
" mmu_idx:%" PRIx16
"\n", addr
, idxmap
);
596 /* This should already be page aligned */
597 addr
&= TARGET_PAGE_MASK
;
599 if (qemu_cpu_is_self(cpu
)) {
600 tlb_flush_page_by_mmuidx_async_0(cpu
, addr
, idxmap
);
601 } else if (idxmap
< TARGET_PAGE_SIZE
) {
603 * Most targets have only a few mmu_idx. In the case where
604 * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid
605 * allocating memory for this operation.
607 async_run_on_cpu(cpu
, tlb_flush_page_by_mmuidx_async_1
,
608 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
610 TLBFlushPageByMMUIdxData
*d
= g_new(TLBFlushPageByMMUIdxData
, 1);
612 /* Otherwise allocate a structure, freed by the worker. */
615 async_run_on_cpu(cpu
, tlb_flush_page_by_mmuidx_async_2
,
616 RUN_ON_CPU_HOST_PTR(d
));
620 void tlb_flush_page(CPUState
*cpu
, vaddr addr
)
622 tlb_flush_page_by_mmuidx(cpu
, addr
, ALL_MMUIDX_BITS
);
625 void tlb_flush_page_by_mmuidx_all_cpus(CPUState
*src_cpu
, vaddr addr
,
628 tlb_debug("addr: %" VADDR_PRIx
" mmu_idx:%"PRIx16
"\n", addr
, idxmap
);
630 /* This should already be page aligned */
631 addr
&= TARGET_PAGE_MASK
;
634 * Allocate memory to hold addr+idxmap only when needed.
635 * See tlb_flush_page_by_mmuidx for details.
637 if (idxmap
< TARGET_PAGE_SIZE
) {
638 flush_all_helper(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
639 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
643 /* Allocate a separate data block for each destination cpu. */
644 CPU_FOREACH(dst_cpu
) {
645 if (dst_cpu
!= src_cpu
) {
646 TLBFlushPageByMMUIdxData
*d
647 = g_new(TLBFlushPageByMMUIdxData
, 1);
651 async_run_on_cpu(dst_cpu
, tlb_flush_page_by_mmuidx_async_2
,
652 RUN_ON_CPU_HOST_PTR(d
));
657 tlb_flush_page_by_mmuidx_async_0(src_cpu
, addr
, idxmap
);
660 void tlb_flush_page_all_cpus(CPUState
*src
, vaddr addr
)
662 tlb_flush_page_by_mmuidx_all_cpus(src
, addr
, ALL_MMUIDX_BITS
);
665 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
669 tlb_debug("addr: %" VADDR_PRIx
" mmu_idx:%"PRIx16
"\n", addr
, idxmap
);
671 /* This should already be page aligned */
672 addr
&= TARGET_PAGE_MASK
;
675 * Allocate memory to hold addr+idxmap only when needed.
676 * See tlb_flush_page_by_mmuidx for details.
678 if (idxmap
< TARGET_PAGE_SIZE
) {
679 flush_all_helper(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
680 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
681 async_safe_run_on_cpu(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
682 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
685 TLBFlushPageByMMUIdxData
*d
;
687 /* Allocate a separate data block for each destination cpu. */
688 CPU_FOREACH(dst_cpu
) {
689 if (dst_cpu
!= src_cpu
) {
690 d
= g_new(TLBFlushPageByMMUIdxData
, 1);
693 async_run_on_cpu(dst_cpu
, tlb_flush_page_by_mmuidx_async_2
,
694 RUN_ON_CPU_HOST_PTR(d
));
698 d
= g_new(TLBFlushPageByMMUIdxData
, 1);
701 async_safe_run_on_cpu(src_cpu
, tlb_flush_page_by_mmuidx_async_2
,
702 RUN_ON_CPU_HOST_PTR(d
));
706 void tlb_flush_page_all_cpus_synced(CPUState
*src
, vaddr addr
)
708 tlb_flush_page_by_mmuidx_all_cpus_synced(src
, addr
, ALL_MMUIDX_BITS
);
711 static void tlb_flush_range_locked(CPUArchState
*env
, int midx
,
712 vaddr addr
, vaddr len
,
715 CPUTLBDesc
*d
= &env_tlb(env
)->d
[midx
];
716 CPUTLBDescFast
*f
= &env_tlb(env
)->f
[midx
];
717 vaddr mask
= MAKE_64BIT_MASK(0, bits
);
720 * If @bits is smaller than the tlb size, there may be multiple entries
721 * within the TLB; otherwise all addresses that match under @mask hit
722 * the same TLB entry.
723 * TODO: Perhaps allow bits to be a few bits less than the size.
724 * For now, just flush the entire TLB.
726 * If @len is larger than the tlb size, then it will take longer to
727 * test all of the entries in the TLB than it will to flush it all.
729 if (mask
< f
->mask
|| len
> f
->mask
) {
730 tlb_debug("forcing full flush midx %d ("
731 "%" VADDR_PRIx
"/%" VADDR_PRIx
"+%" VADDR_PRIx
")\n",
732 midx
, addr
, mask
, len
);
733 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
738 * Check if we need to flush due to large pages.
739 * Because large_page_mask contains all 1's from the msb,
740 * we only need to test the end of the range.
742 if (((addr
+ len
- 1) & d
->large_page_mask
) == d
->large_page_addr
) {
743 tlb_debug("forcing full flush midx %d ("
744 "%" VADDR_PRIx
"/%" VADDR_PRIx
")\n",
745 midx
, d
->large_page_addr
, d
->large_page_mask
);
746 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
750 for (vaddr i
= 0; i
< len
; i
+= TARGET_PAGE_SIZE
) {
751 vaddr page
= addr
+ i
;
752 CPUTLBEntry
*entry
= tlb_entry(env
, midx
, page
);
754 if (tlb_flush_entry_mask_locked(entry
, page
, mask
)) {
755 tlb_n_used_entries_dec(env
, midx
);
757 tlb_flush_vtlb_page_mask_locked(env
, midx
, page
, mask
);
768 static void tlb_flush_range_by_mmuidx_async_0(CPUState
*cpu
,
771 CPUArchState
*env
= cpu
->env_ptr
;
774 assert_cpu_is_self(cpu
);
776 tlb_debug("range: %" VADDR_PRIx
"/%u+%" VADDR_PRIx
" mmu_map:0x%x\n",
777 d
.addr
, d
.bits
, d
.len
, d
.idxmap
);
779 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
780 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
781 if ((d
.idxmap
>> mmu_idx
) & 1) {
782 tlb_flush_range_locked(env
, mmu_idx
, d
.addr
, d
.len
, d
.bits
);
785 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
788 * If the length is larger than the jump cache size, then it will take
789 * longer to clear each entry individually than it will to clear it all.
791 if (d
.len
>= (TARGET_PAGE_SIZE
* TB_JMP_CACHE_SIZE
)) {
792 tcg_flush_jmp_cache(cpu
);
797 * Discard jump cache entries for any tb which might potentially
798 * overlap the flushed pages, which includes the previous.
800 d
.addr
-= TARGET_PAGE_SIZE
;
801 for (vaddr i
= 0, n
= d
.len
/ TARGET_PAGE_SIZE
+ 1; i
< n
; i
++) {
802 tb_jmp_cache_clear_page(cpu
, d
.addr
);
803 d
.addr
+= TARGET_PAGE_SIZE
;
807 static void tlb_flush_range_by_mmuidx_async_1(CPUState
*cpu
,
808 run_on_cpu_data data
)
810 TLBFlushRangeData
*d
= data
.host_ptr
;
811 tlb_flush_range_by_mmuidx_async_0(cpu
, *d
);
815 void tlb_flush_range_by_mmuidx(CPUState
*cpu
, vaddr addr
,
816 vaddr len
, uint16_t idxmap
,
822 * If all bits are significant, and len is small,
823 * this devolves to tlb_flush_page.
825 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
826 tlb_flush_page_by_mmuidx(cpu
, addr
, idxmap
);
829 /* If no page bits are significant, this devolves to tlb_flush. */
830 if (bits
< TARGET_PAGE_BITS
) {
831 tlb_flush_by_mmuidx(cpu
, idxmap
);
835 /* This should already be page aligned */
836 d
.addr
= addr
& TARGET_PAGE_MASK
;
841 if (qemu_cpu_is_self(cpu
)) {
842 tlb_flush_range_by_mmuidx_async_0(cpu
, d
);
844 /* Otherwise allocate a structure, freed by the worker. */
845 TLBFlushRangeData
*p
= g_memdup(&d
, sizeof(d
));
846 async_run_on_cpu(cpu
, tlb_flush_range_by_mmuidx_async_1
,
847 RUN_ON_CPU_HOST_PTR(p
));
851 void tlb_flush_page_bits_by_mmuidx(CPUState
*cpu
, vaddr addr
,
852 uint16_t idxmap
, unsigned bits
)
854 tlb_flush_range_by_mmuidx(cpu
, addr
, TARGET_PAGE_SIZE
, idxmap
, bits
);
857 void tlb_flush_range_by_mmuidx_all_cpus(CPUState
*src_cpu
,
858 vaddr addr
, vaddr len
,
859 uint16_t idxmap
, unsigned bits
)
865 * If all bits are significant, and len is small,
866 * this devolves to tlb_flush_page.
868 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
869 tlb_flush_page_by_mmuidx_all_cpus(src_cpu
, addr
, idxmap
);
872 /* If no page bits are significant, this devolves to tlb_flush. */
873 if (bits
< TARGET_PAGE_BITS
) {
874 tlb_flush_by_mmuidx_all_cpus(src_cpu
, idxmap
);
878 /* This should already be page aligned */
879 d
.addr
= addr
& TARGET_PAGE_MASK
;
884 /* Allocate a separate data block for each destination cpu. */
885 CPU_FOREACH(dst_cpu
) {
886 if (dst_cpu
!= src_cpu
) {
887 TLBFlushRangeData
*p
= g_memdup(&d
, sizeof(d
));
888 async_run_on_cpu(dst_cpu
,
889 tlb_flush_range_by_mmuidx_async_1
,
890 RUN_ON_CPU_HOST_PTR(p
));
894 tlb_flush_range_by_mmuidx_async_0(src_cpu
, d
);
897 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState
*src_cpu
,
898 vaddr addr
, uint16_t idxmap
,
901 tlb_flush_range_by_mmuidx_all_cpus(src_cpu
, addr
, TARGET_PAGE_SIZE
,
905 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
911 TLBFlushRangeData d
, *p
;
915 * If all bits are significant, and len is small,
916 * this devolves to tlb_flush_page.
918 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
919 tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu
, addr
, idxmap
);
922 /* If no page bits are significant, this devolves to tlb_flush. */
923 if (bits
< TARGET_PAGE_BITS
) {
924 tlb_flush_by_mmuidx_all_cpus_synced(src_cpu
, idxmap
);
928 /* This should already be page aligned */
929 d
.addr
= addr
& TARGET_PAGE_MASK
;
934 /* Allocate a separate data block for each destination cpu. */
935 CPU_FOREACH(dst_cpu
) {
936 if (dst_cpu
!= src_cpu
) {
937 p
= g_memdup(&d
, sizeof(d
));
938 async_run_on_cpu(dst_cpu
, tlb_flush_range_by_mmuidx_async_1
,
939 RUN_ON_CPU_HOST_PTR(p
));
943 p
= g_memdup(&d
, sizeof(d
));
944 async_safe_run_on_cpu(src_cpu
, tlb_flush_range_by_mmuidx_async_1
,
945 RUN_ON_CPU_HOST_PTR(p
));
948 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
953 tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu
, addr
, TARGET_PAGE_SIZE
,
957 /* update the TLBs so that writes to code in the virtual page 'addr'
959 void tlb_protect_code(ram_addr_t ram_addr
)
961 cpu_physical_memory_test_and_clear_dirty(ram_addr
& TARGET_PAGE_MASK
,
966 /* update the TLB so that writes in physical page 'phys_addr' are no longer
967 tested for self modifying code */
968 void tlb_unprotect_code(ram_addr_t ram_addr
)
970 cpu_physical_memory_set_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
);
975 * Dirty write flag handling
977 * When the TCG code writes to a location it looks up the address in
978 * the TLB and uses that data to compute the final address. If any of
979 * the lower bits of the address are set then the slow path is forced.
980 * There are a number of reasons to do this but for normal RAM the
981 * most usual is detecting writes to code regions which may invalidate
984 * Other vCPUs might be reading their TLBs during guest execution, so we update
985 * te->addr_write with qatomic_set. We don't need to worry about this for
986 * oversized guests as MTTCG is disabled for them.
988 * Called with tlb_c.lock held.
990 static void tlb_reset_dirty_range_locked(CPUTLBEntry
*tlb_entry
,
991 uintptr_t start
, uintptr_t length
)
993 uintptr_t addr
= tlb_entry
->addr_write
;
995 if ((addr
& (TLB_INVALID_MASK
| TLB_MMIO
|
996 TLB_DISCARD_WRITE
| TLB_NOTDIRTY
)) == 0) {
997 addr
&= TARGET_PAGE_MASK
;
998 addr
+= tlb_entry
->addend
;
999 if ((addr
- start
) < length
) {
1000 #if TARGET_LONG_BITS == 32
1001 uint32_t *ptr_write
= (uint32_t *)&tlb_entry
->addr_write
;
1002 ptr_write
+= HOST_BIG_ENDIAN
;
1003 qatomic_set(ptr_write
, *ptr_write
| TLB_NOTDIRTY
);
1004 #elif TCG_OVERSIZED_GUEST
1005 tlb_entry
->addr_write
|= TLB_NOTDIRTY
;
1007 qatomic_set(&tlb_entry
->addr_write
,
1008 tlb_entry
->addr_write
| TLB_NOTDIRTY
);
1015 * Called with tlb_c.lock held.
1016 * Called only from the vCPU context, i.e. the TLB's owner thread.
1018 static inline void copy_tlb_helper_locked(CPUTLBEntry
*d
, const CPUTLBEntry
*s
)
1023 /* This is a cross vCPU call (i.e. another vCPU resetting the flags of
1025 * We must take tlb_c.lock to avoid racing with another vCPU update. The only
1026 * thing actually updated is the target TLB entry ->addr_write flags.
1028 void tlb_reset_dirty(CPUState
*cpu
, ram_addr_t start1
, ram_addr_t length
)
1035 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1036 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1038 unsigned int n
= tlb_n_entries(&env_tlb(env
)->f
[mmu_idx
]);
1040 for (i
= 0; i
< n
; i
++) {
1041 tlb_reset_dirty_range_locked(&env_tlb(env
)->f
[mmu_idx
].table
[i
],
1045 for (i
= 0; i
< CPU_VTLB_SIZE
; i
++) {
1046 tlb_reset_dirty_range_locked(&env_tlb(env
)->d
[mmu_idx
].vtable
[i
],
1050 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1053 /* Called with tlb_c.lock held */
1054 static inline void tlb_set_dirty1_locked(CPUTLBEntry
*tlb_entry
,
1057 if (tlb_entry
->addr_write
== (addr
| TLB_NOTDIRTY
)) {
1058 tlb_entry
->addr_write
= addr
;
1062 /* update the TLB corresponding to virtual page vaddr
1063 so that it is no longer dirty */
1064 void tlb_set_dirty(CPUState
*cpu
, vaddr addr
)
1066 CPUArchState
*env
= cpu
->env_ptr
;
1069 assert_cpu_is_self(cpu
);
1071 addr
&= TARGET_PAGE_MASK
;
1072 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1073 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1074 tlb_set_dirty1_locked(tlb_entry(env
, mmu_idx
, addr
), addr
);
1077 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1079 for (k
= 0; k
< CPU_VTLB_SIZE
; k
++) {
1080 tlb_set_dirty1_locked(&env_tlb(env
)->d
[mmu_idx
].vtable
[k
], addr
);
1083 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1086 /* Our TLB does not support large pages, so remember the area covered by
1087 large pages and trigger a full TLB flush if these are invalidated. */
1088 static void tlb_add_large_page(CPUArchState
*env
, int mmu_idx
,
1089 vaddr addr
, uint64_t size
)
1091 vaddr lp_addr
= env_tlb(env
)->d
[mmu_idx
].large_page_addr
;
1092 vaddr lp_mask
= ~(size
- 1);
1094 if (lp_addr
== (vaddr
)-1) {
1095 /* No previous large page. */
1098 /* Extend the existing region to include the new page.
1099 This is a compromise between unnecessary flushes and
1100 the cost of maintaining a full variable size TLB. */
1101 lp_mask
&= env_tlb(env
)->d
[mmu_idx
].large_page_mask
;
1102 while (((lp_addr
^ addr
) & lp_mask
) != 0) {
1106 env_tlb(env
)->d
[mmu_idx
].large_page_addr
= lp_addr
& lp_mask
;
1107 env_tlb(env
)->d
[mmu_idx
].large_page_mask
= lp_mask
;
1111 * Add a new TLB entry. At most one entry for a given virtual address
1112 * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
1113 * supplied size is only used by tlb_flush_page.
1115 * Called from TCG-generated code, which is under an RCU read-side
1118 void tlb_set_page_full(CPUState
*cpu
, int mmu_idx
,
1119 vaddr addr
, CPUTLBEntryFull
*full
)
1121 CPUArchState
*env
= cpu
->env_ptr
;
1122 CPUTLB
*tlb
= env_tlb(env
);
1123 CPUTLBDesc
*desc
= &tlb
->d
[mmu_idx
];
1124 MemoryRegionSection
*section
;
1127 vaddr write_address
;
1129 CPUTLBEntry
*te
, tn
;
1130 hwaddr iotlb
, xlat
, sz
, paddr_page
;
1132 int asidx
, wp_flags
, prot
;
1133 bool is_ram
, is_romd
;
1135 assert_cpu_is_self(cpu
);
1137 if (full
->lg_page_size
<= TARGET_PAGE_BITS
) {
1138 sz
= TARGET_PAGE_SIZE
;
1140 sz
= (hwaddr
)1 << full
->lg_page_size
;
1141 tlb_add_large_page(env
, mmu_idx
, addr
, sz
);
1143 addr_page
= addr
& TARGET_PAGE_MASK
;
1144 paddr_page
= full
->phys_addr
& TARGET_PAGE_MASK
;
1147 asidx
= cpu_asidx_from_attrs(cpu
, full
->attrs
);
1148 section
= address_space_translate_for_iotlb(cpu
, asidx
, paddr_page
,
1149 &xlat
, &sz
, full
->attrs
, &prot
);
1150 assert(sz
>= TARGET_PAGE_SIZE
);
1152 tlb_debug("vaddr=%" VADDR_PRIx
" paddr=0x" HWADDR_FMT_plx
1153 " prot=%x idx=%d\n",
1154 addr
, full
->phys_addr
, prot
, mmu_idx
);
1156 address
= addr_page
;
1157 if (full
->lg_page_size
< TARGET_PAGE_BITS
) {
1158 /* Repeat the MMU check and TLB fill on every access. */
1159 address
|= TLB_INVALID_MASK
;
1161 if (full
->attrs
.byte_swap
) {
1162 address
|= TLB_BSWAP
;
1165 is_ram
= memory_region_is_ram(section
->mr
);
1166 is_romd
= memory_region_is_romd(section
->mr
);
1168 if (is_ram
|| is_romd
) {
1169 /* RAM and ROMD both have associated host memory. */
1170 addend
= (uintptr_t)memory_region_get_ram_ptr(section
->mr
) + xlat
;
1172 /* I/O does not; force the host address to NULL. */
1176 write_address
= address
;
1178 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1180 * Computing is_clean is expensive; avoid all that unless
1181 * the page is actually writable.
1183 if (prot
& PAGE_WRITE
) {
1184 if (section
->readonly
) {
1185 write_address
|= TLB_DISCARD_WRITE
;
1186 } else if (cpu_physical_memory_is_clean(iotlb
)) {
1187 write_address
|= TLB_NOTDIRTY
;
1192 iotlb
= memory_region_section_get_iotlb(cpu
, section
) + xlat
;
1194 * Writes to romd devices must go through MMIO to enable write.
1195 * Reads to romd devices go through the ram_ptr found above,
1196 * but of course reads to I/O must go through MMIO.
1198 write_address
|= TLB_MMIO
;
1200 address
= write_address
;
1204 wp_flags
= cpu_watchpoint_address_matches(cpu
, addr_page
,
1207 index
= tlb_index(env
, mmu_idx
, addr_page
);
1208 te
= tlb_entry(env
, mmu_idx
, addr_page
);
1211 * Hold the TLB lock for the rest of the function. We could acquire/release
1212 * the lock several times in the function, but it is faster to amortize the
1213 * acquisition cost by acquiring it just once. Note that this leads to
1214 * a longer critical section, but this is not a concern since the TLB lock
1215 * is unlikely to be contended.
1217 qemu_spin_lock(&tlb
->c
.lock
);
1219 /* Note that the tlb is no longer clean. */
1220 tlb
->c
.dirty
|= 1 << mmu_idx
;
1222 /* Make sure there's no cached translation for the new page. */
1223 tlb_flush_vtlb_page_locked(env
, mmu_idx
, addr_page
);
1226 * Only evict the old entry to the victim tlb if it's for a
1227 * different page; otherwise just overwrite the stale data.
1229 if (!tlb_hit_page_anyprot(te
, addr_page
) && !tlb_entry_is_empty(te
)) {
1230 unsigned vidx
= desc
->vindex
++ % CPU_VTLB_SIZE
;
1231 CPUTLBEntry
*tv
= &desc
->vtable
[vidx
];
1233 /* Evict the old entry into the victim tlb. */
1234 copy_tlb_helper_locked(tv
, te
);
1235 desc
->vfulltlb
[vidx
] = desc
->fulltlb
[index
];
1236 tlb_n_used_entries_dec(env
, mmu_idx
);
1239 /* refill the tlb */
1241 * At this point iotlb contains a physical section number in the lower
1242 * TARGET_PAGE_BITS, and either
1243 * + the ram_addr_t of the page base of the target RAM (RAM)
1244 * + the offset within section->mr of the page base (I/O, ROMD)
1245 * We subtract the vaddr_page (which is page aligned and thus won't
1246 * disturb the low bits) to give an offset which can be added to the
1247 * (non-page-aligned) vaddr of the eventual memory access to get
1248 * the MemoryRegion offset for the access. Note that the vaddr we
1249 * subtract here is that of the page base, and not the same as the
1250 * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
1252 desc
->fulltlb
[index
] = *full
;
1253 desc
->fulltlb
[index
].xlat_section
= iotlb
- addr_page
;
1254 desc
->fulltlb
[index
].phys_addr
= paddr_page
;
1256 /* Now calculate the new entry */
1257 tn
.addend
= addend
- addr_page
;
1258 if (prot
& PAGE_READ
) {
1259 tn
.addr_read
= address
;
1260 if (wp_flags
& BP_MEM_READ
) {
1261 tn
.addr_read
|= TLB_WATCHPOINT
;
1267 if (prot
& PAGE_EXEC
) {
1268 tn
.addr_code
= address
;
1274 if (prot
& PAGE_WRITE
) {
1275 tn
.addr_write
= write_address
;
1276 if (prot
& PAGE_WRITE_INV
) {
1277 tn
.addr_write
|= TLB_INVALID_MASK
;
1279 if (wp_flags
& BP_MEM_WRITE
) {
1280 tn
.addr_write
|= TLB_WATCHPOINT
;
1284 copy_tlb_helper_locked(te
, &tn
);
1285 tlb_n_used_entries_inc(env
, mmu_idx
);
1286 qemu_spin_unlock(&tlb
->c
.lock
);
1289 void tlb_set_page_with_attrs(CPUState
*cpu
, vaddr addr
,
1290 hwaddr paddr
, MemTxAttrs attrs
, int prot
,
1291 int mmu_idx
, uint64_t size
)
1293 CPUTLBEntryFull full
= {
1297 .lg_page_size
= ctz64(size
)
1300 assert(is_power_of_2(size
));
1301 tlb_set_page_full(cpu
, mmu_idx
, addr
, &full
);
1304 void tlb_set_page(CPUState
*cpu
, vaddr addr
,
1305 hwaddr paddr
, int prot
,
1306 int mmu_idx
, uint64_t size
)
1308 tlb_set_page_with_attrs(cpu
, addr
, paddr
, MEMTXATTRS_UNSPECIFIED
,
1309 prot
, mmu_idx
, size
);
1313 * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
1314 * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
1315 * be discarded and looked up again (e.g. via tlb_entry()).
1317 static void tlb_fill(CPUState
*cpu
, vaddr addr
, int size
,
1318 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
1323 * This is not a probe, so only valid return is success; failure
1324 * should result in exception + longjmp to the cpu loop.
1326 ok
= cpu
->cc
->tcg_ops
->tlb_fill(cpu
, addr
, size
,
1327 access_type
, mmu_idx
, false, retaddr
);
1331 static inline void cpu_unaligned_access(CPUState
*cpu
, vaddr addr
,
1332 MMUAccessType access_type
,
1333 int mmu_idx
, uintptr_t retaddr
)
1335 cpu
->cc
->tcg_ops
->do_unaligned_access(cpu
, addr
, access_type
,
1339 static inline void cpu_transaction_failed(CPUState
*cpu
, hwaddr physaddr
,
1340 vaddr addr
, unsigned size
,
1341 MMUAccessType access_type
,
1342 int mmu_idx
, MemTxAttrs attrs
,
1343 MemTxResult response
,
1346 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
1348 if (!cpu
->ignore_memory_transaction_failures
&&
1349 cc
->tcg_ops
->do_transaction_failed
) {
1350 cc
->tcg_ops
->do_transaction_failed(cpu
, physaddr
, addr
, size
,
1351 access_type
, mmu_idx
, attrs
,
1356 static uint64_t io_readx(CPUArchState
*env
, CPUTLBEntryFull
*full
,
1357 int mmu_idx
, vaddr addr
, uintptr_t retaddr
,
1358 MMUAccessType access_type
, MemOp op
)
1360 CPUState
*cpu
= env_cpu(env
);
1362 MemoryRegionSection
*section
;
1367 section
= iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1369 mr_offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1370 cpu
->mem_io_pc
= retaddr
;
1371 if (!cpu
->can_do_io
) {
1372 cpu_io_recompile(cpu
, retaddr
);
1376 QEMU_IOTHREAD_LOCK_GUARD();
1377 r
= memory_region_dispatch_read(mr
, mr_offset
, &val
, op
, full
->attrs
);
1380 if (r
!= MEMTX_OK
) {
1381 hwaddr physaddr
= mr_offset
+
1382 section
->offset_within_address_space
-
1383 section
->offset_within_region
;
1385 cpu_transaction_failed(cpu
, physaddr
, addr
, memop_size(op
), access_type
,
1386 mmu_idx
, full
->attrs
, r
, retaddr
);
1392 * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin.
1393 * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
1394 * because of the side effect of io_writex changing memory layout.
1396 static void save_iotlb_data(CPUState
*cs
, MemoryRegionSection
*section
,
1399 #ifdef CONFIG_PLUGIN
1400 SavedIOTLB
*saved
= &cs
->saved_iotlb
;
1401 saved
->section
= section
;
1402 saved
->mr_offset
= mr_offset
;
1406 static void io_writex(CPUArchState
*env
, CPUTLBEntryFull
*full
,
1407 int mmu_idx
, uint64_t val
, vaddr addr
,
1408 uintptr_t retaddr
, MemOp op
)
1410 CPUState
*cpu
= env_cpu(env
);
1412 MemoryRegionSection
*section
;
1416 section
= iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1418 mr_offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1419 if (!cpu
->can_do_io
) {
1420 cpu_io_recompile(cpu
, retaddr
);
1422 cpu
->mem_io_pc
= retaddr
;
1425 * The memory_region_dispatch may trigger a flush/resize
1426 * so for plugins we save the iotlb_data just in case.
1428 save_iotlb_data(cpu
, section
, mr_offset
);
1431 QEMU_IOTHREAD_LOCK_GUARD();
1432 r
= memory_region_dispatch_write(mr
, mr_offset
, val
, op
, full
->attrs
);
1435 if (r
!= MEMTX_OK
) {
1436 hwaddr physaddr
= mr_offset
+
1437 section
->offset_within_address_space
-
1438 section
->offset_within_region
;
1440 cpu_transaction_failed(cpu
, physaddr
, addr
, memop_size(op
),
1441 MMU_DATA_STORE
, mmu_idx
, full
->attrs
, r
,
1446 /* Return true if ADDR is present in the victim tlb, and has been copied
1447 back to the main tlb. */
1448 static bool victim_tlb_hit(CPUArchState
*env
, size_t mmu_idx
, size_t index
,
1449 MMUAccessType access_type
, vaddr page
)
1453 assert_cpu_is_self(env_cpu(env
));
1454 for (vidx
= 0; vidx
< CPU_VTLB_SIZE
; ++vidx
) {
1455 CPUTLBEntry
*vtlb
= &env_tlb(env
)->d
[mmu_idx
].vtable
[vidx
];
1456 uint64_t cmp
= tlb_read_idx(vtlb
, access_type
);
1459 /* Found entry in victim tlb, swap tlb and iotlb. */
1460 CPUTLBEntry tmptlb
, *tlb
= &env_tlb(env
)->f
[mmu_idx
].table
[index
];
1462 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1463 copy_tlb_helper_locked(&tmptlb
, tlb
);
1464 copy_tlb_helper_locked(tlb
, vtlb
);
1465 copy_tlb_helper_locked(vtlb
, &tmptlb
);
1466 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1468 CPUTLBEntryFull
*f1
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1469 CPUTLBEntryFull
*f2
= &env_tlb(env
)->d
[mmu_idx
].vfulltlb
[vidx
];
1470 CPUTLBEntryFull tmpf
;
1471 tmpf
= *f1
; *f1
= *f2
; *f2
= tmpf
;
1478 static void notdirty_write(CPUState
*cpu
, vaddr mem_vaddr
, unsigned size
,
1479 CPUTLBEntryFull
*full
, uintptr_t retaddr
)
1481 ram_addr_t ram_addr
= mem_vaddr
+ full
->xlat_section
;
1483 trace_memory_notdirty_write_access(mem_vaddr
, ram_addr
, size
);
1485 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
1486 tb_invalidate_phys_range_fast(ram_addr
, size
, retaddr
);
1490 * Set both VGA and migration bits for simplicity and to remove
1491 * the notdirty callback faster.
1493 cpu_physical_memory_set_dirty_range(ram_addr
, size
, DIRTY_CLIENTS_NOCODE
);
1495 /* We remove the notdirty callback only if the code has been flushed. */
1496 if (!cpu_physical_memory_is_clean(ram_addr
)) {
1497 trace_memory_notdirty_set_dirty(mem_vaddr
);
1498 tlb_set_dirty(cpu
, mem_vaddr
);
1502 static int probe_access_internal(CPUArchState
*env
, target_ulong addr
,
1503 int fault_size
, MMUAccessType access_type
,
1504 int mmu_idx
, bool nonfault
,
1505 void **phost
, CPUTLBEntryFull
**pfull
,
1508 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1509 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
1510 uint64_t tlb_addr
= tlb_read_idx(entry
, access_type
);
1511 target_ulong page_addr
= addr
& TARGET_PAGE_MASK
;
1512 int flags
= TLB_FLAGS_MASK
;
1514 if (!tlb_hit_page(tlb_addr
, page_addr
)) {
1515 if (!victim_tlb_hit(env
, mmu_idx
, index
, access_type
, page_addr
)) {
1516 CPUState
*cs
= env_cpu(env
);
1518 if (!cs
->cc
->tcg_ops
->tlb_fill(cs
, addr
, fault_size
, access_type
,
1519 mmu_idx
, nonfault
, retaddr
)) {
1520 /* Non-faulting page table read failed. */
1523 return TLB_INVALID_MASK
;
1526 /* TLB resize via tlb_fill may have moved the entry. */
1527 index
= tlb_index(env
, mmu_idx
, addr
);
1528 entry
= tlb_entry(env
, mmu_idx
, addr
);
1531 * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
1532 * to force the next access through tlb_fill. We've just
1533 * called tlb_fill, so we know that this entry *is* valid.
1535 flags
&= ~TLB_INVALID_MASK
;
1537 tlb_addr
= tlb_read_idx(entry
, access_type
);
1541 *pfull
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1543 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
1544 if (unlikely(flags
& ~(TLB_WATCHPOINT
| TLB_NOTDIRTY
))) {
1549 /* Everything else is RAM. */
1550 *phost
= (void *)((uintptr_t)addr
+ entry
->addend
);
1554 int probe_access_full(CPUArchState
*env
, target_ulong addr
, int size
,
1555 MMUAccessType access_type
, int mmu_idx
,
1556 bool nonfault
, void **phost
, CPUTLBEntryFull
**pfull
,
1559 int flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1560 nonfault
, phost
, pfull
, retaddr
);
1562 /* Handle clean RAM pages. */
1563 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1564 notdirty_write(env_cpu(env
), addr
, 1, *pfull
, retaddr
);
1565 flags
&= ~TLB_NOTDIRTY
;
1571 int probe_access_flags(CPUArchState
*env
, target_ulong addr
, int size
,
1572 MMUAccessType access_type
, int mmu_idx
,
1573 bool nonfault
, void **phost
, uintptr_t retaddr
)
1575 CPUTLBEntryFull
*full
;
1578 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
1580 flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1581 nonfault
, phost
, &full
, retaddr
);
1583 /* Handle clean RAM pages. */
1584 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1585 notdirty_write(env_cpu(env
), addr
, 1, full
, retaddr
);
1586 flags
&= ~TLB_NOTDIRTY
;
1592 void *probe_access(CPUArchState
*env
, target_ulong addr
, int size
,
1593 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
1595 CPUTLBEntryFull
*full
;
1599 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
1601 flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1602 false, &host
, &full
, retaddr
);
1604 /* Per the interface, size == 0 merely faults the access. */
1609 if (unlikely(flags
& (TLB_NOTDIRTY
| TLB_WATCHPOINT
))) {
1610 /* Handle watchpoints. */
1611 if (flags
& TLB_WATCHPOINT
) {
1612 int wp_access
= (access_type
== MMU_DATA_STORE
1613 ? BP_MEM_WRITE
: BP_MEM_READ
);
1614 cpu_check_watchpoint(env_cpu(env
), addr
, size
,
1615 full
->attrs
, wp_access
, retaddr
);
1618 /* Handle clean RAM pages. */
1619 if (flags
& TLB_NOTDIRTY
) {
1620 notdirty_write(env_cpu(env
), addr
, 1, full
, retaddr
);
1627 void *tlb_vaddr_to_host(CPUArchState
*env
, abi_ptr addr
,
1628 MMUAccessType access_type
, int mmu_idx
)
1630 CPUTLBEntryFull
*full
;
1634 flags
= probe_access_internal(env
, addr
, 0, access_type
,
1635 mmu_idx
, true, &host
, &full
, 0);
1637 /* No combination of flags are expected by the caller. */
1638 return flags
? NULL
: host
;
1642 * Return a ram_addr_t for the virtual address for execution.
1644 * Return -1 if we can't translate and execute from an entire page
1645 * of RAM. This will force us to execute by loading and translating
1646 * one insn at a time, without caching.
1648 * NOTE: This function will trigger an exception if the page is
1651 tb_page_addr_t
get_page_addr_code_hostp(CPUArchState
*env
, target_ulong addr
,
1654 CPUTLBEntryFull
*full
;
1657 (void)probe_access_internal(env
, addr
, 1, MMU_INST_FETCH
,
1658 cpu_mmu_index(env
, true), false, &p
, &full
, 0);
1663 if (full
->lg_page_size
< TARGET_PAGE_BITS
) {
1670 return qemu_ram_addr_from_host_nofail(p
);
1673 /* Load/store with atomicity primitives. */
1674 #include "ldst_atomicity.c.inc"
1676 #ifdef CONFIG_PLUGIN
1678 * Perform a TLB lookup and populate the qemu_plugin_hwaddr structure.
1679 * This should be a hot path as we will have just looked this path up
1680 * in the softmmu lookup code (or helper). We don't handle re-fills or
1681 * checking the victim table. This is purely informational.
1683 * This almost never fails as the memory access being instrumented
1684 * should have just filled the TLB. The one corner case is io_writex
1685 * which can cause TLB flushes and potential resizing of the TLBs
1686 * losing the information we need. In those cases we need to recover
1687 * data from a copy of the CPUTLBEntryFull. As long as this always occurs
1688 * from the same thread (which a mem callback will be) this is safe.
1691 bool tlb_plugin_lookup(CPUState
*cpu
, vaddr addr
, int mmu_idx
,
1692 bool is_store
, struct qemu_plugin_hwaddr
*data
)
1694 CPUArchState
*env
= cpu
->env_ptr
;
1695 CPUTLBEntry
*tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1696 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1697 uint64_t tlb_addr
= is_store
? tlb_addr_write(tlbe
) : tlbe
->addr_read
;
1699 if (likely(tlb_hit(tlb_addr
, addr
))) {
1700 /* We must have an iotlb entry for MMIO */
1701 if (tlb_addr
& TLB_MMIO
) {
1702 CPUTLBEntryFull
*full
;
1703 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1705 data
->v
.io
.section
=
1706 iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1707 data
->v
.io
.offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1709 data
->is_io
= false;
1710 data
->v
.ram
.hostaddr
= (void *)((uintptr_t)addr
+ tlbe
->addend
);
1714 SavedIOTLB
*saved
= &cpu
->saved_iotlb
;
1716 data
->v
.io
.section
= saved
->section
;
1717 data
->v
.io
.offset
= saved
->mr_offset
;
1725 * Probe for a load/store operation.
1726 * Return the host address and into @flags.
1729 typedef struct MMULookupPageData
{
1730 CPUTLBEntryFull
*full
;
1735 } MMULookupPageData
;
1737 typedef struct MMULookupLocals
{
1738 MMULookupPageData page
[2];
1744 * mmu_lookup1: translate one page
1746 * @data: lookup parameters
1747 * @mmu_idx: virtual address context
1748 * @access_type: load/store/code
1749 * @ra: return address into tcg generated code, or 0
1751 * Resolve the translation for the one page at @data.addr, filling in
1752 * the rest of @data with the results. If the translation fails,
1753 * tlb_fill will longjmp out. Return true if the softmmu tlb for
1754 * @mmu_idx may have resized.
1756 static bool mmu_lookup1(CPUArchState
*env
, MMULookupPageData
*data
,
1757 int mmu_idx
, MMUAccessType access_type
, uintptr_t ra
)
1759 vaddr addr
= data
->addr
;
1760 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1761 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
1762 uint64_t tlb_addr
= tlb_read_idx(entry
, access_type
);
1763 bool maybe_resized
= false;
1765 /* If the TLB entry is for a different page, reload and try again. */
1766 if (!tlb_hit(tlb_addr
, addr
)) {
1767 if (!victim_tlb_hit(env
, mmu_idx
, index
, access_type
,
1768 addr
& TARGET_PAGE_MASK
)) {
1769 tlb_fill(env_cpu(env
), addr
, data
->size
, access_type
, mmu_idx
, ra
);
1770 maybe_resized
= true;
1771 index
= tlb_index(env
, mmu_idx
, addr
);
1772 entry
= tlb_entry(env
, mmu_idx
, addr
);
1774 tlb_addr
= tlb_read_idx(entry
, access_type
) & ~TLB_INVALID_MASK
;
1777 data
->flags
= tlb_addr
& TLB_FLAGS_MASK
;
1778 data
->full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1779 /* Compute haddr speculatively; depending on flags it might be invalid. */
1780 data
->haddr
= (void *)((uintptr_t)addr
+ entry
->addend
);
1782 return maybe_resized
;
1786 * mmu_watch_or_dirty
1788 * @data: lookup parameters
1789 * @access_type: load/store/code
1790 * @ra: return address into tcg generated code, or 0
1792 * Trigger watchpoints for @data.addr:@data.size;
1793 * record writes to protected clean pages.
1795 static void mmu_watch_or_dirty(CPUArchState
*env
, MMULookupPageData
*data
,
1796 MMUAccessType access_type
, uintptr_t ra
)
1798 CPUTLBEntryFull
*full
= data
->full
;
1799 vaddr addr
= data
->addr
;
1800 int flags
= data
->flags
;
1801 int size
= data
->size
;
1803 /* On watchpoint hit, this will longjmp out. */
1804 if (flags
& TLB_WATCHPOINT
) {
1805 int wp
= access_type
== MMU_DATA_STORE
? BP_MEM_WRITE
: BP_MEM_READ
;
1806 cpu_check_watchpoint(env_cpu(env
), addr
, size
, full
->attrs
, wp
, ra
);
1807 flags
&= ~TLB_WATCHPOINT
;
1810 /* Note that notdirty is only set for writes. */
1811 if (flags
& TLB_NOTDIRTY
) {
1812 notdirty_write(env_cpu(env
), addr
, size
, full
, ra
);
1813 flags
&= ~TLB_NOTDIRTY
;
1815 data
->flags
= flags
;
1819 * mmu_lookup: translate page(s)
1821 * @addr: virtual address
1822 * @oi: combined mmu_idx and MemOp
1823 * @ra: return address into tcg generated code, or 0
1824 * @access_type: load/store/code
1827 * Resolve the translation for the page(s) beginning at @addr, for MemOp.size
1828 * bytes. Return true if the lookup crosses a page boundary.
1830 static bool mmu_lookup(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
1831 uintptr_t ra
, MMUAccessType type
, MMULookupLocals
*l
)
1837 l
->memop
= get_memop(oi
);
1838 l
->mmu_idx
= get_mmuidx(oi
);
1840 tcg_debug_assert(l
->mmu_idx
< NB_MMU_MODES
);
1842 /* Handle CPU specific unaligned behaviour */
1843 a_bits
= get_alignment_bits(l
->memop
);
1844 if (addr
& ((1 << a_bits
) - 1)) {
1845 cpu_unaligned_access(env_cpu(env
), addr
, type
, l
->mmu_idx
, ra
);
1848 l
->page
[0].addr
= addr
;
1849 l
->page
[0].size
= memop_size(l
->memop
);
1850 l
->page
[1].addr
= (addr
+ l
->page
[0].size
- 1) & TARGET_PAGE_MASK
;
1851 l
->page
[1].size
= 0;
1852 crosspage
= (addr
^ l
->page
[1].addr
) & TARGET_PAGE_MASK
;
1854 if (likely(!crosspage
)) {
1855 mmu_lookup1(env
, &l
->page
[0], l
->mmu_idx
, type
, ra
);
1857 flags
= l
->page
[0].flags
;
1858 if (unlikely(flags
& (TLB_WATCHPOINT
| TLB_NOTDIRTY
))) {
1859 mmu_watch_or_dirty(env
, &l
->page
[0], type
, ra
);
1861 if (unlikely(flags
& TLB_BSWAP
)) {
1862 l
->memop
^= MO_BSWAP
;
1865 /* Finish compute of page crossing. */
1866 int size0
= l
->page
[1].addr
- addr
;
1867 l
->page
[1].size
= l
->page
[0].size
- size0
;
1868 l
->page
[0].size
= size0
;
1871 * Lookup both pages, recognizing exceptions from either. If the
1872 * second lookup potentially resized, refresh first CPUTLBEntryFull.
1874 mmu_lookup1(env
, &l
->page
[0], l
->mmu_idx
, type
, ra
);
1875 if (mmu_lookup1(env
, &l
->page
[1], l
->mmu_idx
, type
, ra
)) {
1876 uintptr_t index
= tlb_index(env
, l
->mmu_idx
, addr
);
1877 l
->page
[0].full
= &env_tlb(env
)->d
[l
->mmu_idx
].fulltlb
[index
];
1880 flags
= l
->page
[0].flags
| l
->page
[1].flags
;
1881 if (unlikely(flags
& (TLB_WATCHPOINT
| TLB_NOTDIRTY
))) {
1882 mmu_watch_or_dirty(env
, &l
->page
[0], type
, ra
);
1883 mmu_watch_or_dirty(env
, &l
->page
[1], type
, ra
);
1887 * Since target/sparc is the only user of TLB_BSWAP, and all
1888 * Sparc accesses are aligned, any treatment across two pages
1889 * would be arbitrary. Refuse it until there's a use.
1891 tcg_debug_assert((flags
& TLB_BSWAP
) == 0);
1898 * Probe for an atomic operation. Do not allow unaligned operations,
1899 * or io operations to proceed. Return the host address.
1901 static void *atomic_mmu_lookup(CPUArchState
*env
, target_ulong addr
,
1902 MemOpIdx oi
, int size
, uintptr_t retaddr
)
1904 uintptr_t mmu_idx
= get_mmuidx(oi
);
1905 MemOp mop
= get_memop(oi
);
1906 int a_bits
= get_alignment_bits(mop
);
1909 target_ulong tlb_addr
;
1911 CPUTLBEntryFull
*full
;
1913 tcg_debug_assert(mmu_idx
< NB_MMU_MODES
);
1915 /* Adjust the given return address. */
1916 retaddr
-= GETPC_ADJ
;
1918 /* Enforce guest required alignment. */
1919 if (unlikely(a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)))) {
1920 /* ??? Maybe indicate atomic op to cpu_unaligned_access */
1921 cpu_unaligned_access(env_cpu(env
), addr
, MMU_DATA_STORE
,
1925 /* Enforce qemu required alignment. */
1926 if (unlikely(addr
& (size
- 1))) {
1927 /* We get here if guest alignment was not requested,
1928 or was not enforced by cpu_unaligned_access above.
1929 We might widen the access and emulate, but for now
1930 mark an exception and exit the cpu loop. */
1931 goto stop_the_world
;
1934 index
= tlb_index(env
, mmu_idx
, addr
);
1935 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1937 /* Check TLB entry and enforce page permissions. */
1938 tlb_addr
= tlb_addr_write(tlbe
);
1939 if (!tlb_hit(tlb_addr
, addr
)) {
1940 if (!victim_tlb_hit(env
, mmu_idx
, index
, MMU_DATA_STORE
,
1941 addr
& TARGET_PAGE_MASK
)) {
1942 tlb_fill(env_cpu(env
), addr
, size
,
1943 MMU_DATA_STORE
, mmu_idx
, retaddr
);
1944 index
= tlb_index(env
, mmu_idx
, addr
);
1945 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1947 tlb_addr
= tlb_addr_write(tlbe
) & ~TLB_INVALID_MASK
;
1951 * Let the guest notice RMW on a write-only page.
1952 * We have just verified that the page is writable.
1953 * Subpage lookups may have left TLB_INVALID_MASK set,
1954 * but addr_read will only be -1 if PAGE_READ was unset.
1956 if (unlikely(tlbe
->addr_read
== -1)) {
1957 tlb_fill(env_cpu(env
), addr
, size
, MMU_DATA_LOAD
, mmu_idx
, retaddr
);
1959 * Since we don't support reads and writes to different
1960 * addresses, and we do have the proper page loaded for
1961 * write, this shouldn't ever return. But just in case,
1962 * handle via stop-the-world.
1964 goto stop_the_world
;
1966 /* Collect TLB_WATCHPOINT for read. */
1967 tlb_addr
|= tlbe
->addr_read
;
1969 /* Notice an IO access or a needs-MMU-lookup access */
1970 if (unlikely(tlb_addr
& (TLB_MMIO
| TLB_DISCARD_WRITE
))) {
1971 /* There's really nothing that can be done to
1972 support this apart from stop-the-world. */
1973 goto stop_the_world
;
1976 hostaddr
= (void *)((uintptr_t)addr
+ tlbe
->addend
);
1977 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1979 if (unlikely(tlb_addr
& TLB_NOTDIRTY
)) {
1980 notdirty_write(env_cpu(env
), addr
, size
, full
, retaddr
);
1983 if (unlikely(tlb_addr
& TLB_WATCHPOINT
)) {
1984 cpu_check_watchpoint(env_cpu(env
), addr
, size
, full
->attrs
,
1985 BP_MEM_READ
| BP_MEM_WRITE
, retaddr
);
1991 cpu_loop_exit_atomic(env_cpu(env
), retaddr
);
1997 * We support two different access types. SOFTMMU_CODE_ACCESS is
1998 * specifically for reading instructions from system memory. It is
1999 * called by the translation loop and in some helpers where the code
2000 * is disassembled. It shouldn't be called directly by guest code.
2002 * For the benefit of TCG generated code, we want to avoid the
2003 * complication of ABI-specific return type promotion and always
2004 * return a value extended to the register size of the host. This is
2005 * tcg_target_long, except in the case of a 32-bit host and 64-bit
2006 * data, and for that we always have uint64_t.
2008 * We don't bother with this widened value for SOFTMMU_CODE_ACCESS.
2014 * @p: translation parameters
2015 * @ret_be: accumulated data
2016 * @mmu_idx: virtual address context
2017 * @ra: return address into tcg generated code, or 0
2019 * Load @p->size bytes from @p->addr, which is memory-mapped i/o.
2020 * The bytes are concatenated in big-endian order with @ret_be.
2022 static uint64_t do_ld_mmio_beN(CPUArchState
*env
, MMULookupPageData
*p
,
2023 uint64_t ret_be
, int mmu_idx
,
2024 MMUAccessType type
, uintptr_t ra
)
2026 CPUTLBEntryFull
*full
= p
->full
;
2027 vaddr addr
= p
->addr
;
2028 int i
, size
= p
->size
;
2030 QEMU_IOTHREAD_LOCK_GUARD();
2031 for (i
= 0; i
< size
; i
++) {
2032 uint8_t x
= io_readx(env
, full
, mmu_idx
, addr
+ i
, ra
, type
, MO_UB
);
2033 ret_be
= (ret_be
<< 8) | x
;
2040 * @p: translation parameters
2041 * @ret_be: accumulated data
2043 * Load @p->size bytes from @p->haddr, which is RAM.
2044 * The bytes to concatenated in big-endian order with @ret_be.
2046 static uint64_t do_ld_bytes_beN(MMULookupPageData
*p
, uint64_t ret_be
)
2048 uint8_t *haddr
= p
->haddr
;
2049 int i
, size
= p
->size
;
2051 for (i
= 0; i
< size
; i
++) {
2052 ret_be
= (ret_be
<< 8) | haddr
[i
];
2059 * @p: translation parameters
2060 * @ret_be: accumulated data
2062 * As do_ld_bytes_beN, but atomically on each aligned part.
2064 static uint64_t do_ld_parts_beN(MMULookupPageData
*p
, uint64_t ret_be
)
2066 void *haddr
= p
->haddr
;
2074 * Find minimum of alignment and size.
2075 * This is slightly stronger than required by MO_ATOM_SUBALIGN, which
2076 * would have only checked the low bits of addr|size once at the start,
2077 * but is just as easy.
2079 switch (((uintptr_t)haddr
| size
) & 7) {
2081 x
= cpu_to_be32(load_atomic4(haddr
));
2082 ret_be
= (ret_be
<< 32) | x
;
2087 x
= cpu_to_be16(load_atomic2(haddr
));
2088 ret_be
= (ret_be
<< 16) | x
;
2092 x
= *(uint8_t *)haddr
;
2093 ret_be
= (ret_be
<< 8) | x
;
2097 g_assert_not_reached();
2101 } while (size
!= 0);
2107 * @p: translation parameters
2108 * @ret_be: accumulated data
2110 * As do_ld_bytes_beN, but with one atomic load.
2111 * Four aligned bytes are guaranteed to cover the load.
2113 static uint64_t do_ld_whole_be4(MMULookupPageData
*p
, uint64_t ret_be
)
2115 int o
= p
->addr
& 3;
2116 uint32_t x
= load_atomic4(p
->haddr
- o
);
2120 x
>>= (4 - p
->size
) * 8;
2121 return (ret_be
<< (p
->size
* 8)) | x
;
2126 * @p: translation parameters
2127 * @ret_be: accumulated data
2129 * As do_ld_bytes_beN, but with one atomic load.
2130 * Eight aligned bytes are guaranteed to cover the load.
2132 static uint64_t do_ld_whole_be8(CPUArchState
*env
, uintptr_t ra
,
2133 MMULookupPageData
*p
, uint64_t ret_be
)
2135 int o
= p
->addr
& 7;
2136 uint64_t x
= load_atomic8_or_exit(env
, ra
, p
->haddr
- o
);
2140 x
>>= (8 - p
->size
) * 8;
2141 return (ret_be
<< (p
->size
* 8)) | x
;
2146 * @p: translation parameters
2147 * @ret_be: accumulated data
2149 * As do_ld_bytes_beN, but with one atomic load.
2150 * 16 aligned bytes are guaranteed to cover the load.
2152 static Int128
do_ld_whole_be16(CPUArchState
*env
, uintptr_t ra
,
2153 MMULookupPageData
*p
, uint64_t ret_be
)
2155 int o
= p
->addr
& 15;
2156 Int128 x
, y
= load_atomic16_or_exit(env
, ra
, p
->haddr
- o
);
2159 if (!HOST_BIG_ENDIAN
) {
2162 y
= int128_lshift(y
, o
* 8);
2163 y
= int128_urshift(y
, (16 - size
) * 8);
2164 x
= int128_make64(ret_be
);
2165 x
= int128_lshift(x
, size
* 8);
2166 return int128_or(x
, y
);
2170 * Wrapper for the above.
2172 static uint64_t do_ld_beN(CPUArchState
*env
, MMULookupPageData
*p
,
2173 uint64_t ret_be
, int mmu_idx
, MMUAccessType type
,
2174 MemOp mop
, uintptr_t ra
)
2177 unsigned tmp
, half_size
;
2179 if (unlikely(p
->flags
& TLB_MMIO
)) {
2180 return do_ld_mmio_beN(env
, p
, ret_be
, mmu_idx
, type
, ra
);
2184 * It is a given that we cross a page and therefore there is no
2185 * atomicity for the load as a whole, but subobjects may need attention.
2187 atom
= mop
& MO_ATOM_MASK
;
2189 case MO_ATOM_SUBALIGN
:
2190 return do_ld_parts_beN(p
, ret_be
);
2192 case MO_ATOM_IFALIGN_PAIR
:
2193 case MO_ATOM_WITHIN16_PAIR
:
2194 tmp
= mop
& MO_SIZE
;
2195 tmp
= tmp
? tmp
- 1 : 0;
2196 half_size
= 1 << tmp
;
2197 if (atom
== MO_ATOM_IFALIGN_PAIR
2198 ? p
->size
== half_size
2199 : p
->size
>= half_size
) {
2200 if (!HAVE_al8_fast
&& p
->size
< 4) {
2201 return do_ld_whole_be4(p
, ret_be
);
2203 return do_ld_whole_be8(env
, ra
, p
, ret_be
);
2208 case MO_ATOM_IFALIGN
:
2209 case MO_ATOM_WITHIN16
:
2211 return do_ld_bytes_beN(p
, ret_be
);
2214 g_assert_not_reached();
2219 * Wrapper for the above, for 8 < size < 16.
2221 static Int128
do_ld16_beN(CPUArchState
*env
, MMULookupPageData
*p
,
2222 uint64_t a
, int mmu_idx
, MemOp mop
, uintptr_t ra
)
2228 if (unlikely(p
->flags
& TLB_MMIO
)) {
2230 a
= do_ld_mmio_beN(env
, p
, a
, mmu_idx
, MMU_DATA_LOAD
, ra
);
2233 b
= do_ld_mmio_beN(env
, p
, 0, mmu_idx
, MMU_DATA_LOAD
, ra
);
2234 return int128_make128(b
, a
);
2238 * It is a given that we cross a page and therefore there is no
2239 * atomicity for the load as a whole, but subobjects may need attention.
2241 atom
= mop
& MO_ATOM_MASK
;
2243 case MO_ATOM_SUBALIGN
:
2245 a
= do_ld_parts_beN(p
, a
);
2246 p
->haddr
+= size
- 8;
2248 b
= do_ld_parts_beN(p
, 0);
2251 case MO_ATOM_WITHIN16_PAIR
:
2252 /* Since size > 8, this is the half that must be atomic. */
2253 return do_ld_whole_be16(env
, ra
, p
, a
);
2255 case MO_ATOM_IFALIGN_PAIR
:
2257 * Since size > 8, both halves are misaligned,
2258 * and so neither is atomic.
2260 case MO_ATOM_IFALIGN
:
2261 case MO_ATOM_WITHIN16
:
2264 a
= do_ld_bytes_beN(p
, a
);
2265 b
= ldq_be_p(p
->haddr
+ size
- 8);
2269 g_assert_not_reached();
2272 return int128_make128(b
, a
);
2275 static uint8_t do_ld_1(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2276 MMUAccessType type
, uintptr_t ra
)
2278 if (unlikely(p
->flags
& TLB_MMIO
)) {
2279 return io_readx(env
, p
->full
, mmu_idx
, p
->addr
, ra
, type
, MO_UB
);
2281 return *(uint8_t *)p
->haddr
;
2285 static uint16_t do_ld_2(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2286 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2290 if (unlikely(p
->flags
& TLB_MMIO
)) {
2291 return io_readx(env
, p
->full
, mmu_idx
, p
->addr
, ra
, type
, memop
);
2294 /* Perform the load host endian, then swap if necessary. */
2295 ret
= load_atom_2(env
, ra
, p
->haddr
, memop
);
2296 if (memop
& MO_BSWAP
) {
2302 static uint32_t do_ld_4(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2303 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2307 if (unlikely(p
->flags
& TLB_MMIO
)) {
2308 return io_readx(env
, p
->full
, mmu_idx
, p
->addr
, ra
, type
, memop
);
2311 /* Perform the load host endian. */
2312 ret
= load_atom_4(env
, ra
, p
->haddr
, memop
);
2313 if (memop
& MO_BSWAP
) {
2319 static uint64_t do_ld_8(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2320 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2324 if (unlikely(p
->flags
& TLB_MMIO
)) {
2325 return io_readx(env
, p
->full
, mmu_idx
, p
->addr
, ra
, type
, memop
);
2328 /* Perform the load host endian. */
2329 ret
= load_atom_8(env
, ra
, p
->haddr
, memop
);
2330 if (memop
& MO_BSWAP
) {
2336 static uint8_t do_ld1_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2337 uintptr_t ra
, MMUAccessType access_type
)
2342 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2343 tcg_debug_assert(!crosspage
);
2345 return do_ld_1(env
, &l
.page
[0], l
.mmu_idx
, access_type
, ra
);
2348 tcg_target_ulong
helper_ldub_mmu(CPUArchState
*env
, uint64_t addr
,
2349 MemOpIdx oi
, uintptr_t retaddr
)
2351 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_8
);
2352 return do_ld1_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2355 static uint16_t do_ld2_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2356 uintptr_t ra
, MMUAccessType access_type
)
2363 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2364 if (likely(!crosspage
)) {
2365 return do_ld_2(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2368 a
= do_ld_1(env
, &l
.page
[0], l
.mmu_idx
, access_type
, ra
);
2369 b
= do_ld_1(env
, &l
.page
[1], l
.mmu_idx
, access_type
, ra
);
2371 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2379 tcg_target_ulong
helper_lduw_mmu(CPUArchState
*env
, uint64_t addr
,
2380 MemOpIdx oi
, uintptr_t retaddr
)
2382 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2383 return do_ld2_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2386 static uint32_t do_ld4_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2387 uintptr_t ra
, MMUAccessType access_type
)
2393 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2394 if (likely(!crosspage
)) {
2395 return do_ld_4(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2398 ret
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2399 ret
= do_ld_beN(env
, &l
.page
[1], ret
, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2400 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2406 tcg_target_ulong
helper_ldul_mmu(CPUArchState
*env
, uint64_t addr
,
2407 MemOpIdx oi
, uintptr_t retaddr
)
2409 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2410 return do_ld4_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2413 static uint64_t do_ld8_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2414 uintptr_t ra
, MMUAccessType access_type
)
2420 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2421 if (likely(!crosspage
)) {
2422 return do_ld_8(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2425 ret
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2426 ret
= do_ld_beN(env
, &l
.page
[1], ret
, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2427 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2433 uint64_t helper_ldq_mmu(CPUArchState
*env
, uint64_t addr
,
2434 MemOpIdx oi
, uintptr_t retaddr
)
2436 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
2437 return do_ld8_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2441 * Provide signed versions of the load routines as well. We can of course
2442 * avoid this for 64-bit data, or for 32-bit data on 32-bit host.
2445 tcg_target_ulong
helper_ldsb_mmu(CPUArchState
*env
, uint64_t addr
,
2446 MemOpIdx oi
, uintptr_t retaddr
)
2448 return (int8_t)helper_ldub_mmu(env
, addr
, oi
, retaddr
);
2451 tcg_target_ulong
helper_ldsw_mmu(CPUArchState
*env
, uint64_t addr
,
2452 MemOpIdx oi
, uintptr_t retaddr
)
2454 return (int16_t)helper_lduw_mmu(env
, addr
, oi
, retaddr
);
2457 tcg_target_ulong
helper_ldsl_mmu(CPUArchState
*env
, uint64_t addr
,
2458 MemOpIdx oi
, uintptr_t retaddr
)
2460 return (int32_t)helper_ldul_mmu(env
, addr
, oi
, retaddr
);
2463 static Int128
do_ld16_mmu(CPUArchState
*env
, vaddr addr
,
2464 MemOpIdx oi
, uintptr_t ra
)
2472 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_LOAD
, &l
);
2473 if (likely(!crosspage
)) {
2474 /* Perform the load host endian. */
2475 if (unlikely(l
.page
[0].flags
& TLB_MMIO
)) {
2476 QEMU_IOTHREAD_LOCK_GUARD();
2477 a
= io_readx(env
, l
.page
[0].full
, l
.mmu_idx
, addr
,
2478 ra
, MMU_DATA_LOAD
, MO_64
);
2479 b
= io_readx(env
, l
.page
[0].full
, l
.mmu_idx
, addr
+ 8,
2480 ra
, MMU_DATA_LOAD
, MO_64
);
2481 ret
= int128_make128(HOST_BIG_ENDIAN
? b
: a
,
2482 HOST_BIG_ENDIAN
? a
: b
);
2484 ret
= load_atom_16(env
, ra
, l
.page
[0].haddr
, l
.memop
);
2486 if (l
.memop
& MO_BSWAP
) {
2487 ret
= bswap128(ret
);
2492 first
= l
.page
[0].size
;
2494 MemOp mop8
= (l
.memop
& ~MO_SIZE
) | MO_64
;
2496 a
= do_ld_8(env
, &l
.page
[0], l
.mmu_idx
, MMU_DATA_LOAD
, mop8
, ra
);
2497 b
= do_ld_8(env
, &l
.page
[1], l
.mmu_idx
, MMU_DATA_LOAD
, mop8
, ra
);
2498 if ((mop8
& MO_BSWAP
) == MO_LE
) {
2499 ret
= int128_make128(a
, b
);
2501 ret
= int128_make128(b
, a
);
2507 a
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
,
2508 MMU_DATA_LOAD
, l
.memop
, ra
);
2509 ret
= do_ld16_beN(env
, &l
.page
[1], a
, l
.mmu_idx
, l
.memop
, ra
);
2511 ret
= do_ld16_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, l
.memop
, ra
);
2512 b
= int128_getlo(ret
);
2513 ret
= int128_lshift(ret
, l
.page
[1].size
* 8);
2514 a
= int128_gethi(ret
);
2515 b
= do_ld_beN(env
, &l
.page
[1], b
, l
.mmu_idx
,
2516 MMU_DATA_LOAD
, l
.memop
, ra
);
2517 ret
= int128_make128(b
, a
);
2519 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2520 ret
= bswap128(ret
);
2525 Int128
helper_ld16_mmu(CPUArchState
*env
, uint64_t addr
,
2526 uint32_t oi
, uintptr_t retaddr
)
2528 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
2529 return do_ld16_mmu(env
, addr
, oi
, retaddr
);
2532 Int128
helper_ld_i128(CPUArchState
*env
, uint64_t addr
, uint32_t oi
)
2534 return helper_ld16_mmu(env
, addr
, oi
, GETPC());
2538 * Load helpers for cpu_ldst.h.
2541 static void plugin_load_cb(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
)
2543 qemu_plugin_vcpu_mem_cb(env_cpu(env
), addr
, oi
, QEMU_PLUGIN_MEM_R
);
2546 uint8_t cpu_ldb_mmu(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
, uintptr_t ra
)
2550 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_UB
);
2551 ret
= do_ld1_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2552 plugin_load_cb(env
, addr
, oi
);
2556 uint16_t cpu_ldw_mmu(CPUArchState
*env
, abi_ptr addr
,
2557 MemOpIdx oi
, uintptr_t ra
)
2561 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2562 ret
= do_ld2_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2563 plugin_load_cb(env
, addr
, oi
);
2567 uint32_t cpu_ldl_mmu(CPUArchState
*env
, abi_ptr addr
,
2568 MemOpIdx oi
, uintptr_t ra
)
2572 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2573 ret
= do_ld4_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2574 plugin_load_cb(env
, addr
, oi
);
2578 uint64_t cpu_ldq_mmu(CPUArchState
*env
, abi_ptr addr
,
2579 MemOpIdx oi
, uintptr_t ra
)
2583 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
2584 ret
= do_ld8_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2585 plugin_load_cb(env
, addr
, oi
);
2589 Int128
cpu_ld16_mmu(CPUArchState
*env
, abi_ptr addr
,
2590 MemOpIdx oi
, uintptr_t ra
)
2594 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
2595 ret
= do_ld16_mmu(env
, addr
, oi
, ra
);
2596 plugin_load_cb(env
, addr
, oi
);
2607 * @p: translation parameters
2608 * @val_le: data to store
2609 * @mmu_idx: virtual address context
2610 * @ra: return address into tcg generated code, or 0
2612 * Store @p->size bytes at @p->addr, which is memory-mapped i/o.
2613 * The bytes to store are extracted in little-endian order from @val_le;
2614 * return the bytes of @val_le beyond @p->size that have not been stored.
2616 static uint64_t do_st_mmio_leN(CPUArchState
*env
, MMULookupPageData
*p
,
2617 uint64_t val_le
, int mmu_idx
, uintptr_t ra
)
2619 CPUTLBEntryFull
*full
= p
->full
;
2620 vaddr addr
= p
->addr
;
2621 int i
, size
= p
->size
;
2623 QEMU_IOTHREAD_LOCK_GUARD();
2624 for (i
= 0; i
< size
; i
++, val_le
>>= 8) {
2625 io_writex(env
, full
, mmu_idx
, val_le
, addr
+ i
, ra
, MO_UB
);
2631 * Wrapper for the above.
2633 static uint64_t do_st_leN(CPUArchState
*env
, MMULookupPageData
*p
,
2634 uint64_t val_le
, int mmu_idx
,
2635 MemOp mop
, uintptr_t ra
)
2638 unsigned tmp
, half_size
;
2640 if (unlikely(p
->flags
& TLB_MMIO
)) {
2641 return do_st_mmio_leN(env
, p
, val_le
, mmu_idx
, ra
);
2642 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2643 return val_le
>> (p
->size
* 8);
2647 * It is a given that we cross a page and therefore there is no atomicity
2648 * for the store as a whole, but subobjects may need attention.
2650 atom
= mop
& MO_ATOM_MASK
;
2652 case MO_ATOM_SUBALIGN
:
2653 return store_parts_leN(p
->haddr
, p
->size
, val_le
);
2655 case MO_ATOM_IFALIGN_PAIR
:
2656 case MO_ATOM_WITHIN16_PAIR
:
2657 tmp
= mop
& MO_SIZE
;
2658 tmp
= tmp
? tmp
- 1 : 0;
2659 half_size
= 1 << tmp
;
2660 if (atom
== MO_ATOM_IFALIGN_PAIR
2661 ? p
->size
== half_size
2662 : p
->size
>= half_size
) {
2663 if (!HAVE_al8_fast
&& p
->size
<= 4) {
2664 return store_whole_le4(p
->haddr
, p
->size
, val_le
);
2665 } else if (HAVE_al8
) {
2666 return store_whole_le8(p
->haddr
, p
->size
, val_le
);
2668 cpu_loop_exit_atomic(env_cpu(env
), ra
);
2673 case MO_ATOM_IFALIGN
:
2674 case MO_ATOM_WITHIN16
:
2676 return store_bytes_leN(p
->haddr
, p
->size
, val_le
);
2679 g_assert_not_reached();
2684 * Wrapper for the above, for 8 < size < 16.
2686 static uint64_t do_st16_leN(CPUArchState
*env
, MMULookupPageData
*p
,
2687 Int128 val_le
, int mmu_idx
,
2688 MemOp mop
, uintptr_t ra
)
2693 if (unlikely(p
->flags
& TLB_MMIO
)) {
2695 do_st_mmio_leN(env
, p
, int128_getlo(val_le
), mmu_idx
, ra
);
2698 return do_st_mmio_leN(env
, p
, int128_gethi(val_le
), mmu_idx
, ra
);
2699 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2700 return int128_gethi(val_le
) >> ((size
- 8) * 8);
2704 * It is a given that we cross a page and therefore there is no atomicity
2705 * for the store as a whole, but subobjects may need attention.
2707 atom
= mop
& MO_ATOM_MASK
;
2709 case MO_ATOM_SUBALIGN
:
2710 store_parts_leN(p
->haddr
, 8, int128_getlo(val_le
));
2711 return store_parts_leN(p
->haddr
+ 8, p
->size
- 8,
2712 int128_gethi(val_le
));
2714 case MO_ATOM_WITHIN16_PAIR
:
2715 /* Since size > 8, this is the half that must be atomic. */
2716 if (!HAVE_ATOMIC128_RW
) {
2717 cpu_loop_exit_atomic(env_cpu(env
), ra
);
2719 return store_whole_le16(p
->haddr
, p
->size
, val_le
);
2721 case MO_ATOM_IFALIGN_PAIR
:
2723 * Since size > 8, both halves are misaligned,
2724 * and so neither is atomic.
2726 case MO_ATOM_IFALIGN
:
2727 case MO_ATOM_WITHIN16
:
2729 stq_le_p(p
->haddr
, int128_getlo(val_le
));
2730 return store_bytes_leN(p
->haddr
+ 8, p
->size
- 8,
2731 int128_gethi(val_le
));
2734 g_assert_not_reached();
2738 static void do_st_1(CPUArchState
*env
, MMULookupPageData
*p
, uint8_t val
,
2739 int mmu_idx
, uintptr_t ra
)
2741 if (unlikely(p
->flags
& TLB_MMIO
)) {
2742 io_writex(env
, p
->full
, mmu_idx
, val
, p
->addr
, ra
, MO_UB
);
2743 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2746 *(uint8_t *)p
->haddr
= val
;
2750 static void do_st_2(CPUArchState
*env
, MMULookupPageData
*p
, uint16_t val
,
2751 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2753 if (unlikely(p
->flags
& TLB_MMIO
)) {
2754 io_writex(env
, p
->full
, mmu_idx
, val
, p
->addr
, ra
, memop
);
2755 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2758 /* Swap to host endian if necessary, then store. */
2759 if (memop
& MO_BSWAP
) {
2762 store_atom_2(env
, ra
, p
->haddr
, memop
, val
);
2766 static void do_st_4(CPUArchState
*env
, MMULookupPageData
*p
, uint32_t val
,
2767 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2769 if (unlikely(p
->flags
& TLB_MMIO
)) {
2770 io_writex(env
, p
->full
, mmu_idx
, val
, p
->addr
, ra
, memop
);
2771 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2774 /* Swap to host endian if necessary, then store. */
2775 if (memop
& MO_BSWAP
) {
2778 store_atom_4(env
, ra
, p
->haddr
, memop
, val
);
2782 static void do_st_8(CPUArchState
*env
, MMULookupPageData
*p
, uint64_t val
,
2783 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2785 if (unlikely(p
->flags
& TLB_MMIO
)) {
2786 io_writex(env
, p
->full
, mmu_idx
, val
, p
->addr
, ra
, memop
);
2787 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2790 /* Swap to host endian if necessary, then store. */
2791 if (memop
& MO_BSWAP
) {
2794 store_atom_8(env
, ra
, p
->haddr
, memop
, val
);
2798 void helper_stb_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
2799 MemOpIdx oi
, uintptr_t ra
)
2804 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_8
);
2805 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2806 tcg_debug_assert(!crosspage
);
2808 do_st_1(env
, &l
.page
[0], val
, l
.mmu_idx
, ra
);
2811 static void do_st2_mmu(CPUArchState
*env
, vaddr addr
, uint16_t val
,
2812 MemOpIdx oi
, uintptr_t ra
)
2818 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2819 if (likely(!crosspage
)) {
2820 do_st_2(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2824 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2825 a
= val
, b
= val
>> 8;
2827 b
= val
, a
= val
>> 8;
2829 do_st_1(env
, &l
.page
[0], a
, l
.mmu_idx
, ra
);
2830 do_st_1(env
, &l
.page
[1], b
, l
.mmu_idx
, ra
);
2833 void helper_stw_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
2834 MemOpIdx oi
, uintptr_t retaddr
)
2836 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2837 do_st2_mmu(env
, addr
, val
, oi
, retaddr
);
2840 static void do_st4_mmu(CPUArchState
*env
, vaddr addr
, uint32_t val
,
2841 MemOpIdx oi
, uintptr_t ra
)
2846 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2847 if (likely(!crosspage
)) {
2848 do_st_4(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2852 /* Swap to little endian for simplicity, then store by bytes. */
2853 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
2856 val
= do_st_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2857 (void) do_st_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
2860 void helper_stl_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
2861 MemOpIdx oi
, uintptr_t retaddr
)
2863 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2864 do_st4_mmu(env
, addr
, val
, oi
, retaddr
);
2867 static void do_st8_mmu(CPUArchState
*env
, vaddr addr
, uint64_t val
,
2868 MemOpIdx oi
, uintptr_t ra
)
2873 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2874 if (likely(!crosspage
)) {
2875 do_st_8(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2879 /* Swap to little endian for simplicity, then store by bytes. */
2880 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
2883 val
= do_st_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2884 (void) do_st_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
2887 void helper_stq_mmu(CPUArchState
*env
, uint64_t addr
, uint64_t val
,
2888 MemOpIdx oi
, uintptr_t retaddr
)
2890 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
2891 do_st8_mmu(env
, addr
, val
, oi
, retaddr
);
2894 static void do_st16_mmu(CPUArchState
*env
, vaddr addr
, Int128 val
,
2895 MemOpIdx oi
, uintptr_t ra
)
2902 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2903 if (likely(!crosspage
)) {
2904 /* Swap to host endian if necessary, then store. */
2905 if (l
.memop
& MO_BSWAP
) {
2906 val
= bswap128(val
);
2908 if (unlikely(l
.page
[0].flags
& TLB_MMIO
)) {
2909 QEMU_IOTHREAD_LOCK_GUARD();
2910 if (HOST_BIG_ENDIAN
) {
2911 b
= int128_getlo(val
), a
= int128_gethi(val
);
2913 a
= int128_getlo(val
), b
= int128_gethi(val
);
2915 io_writex(env
, l
.page
[0].full
, l
.mmu_idx
, a
, addr
, ra
, MO_64
);
2916 io_writex(env
, l
.page
[0].full
, l
.mmu_idx
, b
, addr
+ 8, ra
, MO_64
);
2917 } else if (unlikely(l
.page
[0].flags
& TLB_DISCARD_WRITE
)) {
2920 store_atom_16(env
, ra
, l
.page
[0].haddr
, l
.memop
, val
);
2925 first
= l
.page
[0].size
;
2927 MemOp mop8
= (l
.memop
& ~(MO_SIZE
| MO_BSWAP
)) | MO_64
;
2929 if (l
.memop
& MO_BSWAP
) {
2930 val
= bswap128(val
);
2932 if (HOST_BIG_ENDIAN
) {
2933 b
= int128_getlo(val
), a
= int128_gethi(val
);
2935 a
= int128_getlo(val
), b
= int128_gethi(val
);
2937 do_st_8(env
, &l
.page
[0], a
, l
.mmu_idx
, mop8
, ra
);
2938 do_st_8(env
, &l
.page
[1], b
, l
.mmu_idx
, mop8
, ra
);
2942 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
2943 val
= bswap128(val
);
2946 do_st_leN(env
, &l
.page
[0], int128_getlo(val
), l
.mmu_idx
, l
.memop
, ra
);
2947 val
= int128_urshift(val
, first
* 8);
2948 do_st16_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
2950 b
= do_st16_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2951 do_st_leN(env
, &l
.page
[1], b
, l
.mmu_idx
, l
.memop
, ra
);
2955 void helper_st16_mmu(CPUArchState
*env
, uint64_t addr
, Int128 val
,
2956 MemOpIdx oi
, uintptr_t retaddr
)
2958 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
2959 do_st16_mmu(env
, addr
, val
, oi
, retaddr
);
2962 void helper_st_i128(CPUArchState
*env
, uint64_t addr
, Int128 val
, MemOpIdx oi
)
2964 helper_st16_mmu(env
, addr
, val
, oi
, GETPC());
2968 * Store Helpers for cpu_ldst.h
2971 static void plugin_store_cb(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
)
2973 qemu_plugin_vcpu_mem_cb(env_cpu(env
), addr
, oi
, QEMU_PLUGIN_MEM_W
);
2976 void cpu_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint8_t val
,
2977 MemOpIdx oi
, uintptr_t retaddr
)
2979 helper_stb_mmu(env
, addr
, val
, oi
, retaddr
);
2980 plugin_store_cb(env
, addr
, oi
);
2983 void cpu_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
2984 MemOpIdx oi
, uintptr_t retaddr
)
2986 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2987 do_st2_mmu(env
, addr
, val
, oi
, retaddr
);
2988 plugin_store_cb(env
, addr
, oi
);
2991 void cpu_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
2992 MemOpIdx oi
, uintptr_t retaddr
)
2994 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2995 do_st4_mmu(env
, addr
, val
, oi
, retaddr
);
2996 plugin_store_cb(env
, addr
, oi
);
2999 void cpu_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
3000 MemOpIdx oi
, uintptr_t retaddr
)
3002 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
3003 do_st8_mmu(env
, addr
, val
, oi
, retaddr
);
3004 plugin_store_cb(env
, addr
, oi
);
3007 void cpu_st16_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
3008 MemOpIdx oi
, uintptr_t retaddr
)
3010 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
3011 do_st16_mmu(env
, addr
, val
, oi
, retaddr
);
3012 plugin_store_cb(env
, addr
, oi
);
3015 #include "ldst_common.c.inc"
3018 * First set of functions passes in OI and RETADDR.
3019 * This makes them callable from other helpers.
3022 #define ATOMIC_NAME(X) \
3023 glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
3025 #define ATOMIC_MMU_CLEANUP
3027 #include "atomic_common.c.inc"
3030 #include "atomic_template.h"
3033 #include "atomic_template.h"
3036 #include "atomic_template.h"
3038 #ifdef CONFIG_ATOMIC64
3040 #include "atomic_template.h"
3043 #if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128)
3044 #define DATA_SIZE 16
3045 #include "atomic_template.h"
3048 /* Code access functions. */
3050 uint32_t cpu_ldub_code(CPUArchState
*env
, abi_ptr addr
)
3052 MemOpIdx oi
= make_memop_idx(MO_UB
, cpu_mmu_index(env
, true));
3053 return do_ld1_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3056 uint32_t cpu_lduw_code(CPUArchState
*env
, abi_ptr addr
)
3058 MemOpIdx oi
= make_memop_idx(MO_TEUW
, cpu_mmu_index(env
, true));
3059 return do_ld2_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3062 uint32_t cpu_ldl_code(CPUArchState
*env
, abi_ptr addr
)
3064 MemOpIdx oi
= make_memop_idx(MO_TEUL
, cpu_mmu_index(env
, true));
3065 return do_ld4_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3068 uint64_t cpu_ldq_code(CPUArchState
*env
, abi_ptr addr
)
3070 MemOpIdx oi
= make_memop_idx(MO_TEUQ
, cpu_mmu_index(env
, true));
3071 return do_ld8_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3074 uint8_t cpu_ldb_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3075 MemOpIdx oi
, uintptr_t retaddr
)
3077 return do_ld1_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3080 uint16_t cpu_ldw_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3081 MemOpIdx oi
, uintptr_t retaddr
)
3083 return do_ld2_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3086 uint32_t cpu_ldl_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3087 MemOpIdx oi
, uintptr_t retaddr
)
3089 return do_ld4_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3092 uint64_t cpu_ldq_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3093 MemOpIdx oi
, uintptr_t retaddr
)
3095 return do_ld8_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);