2 * Common CPU TLB handling
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
22 #include "hw/core/tcg-cpu-ops.h"
23 #include "exec/exec-all.h"
24 #include "exec/memory.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/cputlb.h"
27 #include "exec/memory-internal.h"
28 #include "exec/ram_addr.h"
30 #include "qemu/error-report.h"
32 #include "exec/helper-proto-common.h"
33 #include "qemu/atomic.h"
34 #include "qemu/atomic128.h"
35 #include "exec/translate-all.h"
40 #include "qemu/plugin-memory.h"
42 #include "tcg/tcg-ldst.h"
43 #include "tcg/oversized-guest.h"
45 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
46 /* #define DEBUG_TLB */
47 /* #define DEBUG_TLB_LOG */
50 # define DEBUG_TLB_GATE 1
52 # define DEBUG_TLB_LOG_GATE 1
54 # define DEBUG_TLB_LOG_GATE 0
57 # define DEBUG_TLB_GATE 0
58 # define DEBUG_TLB_LOG_GATE 0
61 #define tlb_debug(fmt, ...) do { \
62 if (DEBUG_TLB_LOG_GATE) { \
63 qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
65 } else if (DEBUG_TLB_GATE) { \
66 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
70 #define assert_cpu_is_self(cpu) do { \
71 if (DEBUG_TLB_GATE) { \
72 g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \
76 /* run_on_cpu_data.target_ptr should always be big enough for a
77 * target_ulong even on 32 bit builds */
78 QEMU_BUILD_BUG_ON(sizeof(target_ulong
) > sizeof(run_on_cpu_data
));
80 /* We currently can't handle more than 16 bits in the MMUIDX bitmask.
82 QEMU_BUILD_BUG_ON(NB_MMU_MODES
> 16);
83 #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
85 static inline size_t tlb_n_entries(CPUTLBDescFast
*fast
)
87 return (fast
->mask
>> CPU_TLB_ENTRY_BITS
) + 1;
90 static inline size_t sizeof_tlb(CPUTLBDescFast
*fast
)
92 return fast
->mask
+ (1 << CPU_TLB_ENTRY_BITS
);
95 static void tlb_window_reset(CPUTLBDesc
*desc
, int64_t ns
,
98 desc
->window_begin_ns
= ns
;
99 desc
->window_max_entries
= max_entries
;
102 static void tb_jmp_cache_clear_page(CPUState
*cpu
, vaddr page_addr
)
104 CPUJumpCache
*jc
= cpu
->tb_jmp_cache
;
111 i0
= tb_jmp_cache_hash_page(page_addr
);
112 for (i
= 0; i
< TB_JMP_PAGE_SIZE
; i
++) {
113 qatomic_set(&jc
->array
[i0
+ i
].tb
, NULL
);
118 * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
119 * @desc: The CPUTLBDesc portion of the TLB
120 * @fast: The CPUTLBDescFast portion of the same TLB
122 * Called with tlb_lock_held.
124 * We have two main constraints when resizing a TLB: (1) we only resize it
125 * on a TLB flush (otherwise we'd have to take a perf hit by either rehashing
126 * the array or unnecessarily flushing it), which means we do not control how
127 * frequently the resizing can occur; (2) we don't have access to the guest's
128 * future scheduling decisions, and therefore have to decide the magnitude of
129 * the resize based on past observations.
131 * In general, a memory-hungry process can benefit greatly from an appropriately
132 * sized TLB, since a guest TLB miss is very expensive. This doesn't mean that
133 * we just have to make the TLB as large as possible; while an oversized TLB
134 * results in minimal TLB miss rates, it also takes longer to be flushed
135 * (flushes can be _very_ frequent), and the reduced locality can also hurt
138 * To achieve near-optimal performance for all kinds of workloads, we:
140 * 1. Aggressively increase the size of the TLB when the use rate of the
141 * TLB being flushed is high, since it is likely that in the near future this
142 * memory-hungry process will execute again, and its memory hungriness will
143 * probably be similar.
145 * 2. Slowly reduce the size of the TLB as the use rate declines over a
146 * reasonably large time window. The rationale is that if in such a time window
147 * we have not observed a high TLB use rate, it is likely that we won't observe
148 * it in the near future. In that case, once a time window expires we downsize
149 * the TLB to match the maximum use rate observed in the window.
151 * 3. Try to keep the maximum use rate in a time window in the 30-70% range,
152 * since in that range performance is likely near-optimal. Recall that the TLB
153 * is direct mapped, so we want the use rate to be low (or at least not too
154 * high), since otherwise we are likely to have a significant amount of
157 static void tlb_mmu_resize_locked(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
,
160 size_t old_size
= tlb_n_entries(fast
);
162 size_t new_size
= old_size
;
163 int64_t window_len_ms
= 100;
164 int64_t window_len_ns
= window_len_ms
* 1000 * 1000;
165 bool window_expired
= now
> desc
->window_begin_ns
+ window_len_ns
;
167 if (desc
->n_used_entries
> desc
->window_max_entries
) {
168 desc
->window_max_entries
= desc
->n_used_entries
;
170 rate
= desc
->window_max_entries
* 100 / old_size
;
173 new_size
= MIN(old_size
<< 1, 1 << CPU_TLB_DYN_MAX_BITS
);
174 } else if (rate
< 30 && window_expired
) {
175 size_t ceil
= pow2ceil(desc
->window_max_entries
);
176 size_t expected_rate
= desc
->window_max_entries
* 100 / ceil
;
179 * Avoid undersizing when the max number of entries seen is just below
180 * a pow2. For instance, if max_entries == 1025, the expected use rate
181 * would be 1025/2048==50%. However, if max_entries == 1023, we'd get
182 * 1023/1024==99.9% use rate, so we'd likely end up doubling the size
183 * later. Thus, make sure that the expected use rate remains below 70%.
184 * (and since we double the size, that means the lowest rate we'd
185 * expect to get is 35%, which is still in the 30-70% range where
186 * we consider that the size is appropriate.)
188 if (expected_rate
> 70) {
191 new_size
= MAX(ceil
, 1 << CPU_TLB_DYN_MIN_BITS
);
194 if (new_size
== old_size
) {
195 if (window_expired
) {
196 tlb_window_reset(desc
, now
, desc
->n_used_entries
);
202 g_free(desc
->fulltlb
);
204 tlb_window_reset(desc
, now
, 0);
205 /* desc->n_used_entries is cleared by the caller */
206 fast
->mask
= (new_size
- 1) << CPU_TLB_ENTRY_BITS
;
207 fast
->table
= g_try_new(CPUTLBEntry
, new_size
);
208 desc
->fulltlb
= g_try_new(CPUTLBEntryFull
, new_size
);
211 * If the allocations fail, try smaller sizes. We just freed some
212 * memory, so going back to half of new_size has a good chance of working.
213 * Increased memory pressure elsewhere in the system might cause the
214 * allocations to fail though, so we progressively reduce the allocation
215 * size, aborting if we cannot even allocate the smallest TLB we support.
217 while (fast
->table
== NULL
|| desc
->fulltlb
== NULL
) {
218 if (new_size
== (1 << CPU_TLB_DYN_MIN_BITS
)) {
219 error_report("%s: %s", __func__
, strerror(errno
));
222 new_size
= MAX(new_size
>> 1, 1 << CPU_TLB_DYN_MIN_BITS
);
223 fast
->mask
= (new_size
- 1) << CPU_TLB_ENTRY_BITS
;
226 g_free(desc
->fulltlb
);
227 fast
->table
= g_try_new(CPUTLBEntry
, new_size
);
228 desc
->fulltlb
= g_try_new(CPUTLBEntryFull
, new_size
);
232 static void tlb_mmu_flush_locked(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
)
234 desc
->n_used_entries
= 0;
235 desc
->large_page_addr
= -1;
236 desc
->large_page_mask
= -1;
238 memset(fast
->table
, -1, sizeof_tlb(fast
));
239 memset(desc
->vtable
, -1, sizeof(desc
->vtable
));
242 static void tlb_flush_one_mmuidx_locked(CPUArchState
*env
, int mmu_idx
,
245 CPUTLBDesc
*desc
= &env_tlb(env
)->d
[mmu_idx
];
246 CPUTLBDescFast
*fast
= &env_tlb(env
)->f
[mmu_idx
];
248 tlb_mmu_resize_locked(desc
, fast
, now
);
249 tlb_mmu_flush_locked(desc
, fast
);
252 static void tlb_mmu_init(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
, int64_t now
)
254 size_t n_entries
= 1 << CPU_TLB_DYN_DEFAULT_BITS
;
256 tlb_window_reset(desc
, now
, 0);
257 desc
->n_used_entries
= 0;
258 fast
->mask
= (n_entries
- 1) << CPU_TLB_ENTRY_BITS
;
259 fast
->table
= g_new(CPUTLBEntry
, n_entries
);
260 desc
->fulltlb
= g_new(CPUTLBEntryFull
, n_entries
);
261 tlb_mmu_flush_locked(desc
, fast
);
264 static inline void tlb_n_used_entries_inc(CPUArchState
*env
, uintptr_t mmu_idx
)
266 env_tlb(env
)->d
[mmu_idx
].n_used_entries
++;
269 static inline void tlb_n_used_entries_dec(CPUArchState
*env
, uintptr_t mmu_idx
)
271 env_tlb(env
)->d
[mmu_idx
].n_used_entries
--;
274 void tlb_init(CPUState
*cpu
)
276 CPUArchState
*env
= cpu
->env_ptr
;
277 int64_t now
= get_clock_realtime();
280 qemu_spin_init(&env_tlb(env
)->c
.lock
);
282 /* All tlbs are initialized flushed. */
283 env_tlb(env
)->c
.dirty
= 0;
285 for (i
= 0; i
< NB_MMU_MODES
; i
++) {
286 tlb_mmu_init(&env_tlb(env
)->d
[i
], &env_tlb(env
)->f
[i
], now
);
290 void tlb_destroy(CPUState
*cpu
)
292 CPUArchState
*env
= cpu
->env_ptr
;
295 qemu_spin_destroy(&env_tlb(env
)->c
.lock
);
296 for (i
= 0; i
< NB_MMU_MODES
; i
++) {
297 CPUTLBDesc
*desc
= &env_tlb(env
)->d
[i
];
298 CPUTLBDescFast
*fast
= &env_tlb(env
)->f
[i
];
301 g_free(desc
->fulltlb
);
305 /* flush_all_helper: run fn across all cpus
307 * If the wait flag is set then the src cpu's helper will be queued as
308 * "safe" work and the loop exited creating a synchronisation point
309 * where all queued work will be finished before execution starts
312 static void flush_all_helper(CPUState
*src
, run_on_cpu_func fn
,
319 async_run_on_cpu(cpu
, fn
, d
);
324 void tlb_flush_counts(size_t *pfull
, size_t *ppart
, size_t *pelide
)
327 size_t full
= 0, part
= 0, elide
= 0;
330 CPUArchState
*env
= cpu
->env_ptr
;
332 full
+= qatomic_read(&env_tlb(env
)->c
.full_flush_count
);
333 part
+= qatomic_read(&env_tlb(env
)->c
.part_flush_count
);
334 elide
+= qatomic_read(&env_tlb(env
)->c
.elide_flush_count
);
341 static void tlb_flush_by_mmuidx_async_work(CPUState
*cpu
, run_on_cpu_data data
)
343 CPUArchState
*env
= cpu
->env_ptr
;
344 uint16_t asked
= data
.host_int
;
345 uint16_t all_dirty
, work
, to_clean
;
346 int64_t now
= get_clock_realtime();
348 assert_cpu_is_self(cpu
);
350 tlb_debug("mmu_idx:0x%04" PRIx16
"\n", asked
);
352 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
354 all_dirty
= env_tlb(env
)->c
.dirty
;
355 to_clean
= asked
& all_dirty
;
356 all_dirty
&= ~to_clean
;
357 env_tlb(env
)->c
.dirty
= all_dirty
;
359 for (work
= to_clean
; work
!= 0; work
&= work
- 1) {
360 int mmu_idx
= ctz32(work
);
361 tlb_flush_one_mmuidx_locked(env
, mmu_idx
, now
);
364 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
366 tcg_flush_jmp_cache(cpu
);
368 if (to_clean
== ALL_MMUIDX_BITS
) {
369 qatomic_set(&env_tlb(env
)->c
.full_flush_count
,
370 env_tlb(env
)->c
.full_flush_count
+ 1);
372 qatomic_set(&env_tlb(env
)->c
.part_flush_count
,
373 env_tlb(env
)->c
.part_flush_count
+ ctpop16(to_clean
));
374 if (to_clean
!= asked
) {
375 qatomic_set(&env_tlb(env
)->c
.elide_flush_count
,
376 env_tlb(env
)->c
.elide_flush_count
+
377 ctpop16(asked
& ~to_clean
));
382 void tlb_flush_by_mmuidx(CPUState
*cpu
, uint16_t idxmap
)
384 tlb_debug("mmu_idx: 0x%" PRIx16
"\n", idxmap
);
386 if (cpu
->created
&& !qemu_cpu_is_self(cpu
)) {
387 async_run_on_cpu(cpu
, tlb_flush_by_mmuidx_async_work
,
388 RUN_ON_CPU_HOST_INT(idxmap
));
390 tlb_flush_by_mmuidx_async_work(cpu
, RUN_ON_CPU_HOST_INT(idxmap
));
394 void tlb_flush(CPUState
*cpu
)
396 tlb_flush_by_mmuidx(cpu
, ALL_MMUIDX_BITS
);
399 void tlb_flush_by_mmuidx_all_cpus(CPUState
*src_cpu
, uint16_t idxmap
)
401 const run_on_cpu_func fn
= tlb_flush_by_mmuidx_async_work
;
403 tlb_debug("mmu_idx: 0x%"PRIx16
"\n", idxmap
);
405 flush_all_helper(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
406 fn(src_cpu
, RUN_ON_CPU_HOST_INT(idxmap
));
409 void tlb_flush_all_cpus(CPUState
*src_cpu
)
411 tlb_flush_by_mmuidx_all_cpus(src_cpu
, ALL_MMUIDX_BITS
);
414 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
, uint16_t idxmap
)
416 const run_on_cpu_func fn
= tlb_flush_by_mmuidx_async_work
;
418 tlb_debug("mmu_idx: 0x%"PRIx16
"\n", idxmap
);
420 flush_all_helper(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
421 async_safe_run_on_cpu(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
424 void tlb_flush_all_cpus_synced(CPUState
*src_cpu
)
426 tlb_flush_by_mmuidx_all_cpus_synced(src_cpu
, ALL_MMUIDX_BITS
);
429 static bool tlb_hit_page_mask_anyprot(CPUTLBEntry
*tlb_entry
,
430 vaddr page
, vaddr mask
)
433 mask
&= TARGET_PAGE_MASK
| TLB_INVALID_MASK
;
435 return (page
== (tlb_entry
->addr_read
& mask
) ||
436 page
== (tlb_addr_write(tlb_entry
) & mask
) ||
437 page
== (tlb_entry
->addr_code
& mask
));
440 static inline bool tlb_hit_page_anyprot(CPUTLBEntry
*tlb_entry
, vaddr page
)
442 return tlb_hit_page_mask_anyprot(tlb_entry
, page
, -1);
446 * tlb_entry_is_empty - return true if the entry is not in use
447 * @te: pointer to CPUTLBEntry
449 static inline bool tlb_entry_is_empty(const CPUTLBEntry
*te
)
451 return te
->addr_read
== -1 && te
->addr_write
== -1 && te
->addr_code
== -1;
454 /* Called with tlb_c.lock held */
455 static bool tlb_flush_entry_mask_locked(CPUTLBEntry
*tlb_entry
,
459 if (tlb_hit_page_mask_anyprot(tlb_entry
, page
, mask
)) {
460 memset(tlb_entry
, -1, sizeof(*tlb_entry
));
466 static inline bool tlb_flush_entry_locked(CPUTLBEntry
*tlb_entry
, vaddr page
)
468 return tlb_flush_entry_mask_locked(tlb_entry
, page
, -1);
471 /* Called with tlb_c.lock held */
472 static void tlb_flush_vtlb_page_mask_locked(CPUArchState
*env
, int mmu_idx
,
476 CPUTLBDesc
*d
= &env_tlb(env
)->d
[mmu_idx
];
479 assert_cpu_is_self(env_cpu(env
));
480 for (k
= 0; k
< CPU_VTLB_SIZE
; k
++) {
481 if (tlb_flush_entry_mask_locked(&d
->vtable
[k
], page
, mask
)) {
482 tlb_n_used_entries_dec(env
, mmu_idx
);
487 static inline void tlb_flush_vtlb_page_locked(CPUArchState
*env
, int mmu_idx
,
490 tlb_flush_vtlb_page_mask_locked(env
, mmu_idx
, page
, -1);
493 static void tlb_flush_page_locked(CPUArchState
*env
, int midx
, vaddr page
)
495 vaddr lp_addr
= env_tlb(env
)->d
[midx
].large_page_addr
;
496 vaddr lp_mask
= env_tlb(env
)->d
[midx
].large_page_mask
;
498 /* Check if we need to flush due to large pages. */
499 if ((page
& lp_mask
) == lp_addr
) {
500 tlb_debug("forcing full flush midx %d (%016"
501 VADDR_PRIx
"/%016" VADDR_PRIx
")\n",
502 midx
, lp_addr
, lp_mask
);
503 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
505 if (tlb_flush_entry_locked(tlb_entry(env
, midx
, page
), page
)) {
506 tlb_n_used_entries_dec(env
, midx
);
508 tlb_flush_vtlb_page_locked(env
, midx
, page
);
513 * tlb_flush_page_by_mmuidx_async_0:
514 * @cpu: cpu on which to flush
515 * @addr: page of virtual address to flush
516 * @idxmap: set of mmu_idx to flush
518 * Helper for tlb_flush_page_by_mmuidx and friends, flush one page
519 * at @addr from the tlbs indicated by @idxmap from @cpu.
521 static void tlb_flush_page_by_mmuidx_async_0(CPUState
*cpu
,
525 CPUArchState
*env
= cpu
->env_ptr
;
528 assert_cpu_is_self(cpu
);
530 tlb_debug("page addr: %016" VADDR_PRIx
" mmu_map:0x%x\n", addr
, idxmap
);
532 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
533 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
534 if ((idxmap
>> mmu_idx
) & 1) {
535 tlb_flush_page_locked(env
, mmu_idx
, addr
);
538 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
541 * Discard jump cache entries for any tb which might potentially
542 * overlap the flushed page, which includes the previous.
544 tb_jmp_cache_clear_page(cpu
, addr
- TARGET_PAGE_SIZE
);
545 tb_jmp_cache_clear_page(cpu
, addr
);
549 * tlb_flush_page_by_mmuidx_async_1:
550 * @cpu: cpu on which to flush
551 * @data: encoded addr + idxmap
553 * Helper for tlb_flush_page_by_mmuidx and friends, called through
554 * async_run_on_cpu. The idxmap parameter is encoded in the page
555 * offset of the target_ptr field. This limits the set of mmu_idx
556 * that can be passed via this method.
558 static void tlb_flush_page_by_mmuidx_async_1(CPUState
*cpu
,
559 run_on_cpu_data data
)
561 vaddr addr_and_idxmap
= data
.target_ptr
;
562 vaddr addr
= addr_and_idxmap
& TARGET_PAGE_MASK
;
563 uint16_t idxmap
= addr_and_idxmap
& ~TARGET_PAGE_MASK
;
565 tlb_flush_page_by_mmuidx_async_0(cpu
, addr
, idxmap
);
571 } TLBFlushPageByMMUIdxData
;
574 * tlb_flush_page_by_mmuidx_async_2:
575 * @cpu: cpu on which to flush
576 * @data: allocated addr + idxmap
578 * Helper for tlb_flush_page_by_mmuidx and friends, called through
579 * async_run_on_cpu. The addr+idxmap parameters are stored in a
580 * TLBFlushPageByMMUIdxData structure that has been allocated
581 * specifically for this helper. Free the structure when done.
583 static void tlb_flush_page_by_mmuidx_async_2(CPUState
*cpu
,
584 run_on_cpu_data data
)
586 TLBFlushPageByMMUIdxData
*d
= data
.host_ptr
;
588 tlb_flush_page_by_mmuidx_async_0(cpu
, d
->addr
, d
->idxmap
);
592 void tlb_flush_page_by_mmuidx(CPUState
*cpu
, vaddr addr
, uint16_t idxmap
)
594 tlb_debug("addr: %016" VADDR_PRIx
" mmu_idx:%" PRIx16
"\n", addr
, idxmap
);
596 /* This should already be page aligned */
597 addr
&= TARGET_PAGE_MASK
;
599 if (qemu_cpu_is_self(cpu
)) {
600 tlb_flush_page_by_mmuidx_async_0(cpu
, addr
, idxmap
);
601 } else if (idxmap
< TARGET_PAGE_SIZE
) {
603 * Most targets have only a few mmu_idx. In the case where
604 * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid
605 * allocating memory for this operation.
607 async_run_on_cpu(cpu
, tlb_flush_page_by_mmuidx_async_1
,
608 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
610 TLBFlushPageByMMUIdxData
*d
= g_new(TLBFlushPageByMMUIdxData
, 1);
612 /* Otherwise allocate a structure, freed by the worker. */
615 async_run_on_cpu(cpu
, tlb_flush_page_by_mmuidx_async_2
,
616 RUN_ON_CPU_HOST_PTR(d
));
620 void tlb_flush_page(CPUState
*cpu
, vaddr addr
)
622 tlb_flush_page_by_mmuidx(cpu
, addr
, ALL_MMUIDX_BITS
);
625 void tlb_flush_page_by_mmuidx_all_cpus(CPUState
*src_cpu
, vaddr addr
,
628 tlb_debug("addr: %016" VADDR_PRIx
" mmu_idx:%"PRIx16
"\n", addr
, idxmap
);
630 /* This should already be page aligned */
631 addr
&= TARGET_PAGE_MASK
;
634 * Allocate memory to hold addr+idxmap only when needed.
635 * See tlb_flush_page_by_mmuidx for details.
637 if (idxmap
< TARGET_PAGE_SIZE
) {
638 flush_all_helper(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
639 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
643 /* Allocate a separate data block for each destination cpu. */
644 CPU_FOREACH(dst_cpu
) {
645 if (dst_cpu
!= src_cpu
) {
646 TLBFlushPageByMMUIdxData
*d
647 = g_new(TLBFlushPageByMMUIdxData
, 1);
651 async_run_on_cpu(dst_cpu
, tlb_flush_page_by_mmuidx_async_2
,
652 RUN_ON_CPU_HOST_PTR(d
));
657 tlb_flush_page_by_mmuidx_async_0(src_cpu
, addr
, idxmap
);
660 void tlb_flush_page_all_cpus(CPUState
*src
, vaddr addr
)
662 tlb_flush_page_by_mmuidx_all_cpus(src
, addr
, ALL_MMUIDX_BITS
);
665 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
669 tlb_debug("addr: %016" VADDR_PRIx
" mmu_idx:%"PRIx16
"\n", addr
, idxmap
);
671 /* This should already be page aligned */
672 addr
&= TARGET_PAGE_MASK
;
675 * Allocate memory to hold addr+idxmap only when needed.
676 * See tlb_flush_page_by_mmuidx for details.
678 if (idxmap
< TARGET_PAGE_SIZE
) {
679 flush_all_helper(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
680 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
681 async_safe_run_on_cpu(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
682 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
685 TLBFlushPageByMMUIdxData
*d
;
687 /* Allocate a separate data block for each destination cpu. */
688 CPU_FOREACH(dst_cpu
) {
689 if (dst_cpu
!= src_cpu
) {
690 d
= g_new(TLBFlushPageByMMUIdxData
, 1);
693 async_run_on_cpu(dst_cpu
, tlb_flush_page_by_mmuidx_async_2
,
694 RUN_ON_CPU_HOST_PTR(d
));
698 d
= g_new(TLBFlushPageByMMUIdxData
, 1);
701 async_safe_run_on_cpu(src_cpu
, tlb_flush_page_by_mmuidx_async_2
,
702 RUN_ON_CPU_HOST_PTR(d
));
706 void tlb_flush_page_all_cpus_synced(CPUState
*src
, vaddr addr
)
708 tlb_flush_page_by_mmuidx_all_cpus_synced(src
, addr
, ALL_MMUIDX_BITS
);
711 static void tlb_flush_range_locked(CPUArchState
*env
, int midx
,
712 vaddr addr
, vaddr len
,
715 CPUTLBDesc
*d
= &env_tlb(env
)->d
[midx
];
716 CPUTLBDescFast
*f
= &env_tlb(env
)->f
[midx
];
717 vaddr mask
= MAKE_64BIT_MASK(0, bits
);
720 * If @bits is smaller than the tlb size, there may be multiple entries
721 * within the TLB; otherwise all addresses that match under @mask hit
722 * the same TLB entry.
723 * TODO: Perhaps allow bits to be a few bits less than the size.
724 * For now, just flush the entire TLB.
726 * If @len is larger than the tlb size, then it will take longer to
727 * test all of the entries in the TLB than it will to flush it all.
729 if (mask
< f
->mask
|| len
> f
->mask
) {
730 tlb_debug("forcing full flush midx %d ("
731 "%016" VADDR_PRIx
"/%016" VADDR_PRIx
"+%016" VADDR_PRIx
")\n",
732 midx
, addr
, mask
, len
);
733 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
738 * Check if we need to flush due to large pages.
739 * Because large_page_mask contains all 1's from the msb,
740 * we only need to test the end of the range.
742 if (((addr
+ len
- 1) & d
->large_page_mask
) == d
->large_page_addr
) {
743 tlb_debug("forcing full flush midx %d ("
744 "%016" VADDR_PRIx
"/%016" VADDR_PRIx
")\n",
745 midx
, d
->large_page_addr
, d
->large_page_mask
);
746 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
750 for (vaddr i
= 0; i
< len
; i
+= TARGET_PAGE_SIZE
) {
751 vaddr page
= addr
+ i
;
752 CPUTLBEntry
*entry
= tlb_entry(env
, midx
, page
);
754 if (tlb_flush_entry_mask_locked(entry
, page
, mask
)) {
755 tlb_n_used_entries_dec(env
, midx
);
757 tlb_flush_vtlb_page_mask_locked(env
, midx
, page
, mask
);
768 static void tlb_flush_range_by_mmuidx_async_0(CPUState
*cpu
,
771 CPUArchState
*env
= cpu
->env_ptr
;
774 assert_cpu_is_self(cpu
);
776 tlb_debug("range: %016" VADDR_PRIx
"/%u+%016" VADDR_PRIx
" mmu_map:0x%x\n",
777 d
.addr
, d
.bits
, d
.len
, d
.idxmap
);
779 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
780 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
781 if ((d
.idxmap
>> mmu_idx
) & 1) {
782 tlb_flush_range_locked(env
, mmu_idx
, d
.addr
, d
.len
, d
.bits
);
785 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
788 * If the length is larger than the jump cache size, then it will take
789 * longer to clear each entry individually than it will to clear it all.
791 if (d
.len
>= (TARGET_PAGE_SIZE
* TB_JMP_CACHE_SIZE
)) {
792 tcg_flush_jmp_cache(cpu
);
797 * Discard jump cache entries for any tb which might potentially
798 * overlap the flushed pages, which includes the previous.
800 d
.addr
-= TARGET_PAGE_SIZE
;
801 for (vaddr i
= 0, n
= d
.len
/ TARGET_PAGE_SIZE
+ 1; i
< n
; i
++) {
802 tb_jmp_cache_clear_page(cpu
, d
.addr
);
803 d
.addr
+= TARGET_PAGE_SIZE
;
807 static void tlb_flush_range_by_mmuidx_async_1(CPUState
*cpu
,
808 run_on_cpu_data data
)
810 TLBFlushRangeData
*d
= data
.host_ptr
;
811 tlb_flush_range_by_mmuidx_async_0(cpu
, *d
);
815 void tlb_flush_range_by_mmuidx(CPUState
*cpu
, vaddr addr
,
816 vaddr len
, uint16_t idxmap
,
822 * If all bits are significant, and len is small,
823 * this devolves to tlb_flush_page.
825 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
826 tlb_flush_page_by_mmuidx(cpu
, addr
, idxmap
);
829 /* If no page bits are significant, this devolves to tlb_flush. */
830 if (bits
< TARGET_PAGE_BITS
) {
831 tlb_flush_by_mmuidx(cpu
, idxmap
);
835 /* This should already be page aligned */
836 d
.addr
= addr
& TARGET_PAGE_MASK
;
841 if (qemu_cpu_is_self(cpu
)) {
842 tlb_flush_range_by_mmuidx_async_0(cpu
, d
);
844 /* Otherwise allocate a structure, freed by the worker. */
845 TLBFlushRangeData
*p
= g_memdup(&d
, sizeof(d
));
846 async_run_on_cpu(cpu
, tlb_flush_range_by_mmuidx_async_1
,
847 RUN_ON_CPU_HOST_PTR(p
));
851 void tlb_flush_page_bits_by_mmuidx(CPUState
*cpu
, vaddr addr
,
852 uint16_t idxmap
, unsigned bits
)
854 tlb_flush_range_by_mmuidx(cpu
, addr
, TARGET_PAGE_SIZE
, idxmap
, bits
);
857 void tlb_flush_range_by_mmuidx_all_cpus(CPUState
*src_cpu
,
858 vaddr addr
, vaddr len
,
859 uint16_t idxmap
, unsigned bits
)
865 * If all bits are significant, and len is small,
866 * this devolves to tlb_flush_page.
868 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
869 tlb_flush_page_by_mmuidx_all_cpus(src_cpu
, addr
, idxmap
);
872 /* If no page bits are significant, this devolves to tlb_flush. */
873 if (bits
< TARGET_PAGE_BITS
) {
874 tlb_flush_by_mmuidx_all_cpus(src_cpu
, idxmap
);
878 /* This should already be page aligned */
879 d
.addr
= addr
& TARGET_PAGE_MASK
;
884 /* Allocate a separate data block for each destination cpu. */
885 CPU_FOREACH(dst_cpu
) {
886 if (dst_cpu
!= src_cpu
) {
887 TLBFlushRangeData
*p
= g_memdup(&d
, sizeof(d
));
888 async_run_on_cpu(dst_cpu
,
889 tlb_flush_range_by_mmuidx_async_1
,
890 RUN_ON_CPU_HOST_PTR(p
));
894 tlb_flush_range_by_mmuidx_async_0(src_cpu
, d
);
897 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState
*src_cpu
,
898 vaddr addr
, uint16_t idxmap
,
901 tlb_flush_range_by_mmuidx_all_cpus(src_cpu
, addr
, TARGET_PAGE_SIZE
,
905 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
911 TLBFlushRangeData d
, *p
;
915 * If all bits are significant, and len is small,
916 * this devolves to tlb_flush_page.
918 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
919 tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu
, addr
, idxmap
);
922 /* If no page bits are significant, this devolves to tlb_flush. */
923 if (bits
< TARGET_PAGE_BITS
) {
924 tlb_flush_by_mmuidx_all_cpus_synced(src_cpu
, idxmap
);
928 /* This should already be page aligned */
929 d
.addr
= addr
& TARGET_PAGE_MASK
;
934 /* Allocate a separate data block for each destination cpu. */
935 CPU_FOREACH(dst_cpu
) {
936 if (dst_cpu
!= src_cpu
) {
937 p
= g_memdup(&d
, sizeof(d
));
938 async_run_on_cpu(dst_cpu
, tlb_flush_range_by_mmuidx_async_1
,
939 RUN_ON_CPU_HOST_PTR(p
));
943 p
= g_memdup(&d
, sizeof(d
));
944 async_safe_run_on_cpu(src_cpu
, tlb_flush_range_by_mmuidx_async_1
,
945 RUN_ON_CPU_HOST_PTR(p
));
948 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
953 tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu
, addr
, TARGET_PAGE_SIZE
,
957 /* update the TLBs so that writes to code in the virtual page 'addr'
959 void tlb_protect_code(ram_addr_t ram_addr
)
961 cpu_physical_memory_test_and_clear_dirty(ram_addr
& TARGET_PAGE_MASK
,
966 /* update the TLB so that writes in physical page 'phys_addr' are no longer
967 tested for self modifying code */
968 void tlb_unprotect_code(ram_addr_t ram_addr
)
970 cpu_physical_memory_set_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
);
975 * Dirty write flag handling
977 * When the TCG code writes to a location it looks up the address in
978 * the TLB and uses that data to compute the final address. If any of
979 * the lower bits of the address are set then the slow path is forced.
980 * There are a number of reasons to do this but for normal RAM the
981 * most usual is detecting writes to code regions which may invalidate
984 * Other vCPUs might be reading their TLBs during guest execution, so we update
985 * te->addr_write with qatomic_set. We don't need to worry about this for
986 * oversized guests as MTTCG is disabled for them.
988 * Called with tlb_c.lock held.
990 static void tlb_reset_dirty_range_locked(CPUTLBEntry
*tlb_entry
,
991 uintptr_t start
, uintptr_t length
)
993 uintptr_t addr
= tlb_entry
->addr_write
;
995 if ((addr
& (TLB_INVALID_MASK
| TLB_MMIO
|
996 TLB_DISCARD_WRITE
| TLB_NOTDIRTY
)) == 0) {
997 addr
&= TARGET_PAGE_MASK
;
998 addr
+= tlb_entry
->addend
;
999 if ((addr
- start
) < length
) {
1000 #if TARGET_LONG_BITS == 32
1001 uint32_t *ptr_write
= (uint32_t *)&tlb_entry
->addr_write
;
1002 ptr_write
+= HOST_BIG_ENDIAN
;
1003 qatomic_set(ptr_write
, *ptr_write
| TLB_NOTDIRTY
);
1004 #elif TCG_OVERSIZED_GUEST
1005 tlb_entry
->addr_write
|= TLB_NOTDIRTY
;
1007 qatomic_set(&tlb_entry
->addr_write
,
1008 tlb_entry
->addr_write
| TLB_NOTDIRTY
);
1015 * Called with tlb_c.lock held.
1016 * Called only from the vCPU context, i.e. the TLB's owner thread.
1018 static inline void copy_tlb_helper_locked(CPUTLBEntry
*d
, const CPUTLBEntry
*s
)
1023 /* This is a cross vCPU call (i.e. another vCPU resetting the flags of
1025 * We must take tlb_c.lock to avoid racing with another vCPU update. The only
1026 * thing actually updated is the target TLB entry ->addr_write flags.
1028 void tlb_reset_dirty(CPUState
*cpu
, ram_addr_t start1
, ram_addr_t length
)
1035 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1036 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1038 unsigned int n
= tlb_n_entries(&env_tlb(env
)->f
[mmu_idx
]);
1040 for (i
= 0; i
< n
; i
++) {
1041 tlb_reset_dirty_range_locked(&env_tlb(env
)->f
[mmu_idx
].table
[i
],
1045 for (i
= 0; i
< CPU_VTLB_SIZE
; i
++) {
1046 tlb_reset_dirty_range_locked(&env_tlb(env
)->d
[mmu_idx
].vtable
[i
],
1050 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1053 /* Called with tlb_c.lock held */
1054 static inline void tlb_set_dirty1_locked(CPUTLBEntry
*tlb_entry
,
1057 if (tlb_entry
->addr_write
== (addr
| TLB_NOTDIRTY
)) {
1058 tlb_entry
->addr_write
= addr
;
1062 /* update the TLB corresponding to virtual page vaddr
1063 so that it is no longer dirty */
1064 void tlb_set_dirty(CPUState
*cpu
, vaddr addr
)
1066 CPUArchState
*env
= cpu
->env_ptr
;
1069 assert_cpu_is_self(cpu
);
1071 addr
&= TARGET_PAGE_MASK
;
1072 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1073 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1074 tlb_set_dirty1_locked(tlb_entry(env
, mmu_idx
, addr
), addr
);
1077 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1079 for (k
= 0; k
< CPU_VTLB_SIZE
; k
++) {
1080 tlb_set_dirty1_locked(&env_tlb(env
)->d
[mmu_idx
].vtable
[k
], addr
);
1083 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1086 /* Our TLB does not support large pages, so remember the area covered by
1087 large pages and trigger a full TLB flush if these are invalidated. */
1088 static void tlb_add_large_page(CPUArchState
*env
, int mmu_idx
,
1089 vaddr addr
, uint64_t size
)
1091 vaddr lp_addr
= env_tlb(env
)->d
[mmu_idx
].large_page_addr
;
1092 vaddr lp_mask
= ~(size
- 1);
1094 if (lp_addr
== (vaddr
)-1) {
1095 /* No previous large page. */
1098 /* Extend the existing region to include the new page.
1099 This is a compromise between unnecessary flushes and
1100 the cost of maintaining a full variable size TLB. */
1101 lp_mask
&= env_tlb(env
)->d
[mmu_idx
].large_page_mask
;
1102 while (((lp_addr
^ addr
) & lp_mask
) != 0) {
1106 env_tlb(env
)->d
[mmu_idx
].large_page_addr
= lp_addr
& lp_mask
;
1107 env_tlb(env
)->d
[mmu_idx
].large_page_mask
= lp_mask
;
1110 static inline void tlb_set_compare(CPUTLBEntryFull
*full
, CPUTLBEntry
*ent
,
1111 target_ulong address
, int flags
,
1112 MMUAccessType access_type
, bool enable
)
1115 address
|= flags
& TLB_FLAGS_MASK
;
1116 flags
&= TLB_SLOW_FLAGS_MASK
;
1118 address
|= TLB_FORCE_SLOW
;
1124 ent
->addr_idx
[access_type
] = address
;
1125 full
->slow_flags
[access_type
] = flags
;
1129 * Add a new TLB entry. At most one entry for a given virtual address
1130 * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
1131 * supplied size is only used by tlb_flush_page.
1133 * Called from TCG-generated code, which is under an RCU read-side
1136 void tlb_set_page_full(CPUState
*cpu
, int mmu_idx
,
1137 vaddr addr
, CPUTLBEntryFull
*full
)
1139 CPUArchState
*env
= cpu
->env_ptr
;
1140 CPUTLB
*tlb
= env_tlb(env
);
1141 CPUTLBDesc
*desc
= &tlb
->d
[mmu_idx
];
1142 MemoryRegionSection
*section
;
1143 unsigned int index
, read_flags
, write_flags
;
1145 CPUTLBEntry
*te
, tn
;
1146 hwaddr iotlb
, xlat
, sz
, paddr_page
;
1148 int asidx
, wp_flags
, prot
;
1149 bool is_ram
, is_romd
;
1151 assert_cpu_is_self(cpu
);
1153 if (full
->lg_page_size
<= TARGET_PAGE_BITS
) {
1154 sz
= TARGET_PAGE_SIZE
;
1156 sz
= (hwaddr
)1 << full
->lg_page_size
;
1157 tlb_add_large_page(env
, mmu_idx
, addr
, sz
);
1159 addr_page
= addr
& TARGET_PAGE_MASK
;
1160 paddr_page
= full
->phys_addr
& TARGET_PAGE_MASK
;
1163 asidx
= cpu_asidx_from_attrs(cpu
, full
->attrs
);
1164 section
= address_space_translate_for_iotlb(cpu
, asidx
, paddr_page
,
1165 &xlat
, &sz
, full
->attrs
, &prot
);
1166 assert(sz
>= TARGET_PAGE_SIZE
);
1168 tlb_debug("vaddr=%016" VADDR_PRIx
" paddr=0x" HWADDR_FMT_plx
1169 " prot=%x idx=%d\n",
1170 addr
, full
->phys_addr
, prot
, mmu_idx
);
1173 if (full
->lg_page_size
< TARGET_PAGE_BITS
) {
1174 /* Repeat the MMU check and TLB fill on every access. */
1175 read_flags
|= TLB_INVALID_MASK
;
1177 if (full
->attrs
.byte_swap
) {
1178 read_flags
|= TLB_BSWAP
;
1181 is_ram
= memory_region_is_ram(section
->mr
);
1182 is_romd
= memory_region_is_romd(section
->mr
);
1184 if (is_ram
|| is_romd
) {
1185 /* RAM and ROMD both have associated host memory. */
1186 addend
= (uintptr_t)memory_region_get_ram_ptr(section
->mr
) + xlat
;
1188 /* I/O does not; force the host address to NULL. */
1192 write_flags
= read_flags
;
1194 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1196 * Computing is_clean is expensive; avoid all that unless
1197 * the page is actually writable.
1199 if (prot
& PAGE_WRITE
) {
1200 if (section
->readonly
) {
1201 write_flags
|= TLB_DISCARD_WRITE
;
1202 } else if (cpu_physical_memory_is_clean(iotlb
)) {
1203 write_flags
|= TLB_NOTDIRTY
;
1208 iotlb
= memory_region_section_get_iotlb(cpu
, section
) + xlat
;
1210 * Writes to romd devices must go through MMIO to enable write.
1211 * Reads to romd devices go through the ram_ptr found above,
1212 * but of course reads to I/O must go through MMIO.
1214 write_flags
|= TLB_MMIO
;
1216 read_flags
= write_flags
;
1220 wp_flags
= cpu_watchpoint_address_matches(cpu
, addr_page
,
1223 index
= tlb_index(env
, mmu_idx
, addr_page
);
1224 te
= tlb_entry(env
, mmu_idx
, addr_page
);
1227 * Hold the TLB lock for the rest of the function. We could acquire/release
1228 * the lock several times in the function, but it is faster to amortize the
1229 * acquisition cost by acquiring it just once. Note that this leads to
1230 * a longer critical section, but this is not a concern since the TLB lock
1231 * is unlikely to be contended.
1233 qemu_spin_lock(&tlb
->c
.lock
);
1235 /* Note that the tlb is no longer clean. */
1236 tlb
->c
.dirty
|= 1 << mmu_idx
;
1238 /* Make sure there's no cached translation for the new page. */
1239 tlb_flush_vtlb_page_locked(env
, mmu_idx
, addr_page
);
1242 * Only evict the old entry to the victim tlb if it's for a
1243 * different page; otherwise just overwrite the stale data.
1245 if (!tlb_hit_page_anyprot(te
, addr_page
) && !tlb_entry_is_empty(te
)) {
1246 unsigned vidx
= desc
->vindex
++ % CPU_VTLB_SIZE
;
1247 CPUTLBEntry
*tv
= &desc
->vtable
[vidx
];
1249 /* Evict the old entry into the victim tlb. */
1250 copy_tlb_helper_locked(tv
, te
);
1251 desc
->vfulltlb
[vidx
] = desc
->fulltlb
[index
];
1252 tlb_n_used_entries_dec(env
, mmu_idx
);
1255 /* refill the tlb */
1257 * At this point iotlb contains a physical section number in the lower
1258 * TARGET_PAGE_BITS, and either
1259 * + the ram_addr_t of the page base of the target RAM (RAM)
1260 * + the offset within section->mr of the page base (I/O, ROMD)
1261 * We subtract addr_page (which is page aligned and thus won't
1262 * disturb the low bits) to give an offset which can be added to the
1263 * (non-page-aligned) vaddr of the eventual memory access to get
1264 * the MemoryRegion offset for the access. Note that the vaddr we
1265 * subtract here is that of the page base, and not the same as the
1266 * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
1268 desc
->fulltlb
[index
] = *full
;
1269 full
= &desc
->fulltlb
[index
];
1270 full
->xlat_section
= iotlb
- addr_page
;
1271 full
->phys_addr
= paddr_page
;
1273 /* Now calculate the new entry */
1274 tn
.addend
= addend
- addr_page
;
1276 tlb_set_compare(full
, &tn
, addr_page
, read_flags
,
1277 MMU_INST_FETCH
, prot
& PAGE_EXEC
);
1279 if (wp_flags
& BP_MEM_READ
) {
1280 read_flags
|= TLB_WATCHPOINT
;
1282 tlb_set_compare(full
, &tn
, addr_page
, read_flags
,
1283 MMU_DATA_LOAD
, prot
& PAGE_READ
);
1285 if (prot
& PAGE_WRITE_INV
) {
1286 write_flags
|= TLB_INVALID_MASK
;
1288 if (wp_flags
& BP_MEM_WRITE
) {
1289 write_flags
|= TLB_WATCHPOINT
;
1291 tlb_set_compare(full
, &tn
, addr_page
, write_flags
,
1292 MMU_DATA_STORE
, prot
& PAGE_WRITE
);
1294 copy_tlb_helper_locked(te
, &tn
);
1295 tlb_n_used_entries_inc(env
, mmu_idx
);
1296 qemu_spin_unlock(&tlb
->c
.lock
);
1299 void tlb_set_page_with_attrs(CPUState
*cpu
, vaddr addr
,
1300 hwaddr paddr
, MemTxAttrs attrs
, int prot
,
1301 int mmu_idx
, uint64_t size
)
1303 CPUTLBEntryFull full
= {
1307 .lg_page_size
= ctz64(size
)
1310 assert(is_power_of_2(size
));
1311 tlb_set_page_full(cpu
, mmu_idx
, addr
, &full
);
1314 void tlb_set_page(CPUState
*cpu
, vaddr addr
,
1315 hwaddr paddr
, int prot
,
1316 int mmu_idx
, uint64_t size
)
1318 tlb_set_page_with_attrs(cpu
, addr
, paddr
, MEMTXATTRS_UNSPECIFIED
,
1319 prot
, mmu_idx
, size
);
1323 * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
1324 * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
1325 * be discarded and looked up again (e.g. via tlb_entry()).
1327 static void tlb_fill(CPUState
*cpu
, vaddr addr
, int size
,
1328 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
1333 * This is not a probe, so only valid return is success; failure
1334 * should result in exception + longjmp to the cpu loop.
1336 ok
= cpu
->cc
->tcg_ops
->tlb_fill(cpu
, addr
, size
,
1337 access_type
, mmu_idx
, false, retaddr
);
1341 static inline void cpu_unaligned_access(CPUState
*cpu
, vaddr addr
,
1342 MMUAccessType access_type
,
1343 int mmu_idx
, uintptr_t retaddr
)
1345 cpu
->cc
->tcg_ops
->do_unaligned_access(cpu
, addr
, access_type
,
1349 static inline void cpu_transaction_failed(CPUState
*cpu
, hwaddr physaddr
,
1350 vaddr addr
, unsigned size
,
1351 MMUAccessType access_type
,
1352 int mmu_idx
, MemTxAttrs attrs
,
1353 MemTxResult response
,
1356 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
1358 if (!cpu
->ignore_memory_transaction_failures
&&
1359 cc
->tcg_ops
->do_transaction_failed
) {
1360 cc
->tcg_ops
->do_transaction_failed(cpu
, physaddr
, addr
, size
,
1361 access_type
, mmu_idx
, attrs
,
1367 * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin.
1368 * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
1369 * because of the side effect of io_writex changing memory layout.
1371 static void save_iotlb_data(CPUState
*cs
, MemoryRegionSection
*section
,
1374 #ifdef CONFIG_PLUGIN
1375 SavedIOTLB
*saved
= &cs
->saved_iotlb
;
1376 saved
->section
= section
;
1377 saved
->mr_offset
= mr_offset
;
1381 static uint64_t io_readx(CPUArchState
*env
, CPUTLBEntryFull
*full
,
1382 int mmu_idx
, vaddr addr
, uintptr_t retaddr
,
1383 MMUAccessType access_type
, MemOp op
)
1385 CPUState
*cpu
= env_cpu(env
);
1387 MemoryRegionSection
*section
;
1392 section
= iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1394 mr_offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1395 cpu
->mem_io_pc
= retaddr
;
1396 if (!cpu
->can_do_io
) {
1397 cpu_io_recompile(cpu
, retaddr
);
1401 * The memory_region_dispatch may trigger a flush/resize
1402 * so for plugins we save the iotlb_data just in case.
1404 save_iotlb_data(cpu
, section
, mr_offset
);
1407 QEMU_IOTHREAD_LOCK_GUARD();
1408 r
= memory_region_dispatch_read(mr
, mr_offset
, &val
, op
, full
->attrs
);
1411 if (r
!= MEMTX_OK
) {
1412 hwaddr physaddr
= mr_offset
+
1413 section
->offset_within_address_space
-
1414 section
->offset_within_region
;
1416 cpu_transaction_failed(cpu
, physaddr
, addr
, memop_size(op
), access_type
,
1417 mmu_idx
, full
->attrs
, r
, retaddr
);
1422 static void io_writex(CPUArchState
*env
, CPUTLBEntryFull
*full
,
1423 int mmu_idx
, uint64_t val
, vaddr addr
,
1424 uintptr_t retaddr
, MemOp op
)
1426 CPUState
*cpu
= env_cpu(env
);
1428 MemoryRegionSection
*section
;
1432 section
= iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1434 mr_offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1435 if (!cpu
->can_do_io
) {
1436 cpu_io_recompile(cpu
, retaddr
);
1438 cpu
->mem_io_pc
= retaddr
;
1441 * The memory_region_dispatch may trigger a flush/resize
1442 * so for plugins we save the iotlb_data just in case.
1444 save_iotlb_data(cpu
, section
, mr_offset
);
1447 QEMU_IOTHREAD_LOCK_GUARD();
1448 r
= memory_region_dispatch_write(mr
, mr_offset
, val
, op
, full
->attrs
);
1451 if (r
!= MEMTX_OK
) {
1452 hwaddr physaddr
= mr_offset
+
1453 section
->offset_within_address_space
-
1454 section
->offset_within_region
;
1456 cpu_transaction_failed(cpu
, physaddr
, addr
, memop_size(op
),
1457 MMU_DATA_STORE
, mmu_idx
, full
->attrs
, r
,
1462 /* Return true if ADDR is present in the victim tlb, and has been copied
1463 back to the main tlb. */
1464 static bool victim_tlb_hit(CPUArchState
*env
, size_t mmu_idx
, size_t index
,
1465 MMUAccessType access_type
, vaddr page
)
1469 assert_cpu_is_self(env_cpu(env
));
1470 for (vidx
= 0; vidx
< CPU_VTLB_SIZE
; ++vidx
) {
1471 CPUTLBEntry
*vtlb
= &env_tlb(env
)->d
[mmu_idx
].vtable
[vidx
];
1472 uint64_t cmp
= tlb_read_idx(vtlb
, access_type
);
1475 /* Found entry in victim tlb, swap tlb and iotlb. */
1476 CPUTLBEntry tmptlb
, *tlb
= &env_tlb(env
)->f
[mmu_idx
].table
[index
];
1478 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1479 copy_tlb_helper_locked(&tmptlb
, tlb
);
1480 copy_tlb_helper_locked(tlb
, vtlb
);
1481 copy_tlb_helper_locked(vtlb
, &tmptlb
);
1482 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1484 CPUTLBEntryFull
*f1
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1485 CPUTLBEntryFull
*f2
= &env_tlb(env
)->d
[mmu_idx
].vfulltlb
[vidx
];
1486 CPUTLBEntryFull tmpf
;
1487 tmpf
= *f1
; *f1
= *f2
; *f2
= tmpf
;
1494 static void notdirty_write(CPUState
*cpu
, vaddr mem_vaddr
, unsigned size
,
1495 CPUTLBEntryFull
*full
, uintptr_t retaddr
)
1497 ram_addr_t ram_addr
= mem_vaddr
+ full
->xlat_section
;
1499 trace_memory_notdirty_write_access(mem_vaddr
, ram_addr
, size
);
1501 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
1502 tb_invalidate_phys_range_fast(ram_addr
, size
, retaddr
);
1506 * Set both VGA and migration bits for simplicity and to remove
1507 * the notdirty callback faster.
1509 cpu_physical_memory_set_dirty_range(ram_addr
, size
, DIRTY_CLIENTS_NOCODE
);
1511 /* We remove the notdirty callback only if the code has been flushed. */
1512 if (!cpu_physical_memory_is_clean(ram_addr
)) {
1513 trace_memory_notdirty_set_dirty(mem_vaddr
);
1514 tlb_set_dirty(cpu
, mem_vaddr
);
1518 static int probe_access_internal(CPUArchState
*env
, vaddr addr
,
1519 int fault_size
, MMUAccessType access_type
,
1520 int mmu_idx
, bool nonfault
,
1521 void **phost
, CPUTLBEntryFull
**pfull
,
1522 uintptr_t retaddr
, bool check_mem_cbs
)
1524 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1525 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
1526 uint64_t tlb_addr
= tlb_read_idx(entry
, access_type
);
1527 vaddr page_addr
= addr
& TARGET_PAGE_MASK
;
1528 int flags
= TLB_FLAGS_MASK
& ~TLB_FORCE_SLOW
;
1529 bool force_mmio
= check_mem_cbs
&& cpu_plugin_mem_cbs_enabled(env_cpu(env
));
1530 CPUTLBEntryFull
*full
;
1532 if (!tlb_hit_page(tlb_addr
, page_addr
)) {
1533 if (!victim_tlb_hit(env
, mmu_idx
, index
, access_type
, page_addr
)) {
1534 CPUState
*cs
= env_cpu(env
);
1536 if (!cs
->cc
->tcg_ops
->tlb_fill(cs
, addr
, fault_size
, access_type
,
1537 mmu_idx
, nonfault
, retaddr
)) {
1538 /* Non-faulting page table read failed. */
1541 return TLB_INVALID_MASK
;
1544 /* TLB resize via tlb_fill may have moved the entry. */
1545 index
= tlb_index(env
, mmu_idx
, addr
);
1546 entry
= tlb_entry(env
, mmu_idx
, addr
);
1549 * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
1550 * to force the next access through tlb_fill. We've just
1551 * called tlb_fill, so we know that this entry *is* valid.
1553 flags
&= ~TLB_INVALID_MASK
;
1555 tlb_addr
= tlb_read_idx(entry
, access_type
);
1559 *pfull
= full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1560 flags
|= full
->slow_flags
[access_type
];
1562 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
1563 if (unlikely(flags
& ~(TLB_WATCHPOINT
| TLB_NOTDIRTY
))
1565 (access_type
!= MMU_INST_FETCH
&& force_mmio
)) {
1570 /* Everything else is RAM. */
1571 *phost
= (void *)((uintptr_t)addr
+ entry
->addend
);
1575 int probe_access_full(CPUArchState
*env
, vaddr addr
, int size
,
1576 MMUAccessType access_type
, int mmu_idx
,
1577 bool nonfault
, void **phost
, CPUTLBEntryFull
**pfull
,
1580 int flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1581 nonfault
, phost
, pfull
, retaddr
, true);
1583 /* Handle clean RAM pages. */
1584 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1585 notdirty_write(env_cpu(env
), addr
, 1, *pfull
, retaddr
);
1586 flags
&= ~TLB_NOTDIRTY
;
1592 int probe_access_full_mmu(CPUArchState
*env
, vaddr addr
, int size
,
1593 MMUAccessType access_type
, int mmu_idx
,
1594 void **phost
, CPUTLBEntryFull
**pfull
)
1596 void *discard_phost
;
1597 CPUTLBEntryFull
*discard_tlb
;
1599 /* privately handle users that don't need full results */
1600 phost
= phost
? phost
: &discard_phost
;
1601 pfull
= pfull
? pfull
: &discard_tlb
;
1603 int flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1604 true, phost
, pfull
, 0, false);
1606 /* Handle clean RAM pages. */
1607 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1608 notdirty_write(env_cpu(env
), addr
, 1, *pfull
, 0);
1609 flags
&= ~TLB_NOTDIRTY
;
1615 int probe_access_flags(CPUArchState
*env
, vaddr addr
, int size
,
1616 MMUAccessType access_type
, int mmu_idx
,
1617 bool nonfault
, void **phost
, uintptr_t retaddr
)
1619 CPUTLBEntryFull
*full
;
1622 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
1624 flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1625 nonfault
, phost
, &full
, retaddr
, true);
1627 /* Handle clean RAM pages. */
1628 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1629 notdirty_write(env_cpu(env
), addr
, 1, full
, retaddr
);
1630 flags
&= ~TLB_NOTDIRTY
;
1636 void *probe_access(CPUArchState
*env
, vaddr addr
, int size
,
1637 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
1639 CPUTLBEntryFull
*full
;
1643 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
1645 flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1646 false, &host
, &full
, retaddr
, true);
1648 /* Per the interface, size == 0 merely faults the access. */
1653 if (unlikely(flags
& (TLB_NOTDIRTY
| TLB_WATCHPOINT
))) {
1654 /* Handle watchpoints. */
1655 if (flags
& TLB_WATCHPOINT
) {
1656 int wp_access
= (access_type
== MMU_DATA_STORE
1657 ? BP_MEM_WRITE
: BP_MEM_READ
);
1658 cpu_check_watchpoint(env_cpu(env
), addr
, size
,
1659 full
->attrs
, wp_access
, retaddr
);
1662 /* Handle clean RAM pages. */
1663 if (flags
& TLB_NOTDIRTY
) {
1664 notdirty_write(env_cpu(env
), addr
, 1, full
, retaddr
);
1671 void *tlb_vaddr_to_host(CPUArchState
*env
, abi_ptr addr
,
1672 MMUAccessType access_type
, int mmu_idx
)
1674 CPUTLBEntryFull
*full
;
1678 flags
= probe_access_internal(env
, addr
, 0, access_type
,
1679 mmu_idx
, true, &host
, &full
, 0, false);
1681 /* No combination of flags are expected by the caller. */
1682 return flags
? NULL
: host
;
1686 * Return a ram_addr_t for the virtual address for execution.
1688 * Return -1 if we can't translate and execute from an entire page
1689 * of RAM. This will force us to execute by loading and translating
1690 * one insn at a time, without caching.
1692 * NOTE: This function will trigger an exception if the page is
1695 tb_page_addr_t
get_page_addr_code_hostp(CPUArchState
*env
, vaddr addr
,
1698 CPUTLBEntryFull
*full
;
1701 (void)probe_access_internal(env
, addr
, 1, MMU_INST_FETCH
,
1702 cpu_mmu_index(env
, true), false,
1703 &p
, &full
, 0, false);
1708 if (full
->lg_page_size
< TARGET_PAGE_BITS
) {
1715 return qemu_ram_addr_from_host_nofail(p
);
1718 /* Load/store with atomicity primitives. */
1719 #include "ldst_atomicity.c.inc"
1721 #ifdef CONFIG_PLUGIN
1723 * Perform a TLB lookup and populate the qemu_plugin_hwaddr structure.
1724 * This should be a hot path as we will have just looked this path up
1725 * in the softmmu lookup code (or helper). We don't handle re-fills or
1726 * checking the victim table. This is purely informational.
1728 * This almost never fails as the memory access being instrumented
1729 * should have just filled the TLB. The one corner case is io_writex
1730 * which can cause TLB flushes and potential resizing of the TLBs
1731 * losing the information we need. In those cases we need to recover
1732 * data from a copy of the CPUTLBEntryFull. As long as this always occurs
1733 * from the same thread (which a mem callback will be) this is safe.
1736 bool tlb_plugin_lookup(CPUState
*cpu
, vaddr addr
, int mmu_idx
,
1737 bool is_store
, struct qemu_plugin_hwaddr
*data
)
1739 CPUArchState
*env
= cpu
->env_ptr
;
1740 CPUTLBEntry
*tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1741 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1742 uint64_t tlb_addr
= is_store
? tlb_addr_write(tlbe
) : tlbe
->addr_read
;
1744 if (likely(tlb_hit(tlb_addr
, addr
))) {
1745 /* We must have an iotlb entry for MMIO */
1746 if (tlb_addr
& TLB_MMIO
) {
1747 CPUTLBEntryFull
*full
;
1748 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1750 data
->v
.io
.section
=
1751 iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1752 data
->v
.io
.offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1754 data
->is_io
= false;
1755 data
->v
.ram
.hostaddr
= (void *)((uintptr_t)addr
+ tlbe
->addend
);
1759 SavedIOTLB
*saved
= &cpu
->saved_iotlb
;
1761 data
->v
.io
.section
= saved
->section
;
1762 data
->v
.io
.offset
= saved
->mr_offset
;
1770 * Probe for a load/store operation.
1771 * Return the host address and into @flags.
1774 typedef struct MMULookupPageData
{
1775 CPUTLBEntryFull
*full
;
1780 } MMULookupPageData
;
1782 typedef struct MMULookupLocals
{
1783 MMULookupPageData page
[2];
1789 * mmu_lookup1: translate one page
1791 * @data: lookup parameters
1792 * @mmu_idx: virtual address context
1793 * @access_type: load/store/code
1794 * @ra: return address into tcg generated code, or 0
1796 * Resolve the translation for the one page at @data.addr, filling in
1797 * the rest of @data with the results. If the translation fails,
1798 * tlb_fill will longjmp out. Return true if the softmmu tlb for
1799 * @mmu_idx may have resized.
1801 static bool mmu_lookup1(CPUArchState
*env
, MMULookupPageData
*data
,
1802 int mmu_idx
, MMUAccessType access_type
, uintptr_t ra
)
1804 vaddr addr
= data
->addr
;
1805 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1806 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
1807 uint64_t tlb_addr
= tlb_read_idx(entry
, access_type
);
1808 bool maybe_resized
= false;
1809 CPUTLBEntryFull
*full
;
1812 /* If the TLB entry is for a different page, reload and try again. */
1813 if (!tlb_hit(tlb_addr
, addr
)) {
1814 if (!victim_tlb_hit(env
, mmu_idx
, index
, access_type
,
1815 addr
& TARGET_PAGE_MASK
)) {
1816 tlb_fill(env_cpu(env
), addr
, data
->size
, access_type
, mmu_idx
, ra
);
1817 maybe_resized
= true;
1818 index
= tlb_index(env
, mmu_idx
, addr
);
1819 entry
= tlb_entry(env
, mmu_idx
, addr
);
1821 tlb_addr
= tlb_read_idx(entry
, access_type
) & ~TLB_INVALID_MASK
;
1824 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1825 flags
= tlb_addr
& (TLB_FLAGS_MASK
& ~TLB_FORCE_SLOW
);
1826 flags
|= full
->slow_flags
[access_type
];
1829 data
->flags
= flags
;
1830 /* Compute haddr speculatively; depending on flags it might be invalid. */
1831 data
->haddr
= (void *)((uintptr_t)addr
+ entry
->addend
);
1833 return maybe_resized
;
1837 * mmu_watch_or_dirty
1839 * @data: lookup parameters
1840 * @access_type: load/store/code
1841 * @ra: return address into tcg generated code, or 0
1843 * Trigger watchpoints for @data.addr:@data.size;
1844 * record writes to protected clean pages.
1846 static void mmu_watch_or_dirty(CPUArchState
*env
, MMULookupPageData
*data
,
1847 MMUAccessType access_type
, uintptr_t ra
)
1849 CPUTLBEntryFull
*full
= data
->full
;
1850 vaddr addr
= data
->addr
;
1851 int flags
= data
->flags
;
1852 int size
= data
->size
;
1854 /* On watchpoint hit, this will longjmp out. */
1855 if (flags
& TLB_WATCHPOINT
) {
1856 int wp
= access_type
== MMU_DATA_STORE
? BP_MEM_WRITE
: BP_MEM_READ
;
1857 cpu_check_watchpoint(env_cpu(env
), addr
, size
, full
->attrs
, wp
, ra
);
1858 flags
&= ~TLB_WATCHPOINT
;
1861 /* Note that notdirty is only set for writes. */
1862 if (flags
& TLB_NOTDIRTY
) {
1863 notdirty_write(env_cpu(env
), addr
, size
, full
, ra
);
1864 flags
&= ~TLB_NOTDIRTY
;
1866 data
->flags
= flags
;
1870 * mmu_lookup: translate page(s)
1872 * @addr: virtual address
1873 * @oi: combined mmu_idx and MemOp
1874 * @ra: return address into tcg generated code, or 0
1875 * @access_type: load/store/code
1878 * Resolve the translation for the page(s) beginning at @addr, for MemOp.size
1879 * bytes. Return true if the lookup crosses a page boundary.
1881 static bool mmu_lookup(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
1882 uintptr_t ra
, MMUAccessType type
, MMULookupLocals
*l
)
1888 l
->memop
= get_memop(oi
);
1889 l
->mmu_idx
= get_mmuidx(oi
);
1891 tcg_debug_assert(l
->mmu_idx
< NB_MMU_MODES
);
1893 /* Handle CPU specific unaligned behaviour */
1894 a_bits
= get_alignment_bits(l
->memop
);
1895 if (addr
& ((1 << a_bits
) - 1)) {
1896 cpu_unaligned_access(env_cpu(env
), addr
, type
, l
->mmu_idx
, ra
);
1899 l
->page
[0].addr
= addr
;
1900 l
->page
[0].size
= memop_size(l
->memop
);
1901 l
->page
[1].addr
= (addr
+ l
->page
[0].size
- 1) & TARGET_PAGE_MASK
;
1902 l
->page
[1].size
= 0;
1903 crosspage
= (addr
^ l
->page
[1].addr
) & TARGET_PAGE_MASK
;
1905 if (likely(!crosspage
)) {
1906 mmu_lookup1(env
, &l
->page
[0], l
->mmu_idx
, type
, ra
);
1908 flags
= l
->page
[0].flags
;
1909 if (unlikely(flags
& (TLB_WATCHPOINT
| TLB_NOTDIRTY
))) {
1910 mmu_watch_or_dirty(env
, &l
->page
[0], type
, ra
);
1912 if (unlikely(flags
& TLB_BSWAP
)) {
1913 l
->memop
^= MO_BSWAP
;
1916 /* Finish compute of page crossing. */
1917 int size0
= l
->page
[1].addr
- addr
;
1918 l
->page
[1].size
= l
->page
[0].size
- size0
;
1919 l
->page
[0].size
= size0
;
1922 * Lookup both pages, recognizing exceptions from either. If the
1923 * second lookup potentially resized, refresh first CPUTLBEntryFull.
1925 mmu_lookup1(env
, &l
->page
[0], l
->mmu_idx
, type
, ra
);
1926 if (mmu_lookup1(env
, &l
->page
[1], l
->mmu_idx
, type
, ra
)) {
1927 uintptr_t index
= tlb_index(env
, l
->mmu_idx
, addr
);
1928 l
->page
[0].full
= &env_tlb(env
)->d
[l
->mmu_idx
].fulltlb
[index
];
1931 flags
= l
->page
[0].flags
| l
->page
[1].flags
;
1932 if (unlikely(flags
& (TLB_WATCHPOINT
| TLB_NOTDIRTY
))) {
1933 mmu_watch_or_dirty(env
, &l
->page
[0], type
, ra
);
1934 mmu_watch_or_dirty(env
, &l
->page
[1], type
, ra
);
1938 * Since target/sparc is the only user of TLB_BSWAP, and all
1939 * Sparc accesses are aligned, any treatment across two pages
1940 * would be arbitrary. Refuse it until there's a use.
1942 tcg_debug_assert((flags
& TLB_BSWAP
) == 0);
1949 * Probe for an atomic operation. Do not allow unaligned operations,
1950 * or io operations to proceed. Return the host address.
1952 static void *atomic_mmu_lookup(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
1953 int size
, uintptr_t retaddr
)
1955 uintptr_t mmu_idx
= get_mmuidx(oi
);
1956 MemOp mop
= get_memop(oi
);
1957 int a_bits
= get_alignment_bits(mop
);
1962 CPUTLBEntryFull
*full
;
1964 tcg_debug_assert(mmu_idx
< NB_MMU_MODES
);
1966 /* Adjust the given return address. */
1967 retaddr
-= GETPC_ADJ
;
1969 /* Enforce guest required alignment. */
1970 if (unlikely(a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)))) {
1971 /* ??? Maybe indicate atomic op to cpu_unaligned_access */
1972 cpu_unaligned_access(env_cpu(env
), addr
, MMU_DATA_STORE
,
1976 /* Enforce qemu required alignment. */
1977 if (unlikely(addr
& (size
- 1))) {
1978 /* We get here if guest alignment was not requested,
1979 or was not enforced by cpu_unaligned_access above.
1980 We might widen the access and emulate, but for now
1981 mark an exception and exit the cpu loop. */
1982 goto stop_the_world
;
1985 index
= tlb_index(env
, mmu_idx
, addr
);
1986 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1988 /* Check TLB entry and enforce page permissions. */
1989 tlb_addr
= tlb_addr_write(tlbe
);
1990 if (!tlb_hit(tlb_addr
, addr
)) {
1991 if (!victim_tlb_hit(env
, mmu_idx
, index
, MMU_DATA_STORE
,
1992 addr
& TARGET_PAGE_MASK
)) {
1993 tlb_fill(env_cpu(env
), addr
, size
,
1994 MMU_DATA_STORE
, mmu_idx
, retaddr
);
1995 index
= tlb_index(env
, mmu_idx
, addr
);
1996 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1998 tlb_addr
= tlb_addr_write(tlbe
) & ~TLB_INVALID_MASK
;
2002 * Let the guest notice RMW on a write-only page.
2003 * We have just verified that the page is writable.
2004 * Subpage lookups may have left TLB_INVALID_MASK set,
2005 * but addr_read will only be -1 if PAGE_READ was unset.
2007 if (unlikely(tlbe
->addr_read
== -1)) {
2008 tlb_fill(env_cpu(env
), addr
, size
, MMU_DATA_LOAD
, mmu_idx
, retaddr
);
2010 * Since we don't support reads and writes to different
2011 * addresses, and we do have the proper page loaded for
2012 * write, this shouldn't ever return. But just in case,
2013 * handle via stop-the-world.
2015 goto stop_the_world
;
2017 /* Collect tlb flags for read. */
2018 tlb_addr
|= tlbe
->addr_read
;
2020 /* Notice an IO access or a needs-MMU-lookup access */
2021 if (unlikely(tlb_addr
& (TLB_MMIO
| TLB_DISCARD_WRITE
))) {
2022 /* There's really nothing that can be done to
2023 support this apart from stop-the-world. */
2024 goto stop_the_world
;
2027 hostaddr
= (void *)((uintptr_t)addr
+ tlbe
->addend
);
2028 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
2030 if (unlikely(tlb_addr
& TLB_NOTDIRTY
)) {
2031 notdirty_write(env_cpu(env
), addr
, size
, full
, retaddr
);
2034 if (unlikely(tlb_addr
& TLB_FORCE_SLOW
)) {
2037 if (full
->slow_flags
[MMU_DATA_STORE
] & TLB_WATCHPOINT
) {
2038 wp_flags
|= BP_MEM_WRITE
;
2040 if (full
->slow_flags
[MMU_DATA_LOAD
] & TLB_WATCHPOINT
) {
2041 wp_flags
|= BP_MEM_READ
;
2044 cpu_check_watchpoint(env_cpu(env
), addr
, size
,
2045 full
->attrs
, wp_flags
, retaddr
);
2052 cpu_loop_exit_atomic(env_cpu(env
), retaddr
);
2058 * We support two different access types. SOFTMMU_CODE_ACCESS is
2059 * specifically for reading instructions from system memory. It is
2060 * called by the translation loop and in some helpers where the code
2061 * is disassembled. It shouldn't be called directly by guest code.
2063 * For the benefit of TCG generated code, we want to avoid the
2064 * complication of ABI-specific return type promotion and always
2065 * return a value extended to the register size of the host. This is
2066 * tcg_target_long, except in the case of a 32-bit host and 64-bit
2067 * data, and for that we always have uint64_t.
2069 * We don't bother with this widened value for SOFTMMU_CODE_ACCESS.
2075 * @full: page parameters
2076 * @ret_be: accumulated data
2077 * @addr: virtual address
2078 * @size: number of bytes
2079 * @mmu_idx: virtual address context
2080 * @ra: return address into tcg generated code, or 0
2081 * Context: iothread lock held
2083 * Load @size bytes from @addr, which is memory-mapped i/o.
2084 * The bytes are concatenated in big-endian order with @ret_be.
2086 static uint64_t do_ld_mmio_beN(CPUArchState
*env
, CPUTLBEntryFull
*full
,
2087 uint64_t ret_be
, vaddr addr
, int size
,
2088 int mmu_idx
, MMUAccessType type
, uintptr_t ra
)
2092 tcg_debug_assert(size
> 0 && size
<= 8);
2094 /* Read aligned pieces up to 8 bytes. */
2095 switch ((size
| (int)addr
) & 7) {
2100 t
= io_readx(env
, full
, mmu_idx
, addr
, ra
, type
, MO_UB
);
2101 ret_be
= (ret_be
<< 8) | t
;
2107 t
= io_readx(env
, full
, mmu_idx
, addr
, ra
, type
, MO_BEUW
);
2108 ret_be
= (ret_be
<< 16) | t
;
2113 t
= io_readx(env
, full
, mmu_idx
, addr
, ra
, type
, MO_BEUL
);
2114 ret_be
= (ret_be
<< 32) | t
;
2119 return io_readx(env
, full
, mmu_idx
, addr
, ra
, type
, MO_BEUQ
);
2121 qemu_build_not_reached();
2129 * @p: translation parameters
2130 * @ret_be: accumulated data
2132 * Load @p->size bytes from @p->haddr, which is RAM.
2133 * The bytes to concatenated in big-endian order with @ret_be.
2135 static uint64_t do_ld_bytes_beN(MMULookupPageData
*p
, uint64_t ret_be
)
2137 uint8_t *haddr
= p
->haddr
;
2138 int i
, size
= p
->size
;
2140 for (i
= 0; i
< size
; i
++) {
2141 ret_be
= (ret_be
<< 8) | haddr
[i
];
2148 * @p: translation parameters
2149 * @ret_be: accumulated data
2151 * As do_ld_bytes_beN, but atomically on each aligned part.
2153 static uint64_t do_ld_parts_beN(MMULookupPageData
*p
, uint64_t ret_be
)
2155 void *haddr
= p
->haddr
;
2163 * Find minimum of alignment and size.
2164 * This is slightly stronger than required by MO_ATOM_SUBALIGN, which
2165 * would have only checked the low bits of addr|size once at the start,
2166 * but is just as easy.
2168 switch (((uintptr_t)haddr
| size
) & 7) {
2170 x
= cpu_to_be32(load_atomic4(haddr
));
2171 ret_be
= (ret_be
<< 32) | x
;
2176 x
= cpu_to_be16(load_atomic2(haddr
));
2177 ret_be
= (ret_be
<< 16) | x
;
2181 x
= *(uint8_t *)haddr
;
2182 ret_be
= (ret_be
<< 8) | x
;
2186 g_assert_not_reached();
2190 } while (size
!= 0);
2196 * @p: translation parameters
2197 * @ret_be: accumulated data
2199 * As do_ld_bytes_beN, but with one atomic load.
2200 * Four aligned bytes are guaranteed to cover the load.
2202 static uint64_t do_ld_whole_be4(MMULookupPageData
*p
, uint64_t ret_be
)
2204 int o
= p
->addr
& 3;
2205 uint32_t x
= load_atomic4(p
->haddr
- o
);
2209 x
>>= (4 - p
->size
) * 8;
2210 return (ret_be
<< (p
->size
* 8)) | x
;
2215 * @p: translation parameters
2216 * @ret_be: accumulated data
2218 * As do_ld_bytes_beN, but with one atomic load.
2219 * Eight aligned bytes are guaranteed to cover the load.
2221 static uint64_t do_ld_whole_be8(CPUArchState
*env
, uintptr_t ra
,
2222 MMULookupPageData
*p
, uint64_t ret_be
)
2224 int o
= p
->addr
& 7;
2225 uint64_t x
= load_atomic8_or_exit(env
, ra
, p
->haddr
- o
);
2229 x
>>= (8 - p
->size
) * 8;
2230 return (ret_be
<< (p
->size
* 8)) | x
;
2235 * @p: translation parameters
2236 * @ret_be: accumulated data
2238 * As do_ld_bytes_beN, but with one atomic load.
2239 * 16 aligned bytes are guaranteed to cover the load.
2241 static Int128
do_ld_whole_be16(CPUArchState
*env
, uintptr_t ra
,
2242 MMULookupPageData
*p
, uint64_t ret_be
)
2244 int o
= p
->addr
& 15;
2245 Int128 x
, y
= load_atomic16_or_exit(env
, ra
, p
->haddr
- o
);
2248 if (!HOST_BIG_ENDIAN
) {
2251 y
= int128_lshift(y
, o
* 8);
2252 y
= int128_urshift(y
, (16 - size
) * 8);
2253 x
= int128_make64(ret_be
);
2254 x
= int128_lshift(x
, size
* 8);
2255 return int128_or(x
, y
);
2259 * Wrapper for the above.
2261 static uint64_t do_ld_beN(CPUArchState
*env
, MMULookupPageData
*p
,
2262 uint64_t ret_be
, int mmu_idx
, MMUAccessType type
,
2263 MemOp mop
, uintptr_t ra
)
2266 unsigned tmp
, half_size
;
2268 if (unlikely(p
->flags
& TLB_MMIO
)) {
2269 QEMU_IOTHREAD_LOCK_GUARD();
2270 return do_ld_mmio_beN(env
, p
->full
, ret_be
, p
->addr
, p
->size
,
2275 * It is a given that we cross a page and therefore there is no
2276 * atomicity for the load as a whole, but subobjects may need attention.
2278 atom
= mop
& MO_ATOM_MASK
;
2280 case MO_ATOM_SUBALIGN
:
2281 return do_ld_parts_beN(p
, ret_be
);
2283 case MO_ATOM_IFALIGN_PAIR
:
2284 case MO_ATOM_WITHIN16_PAIR
:
2285 tmp
= mop
& MO_SIZE
;
2286 tmp
= tmp
? tmp
- 1 : 0;
2287 half_size
= 1 << tmp
;
2288 if (atom
== MO_ATOM_IFALIGN_PAIR
2289 ? p
->size
== half_size
2290 : p
->size
>= half_size
) {
2291 if (!HAVE_al8_fast
&& p
->size
< 4) {
2292 return do_ld_whole_be4(p
, ret_be
);
2294 return do_ld_whole_be8(env
, ra
, p
, ret_be
);
2299 case MO_ATOM_IFALIGN
:
2300 case MO_ATOM_WITHIN16
:
2302 return do_ld_bytes_beN(p
, ret_be
);
2305 g_assert_not_reached();
2310 * Wrapper for the above, for 8 < size < 16.
2312 static Int128
do_ld16_beN(CPUArchState
*env
, MMULookupPageData
*p
,
2313 uint64_t a
, int mmu_idx
, MemOp mop
, uintptr_t ra
)
2319 if (unlikely(p
->flags
& TLB_MMIO
)) {
2320 QEMU_IOTHREAD_LOCK_GUARD();
2321 a
= do_ld_mmio_beN(env
, p
->full
, a
, p
->addr
, size
- 8,
2322 mmu_idx
, MMU_DATA_LOAD
, ra
);
2323 b
= do_ld_mmio_beN(env
, p
->full
, 0, p
->addr
+ 8, 8,
2324 mmu_idx
, MMU_DATA_LOAD
, ra
);
2325 return int128_make128(b
, a
);
2329 * It is a given that we cross a page and therefore there is no
2330 * atomicity for the load as a whole, but subobjects may need attention.
2332 atom
= mop
& MO_ATOM_MASK
;
2334 case MO_ATOM_SUBALIGN
:
2336 a
= do_ld_parts_beN(p
, a
);
2337 p
->haddr
+= size
- 8;
2339 b
= do_ld_parts_beN(p
, 0);
2342 case MO_ATOM_WITHIN16_PAIR
:
2343 /* Since size > 8, this is the half that must be atomic. */
2344 return do_ld_whole_be16(env
, ra
, p
, a
);
2346 case MO_ATOM_IFALIGN_PAIR
:
2348 * Since size > 8, both halves are misaligned,
2349 * and so neither is atomic.
2351 case MO_ATOM_IFALIGN
:
2352 case MO_ATOM_WITHIN16
:
2355 a
= do_ld_bytes_beN(p
, a
);
2356 b
= ldq_be_p(p
->haddr
+ size
- 8);
2360 g_assert_not_reached();
2363 return int128_make128(b
, a
);
2366 static uint8_t do_ld_1(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2367 MMUAccessType type
, uintptr_t ra
)
2369 if (unlikely(p
->flags
& TLB_MMIO
)) {
2370 return io_readx(env
, p
->full
, mmu_idx
, p
->addr
, ra
, type
, MO_UB
);
2372 return *(uint8_t *)p
->haddr
;
2376 static uint16_t do_ld_2(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2377 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2381 if (unlikely(p
->flags
& TLB_MMIO
)) {
2382 QEMU_IOTHREAD_LOCK_GUARD();
2383 ret
= do_ld_mmio_beN(env
, p
->full
, 0, p
->addr
, 2, mmu_idx
, type
, ra
);
2384 if ((memop
& MO_BSWAP
) == MO_LE
) {
2388 /* Perform the load host endian, then swap if necessary. */
2389 ret
= load_atom_2(env
, ra
, p
->haddr
, memop
);
2390 if (memop
& MO_BSWAP
) {
2397 static uint32_t do_ld_4(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2398 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2402 if (unlikely(p
->flags
& TLB_MMIO
)) {
2403 QEMU_IOTHREAD_LOCK_GUARD();
2404 ret
= do_ld_mmio_beN(env
, p
->full
, 0, p
->addr
, 4, mmu_idx
, type
, ra
);
2405 if ((memop
& MO_BSWAP
) == MO_LE
) {
2409 /* Perform the load host endian. */
2410 ret
= load_atom_4(env
, ra
, p
->haddr
, memop
);
2411 if (memop
& MO_BSWAP
) {
2418 static uint64_t do_ld_8(CPUArchState
*env
, MMULookupPageData
*p
, int mmu_idx
,
2419 MMUAccessType type
, MemOp memop
, uintptr_t ra
)
2423 if (unlikely(p
->flags
& TLB_MMIO
)) {
2424 QEMU_IOTHREAD_LOCK_GUARD();
2425 ret
= do_ld_mmio_beN(env
, p
->full
, 0, p
->addr
, 8, mmu_idx
, type
, ra
);
2426 if ((memop
& MO_BSWAP
) == MO_LE
) {
2430 /* Perform the load host endian. */
2431 ret
= load_atom_8(env
, ra
, p
->haddr
, memop
);
2432 if (memop
& MO_BSWAP
) {
2439 static uint8_t do_ld1_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2440 uintptr_t ra
, MMUAccessType access_type
)
2445 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2446 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2447 tcg_debug_assert(!crosspage
);
2449 return do_ld_1(env
, &l
.page
[0], l
.mmu_idx
, access_type
, ra
);
2452 tcg_target_ulong
helper_ldub_mmu(CPUArchState
*env
, uint64_t addr
,
2453 MemOpIdx oi
, uintptr_t retaddr
)
2455 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_8
);
2456 return do_ld1_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2459 static uint16_t do_ld2_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2460 uintptr_t ra
, MMUAccessType access_type
)
2467 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2468 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2469 if (likely(!crosspage
)) {
2470 return do_ld_2(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2473 a
= do_ld_1(env
, &l
.page
[0], l
.mmu_idx
, access_type
, ra
);
2474 b
= do_ld_1(env
, &l
.page
[1], l
.mmu_idx
, access_type
, ra
);
2476 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2484 tcg_target_ulong
helper_lduw_mmu(CPUArchState
*env
, uint64_t addr
,
2485 MemOpIdx oi
, uintptr_t retaddr
)
2487 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2488 return do_ld2_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2491 static uint32_t do_ld4_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2492 uintptr_t ra
, MMUAccessType access_type
)
2498 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2499 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2500 if (likely(!crosspage
)) {
2501 return do_ld_4(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2504 ret
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2505 ret
= do_ld_beN(env
, &l
.page
[1], ret
, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2506 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2512 tcg_target_ulong
helper_ldul_mmu(CPUArchState
*env
, uint64_t addr
,
2513 MemOpIdx oi
, uintptr_t retaddr
)
2515 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2516 return do_ld4_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2519 static uint64_t do_ld8_mmu(CPUArchState
*env
, vaddr addr
, MemOpIdx oi
,
2520 uintptr_t ra
, MMUAccessType access_type
)
2526 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2527 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, access_type
, &l
);
2528 if (likely(!crosspage
)) {
2529 return do_ld_8(env
, &l
.page
[0], l
.mmu_idx
, access_type
, l
.memop
, ra
);
2532 ret
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2533 ret
= do_ld_beN(env
, &l
.page
[1], ret
, l
.mmu_idx
, access_type
, l
.memop
, ra
);
2534 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2540 uint64_t helper_ldq_mmu(CPUArchState
*env
, uint64_t addr
,
2541 MemOpIdx oi
, uintptr_t retaddr
)
2543 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
2544 return do_ld8_mmu(env
, addr
, oi
, retaddr
, MMU_DATA_LOAD
);
2548 * Provide signed versions of the load routines as well. We can of course
2549 * avoid this for 64-bit data, or for 32-bit data on 32-bit host.
2552 tcg_target_ulong
helper_ldsb_mmu(CPUArchState
*env
, uint64_t addr
,
2553 MemOpIdx oi
, uintptr_t retaddr
)
2555 return (int8_t)helper_ldub_mmu(env
, addr
, oi
, retaddr
);
2558 tcg_target_ulong
helper_ldsw_mmu(CPUArchState
*env
, uint64_t addr
,
2559 MemOpIdx oi
, uintptr_t retaddr
)
2561 return (int16_t)helper_lduw_mmu(env
, addr
, oi
, retaddr
);
2564 tcg_target_ulong
helper_ldsl_mmu(CPUArchState
*env
, uint64_t addr
,
2565 MemOpIdx oi
, uintptr_t retaddr
)
2567 return (int32_t)helper_ldul_mmu(env
, addr
, oi
, retaddr
);
2570 static Int128
do_ld16_mmu(CPUArchState
*env
, vaddr addr
,
2571 MemOpIdx oi
, uintptr_t ra
)
2579 cpu_req_mo(TCG_MO_LD_LD
| TCG_MO_ST_LD
);
2580 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_LOAD
, &l
);
2581 if (likely(!crosspage
)) {
2582 if (unlikely(l
.page
[0].flags
& TLB_MMIO
)) {
2583 QEMU_IOTHREAD_LOCK_GUARD();
2584 a
= do_ld_mmio_beN(env
, l
.page
[0].full
, 0, addr
, 8,
2585 l
.mmu_idx
, MMU_DATA_LOAD
, ra
);
2586 b
= do_ld_mmio_beN(env
, l
.page
[0].full
, 0, addr
+ 8, 8,
2587 l
.mmu_idx
, MMU_DATA_LOAD
, ra
);
2588 ret
= int128_make128(b
, a
);
2589 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2590 ret
= bswap128(ret
);
2593 /* Perform the load host endian. */
2594 ret
= load_atom_16(env
, ra
, l
.page
[0].haddr
, l
.memop
);
2595 if (l
.memop
& MO_BSWAP
) {
2596 ret
= bswap128(ret
);
2602 first
= l
.page
[0].size
;
2604 MemOp mop8
= (l
.memop
& ~MO_SIZE
) | MO_64
;
2606 a
= do_ld_8(env
, &l
.page
[0], l
.mmu_idx
, MMU_DATA_LOAD
, mop8
, ra
);
2607 b
= do_ld_8(env
, &l
.page
[1], l
.mmu_idx
, MMU_DATA_LOAD
, mop8
, ra
);
2608 if ((mop8
& MO_BSWAP
) == MO_LE
) {
2609 ret
= int128_make128(a
, b
);
2611 ret
= int128_make128(b
, a
);
2617 a
= do_ld_beN(env
, &l
.page
[0], 0, l
.mmu_idx
,
2618 MMU_DATA_LOAD
, l
.memop
, ra
);
2619 ret
= do_ld16_beN(env
, &l
.page
[1], a
, l
.mmu_idx
, l
.memop
, ra
);
2621 ret
= do_ld16_beN(env
, &l
.page
[0], 0, l
.mmu_idx
, l
.memop
, ra
);
2622 b
= int128_getlo(ret
);
2623 ret
= int128_lshift(ret
, l
.page
[1].size
* 8);
2624 a
= int128_gethi(ret
);
2625 b
= do_ld_beN(env
, &l
.page
[1], b
, l
.mmu_idx
,
2626 MMU_DATA_LOAD
, l
.memop
, ra
);
2627 ret
= int128_make128(b
, a
);
2629 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2630 ret
= bswap128(ret
);
2635 Int128
helper_ld16_mmu(CPUArchState
*env
, uint64_t addr
,
2636 uint32_t oi
, uintptr_t retaddr
)
2638 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
2639 return do_ld16_mmu(env
, addr
, oi
, retaddr
);
2642 Int128
helper_ld_i128(CPUArchState
*env
, uint64_t addr
, uint32_t oi
)
2644 return helper_ld16_mmu(env
, addr
, oi
, GETPC());
2648 * Load helpers for cpu_ldst.h.
2651 static void plugin_load_cb(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
)
2653 qemu_plugin_vcpu_mem_cb(env_cpu(env
), addr
, oi
, QEMU_PLUGIN_MEM_R
);
2656 uint8_t cpu_ldb_mmu(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
, uintptr_t ra
)
2660 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_UB
);
2661 ret
= do_ld1_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2662 plugin_load_cb(env
, addr
, oi
);
2666 uint16_t cpu_ldw_mmu(CPUArchState
*env
, abi_ptr addr
,
2667 MemOpIdx oi
, uintptr_t ra
)
2671 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2672 ret
= do_ld2_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2673 plugin_load_cb(env
, addr
, oi
);
2677 uint32_t cpu_ldl_mmu(CPUArchState
*env
, abi_ptr addr
,
2678 MemOpIdx oi
, uintptr_t ra
)
2682 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
2683 ret
= do_ld4_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2684 plugin_load_cb(env
, addr
, oi
);
2688 uint64_t cpu_ldq_mmu(CPUArchState
*env
, abi_ptr addr
,
2689 MemOpIdx oi
, uintptr_t ra
)
2693 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
2694 ret
= do_ld8_mmu(env
, addr
, oi
, ra
, MMU_DATA_LOAD
);
2695 plugin_load_cb(env
, addr
, oi
);
2699 Int128
cpu_ld16_mmu(CPUArchState
*env
, abi_ptr addr
,
2700 MemOpIdx oi
, uintptr_t ra
)
2704 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
2705 ret
= do_ld16_mmu(env
, addr
, oi
, ra
);
2706 plugin_load_cb(env
, addr
, oi
);
2717 * @full: page parameters
2718 * @val_le: data to store
2719 * @addr: virtual address
2720 * @size: number of bytes
2721 * @mmu_idx: virtual address context
2722 * @ra: return address into tcg generated code, or 0
2723 * Context: iothread lock held
2725 * Store @size bytes at @addr, which is memory-mapped i/o.
2726 * The bytes to store are extracted in little-endian order from @val_le;
2727 * return the bytes of @val_le beyond @p->size that have not been stored.
2729 static uint64_t do_st_mmio_leN(CPUArchState
*env
, CPUTLBEntryFull
*full
,
2730 uint64_t val_le
, vaddr addr
, int size
,
2731 int mmu_idx
, uintptr_t ra
)
2733 tcg_debug_assert(size
> 0 && size
<= 8);
2736 /* Store aligned pieces up to 8 bytes. */
2737 switch ((size
| (int)addr
) & 7) {
2742 io_writex(env
, full
, mmu_idx
, val_le
, addr
, ra
, MO_UB
);
2749 io_writex(env
, full
, mmu_idx
, val_le
, addr
, ra
, MO_LEUW
);
2755 io_writex(env
, full
, mmu_idx
, val_le
, addr
, ra
, MO_LEUL
);
2761 io_writex(env
, full
, mmu_idx
, val_le
, addr
, ra
, MO_LEUQ
);
2764 qemu_build_not_reached();
2772 * Wrapper for the above.
2774 static uint64_t do_st_leN(CPUArchState
*env
, MMULookupPageData
*p
,
2775 uint64_t val_le
, int mmu_idx
,
2776 MemOp mop
, uintptr_t ra
)
2779 unsigned tmp
, half_size
;
2781 if (unlikely(p
->flags
& TLB_MMIO
)) {
2782 QEMU_IOTHREAD_LOCK_GUARD();
2783 return do_st_mmio_leN(env
, p
->full
, val_le
, p
->addr
,
2784 p
->size
, mmu_idx
, ra
);
2785 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2786 return val_le
>> (p
->size
* 8);
2790 * It is a given that we cross a page and therefore there is no atomicity
2791 * for the store as a whole, but subobjects may need attention.
2793 atom
= mop
& MO_ATOM_MASK
;
2795 case MO_ATOM_SUBALIGN
:
2796 return store_parts_leN(p
->haddr
, p
->size
, val_le
);
2798 case MO_ATOM_IFALIGN_PAIR
:
2799 case MO_ATOM_WITHIN16_PAIR
:
2800 tmp
= mop
& MO_SIZE
;
2801 tmp
= tmp
? tmp
- 1 : 0;
2802 half_size
= 1 << tmp
;
2803 if (atom
== MO_ATOM_IFALIGN_PAIR
2804 ? p
->size
== half_size
2805 : p
->size
>= half_size
) {
2806 if (!HAVE_al8_fast
&& p
->size
<= 4) {
2807 return store_whole_le4(p
->haddr
, p
->size
, val_le
);
2808 } else if (HAVE_al8
) {
2809 return store_whole_le8(p
->haddr
, p
->size
, val_le
);
2811 cpu_loop_exit_atomic(env_cpu(env
), ra
);
2816 case MO_ATOM_IFALIGN
:
2817 case MO_ATOM_WITHIN16
:
2819 return store_bytes_leN(p
->haddr
, p
->size
, val_le
);
2822 g_assert_not_reached();
2827 * Wrapper for the above, for 8 < size < 16.
2829 static uint64_t do_st16_leN(CPUArchState
*env
, MMULookupPageData
*p
,
2830 Int128 val_le
, int mmu_idx
,
2831 MemOp mop
, uintptr_t ra
)
2836 if (unlikely(p
->flags
& TLB_MMIO
)) {
2837 QEMU_IOTHREAD_LOCK_GUARD();
2838 do_st_mmio_leN(env
, p
->full
, int128_getlo(val_le
),
2839 p
->addr
, 8, mmu_idx
, ra
);
2840 return do_st_mmio_leN(env
, p
->full
, int128_gethi(val_le
),
2841 p
->addr
+ 8, size
- 8, mmu_idx
, ra
);
2842 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2843 return int128_gethi(val_le
) >> ((size
- 8) * 8);
2847 * It is a given that we cross a page and therefore there is no atomicity
2848 * for the store as a whole, but subobjects may need attention.
2850 atom
= mop
& MO_ATOM_MASK
;
2852 case MO_ATOM_SUBALIGN
:
2853 store_parts_leN(p
->haddr
, 8, int128_getlo(val_le
));
2854 return store_parts_leN(p
->haddr
+ 8, p
->size
- 8,
2855 int128_gethi(val_le
));
2857 case MO_ATOM_WITHIN16_PAIR
:
2858 /* Since size > 8, this is the half that must be atomic. */
2859 if (!HAVE_ATOMIC128_RW
) {
2860 cpu_loop_exit_atomic(env_cpu(env
), ra
);
2862 return store_whole_le16(p
->haddr
, p
->size
, val_le
);
2864 case MO_ATOM_IFALIGN_PAIR
:
2866 * Since size > 8, both halves are misaligned,
2867 * and so neither is atomic.
2869 case MO_ATOM_IFALIGN
:
2870 case MO_ATOM_WITHIN16
:
2872 stq_le_p(p
->haddr
, int128_getlo(val_le
));
2873 return store_bytes_leN(p
->haddr
+ 8, p
->size
- 8,
2874 int128_gethi(val_le
));
2877 g_assert_not_reached();
2881 static void do_st_1(CPUArchState
*env
, MMULookupPageData
*p
, uint8_t val
,
2882 int mmu_idx
, uintptr_t ra
)
2884 if (unlikely(p
->flags
& TLB_MMIO
)) {
2885 io_writex(env
, p
->full
, mmu_idx
, val
, p
->addr
, ra
, MO_UB
);
2886 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2889 *(uint8_t *)p
->haddr
= val
;
2893 static void do_st_2(CPUArchState
*env
, MMULookupPageData
*p
, uint16_t val
,
2894 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2896 if (unlikely(p
->flags
& TLB_MMIO
)) {
2897 if ((memop
& MO_BSWAP
) != MO_LE
) {
2900 QEMU_IOTHREAD_LOCK_GUARD();
2901 do_st_mmio_leN(env
, p
->full
, val
, p
->addr
, 2, mmu_idx
, ra
);
2902 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2905 /* Swap to host endian if necessary, then store. */
2906 if (memop
& MO_BSWAP
) {
2909 store_atom_2(env
, ra
, p
->haddr
, memop
, val
);
2913 static void do_st_4(CPUArchState
*env
, MMULookupPageData
*p
, uint32_t val
,
2914 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2916 if (unlikely(p
->flags
& TLB_MMIO
)) {
2917 if ((memop
& MO_BSWAP
) != MO_LE
) {
2920 QEMU_IOTHREAD_LOCK_GUARD();
2921 do_st_mmio_leN(env
, p
->full
, val
, p
->addr
, 4, mmu_idx
, ra
);
2922 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2925 /* Swap to host endian if necessary, then store. */
2926 if (memop
& MO_BSWAP
) {
2929 store_atom_4(env
, ra
, p
->haddr
, memop
, val
);
2933 static void do_st_8(CPUArchState
*env
, MMULookupPageData
*p
, uint64_t val
,
2934 int mmu_idx
, MemOp memop
, uintptr_t ra
)
2936 if (unlikely(p
->flags
& TLB_MMIO
)) {
2937 if ((memop
& MO_BSWAP
) != MO_LE
) {
2940 QEMU_IOTHREAD_LOCK_GUARD();
2941 do_st_mmio_leN(env
, p
->full
, val
, p
->addr
, 8, mmu_idx
, ra
);
2942 } else if (unlikely(p
->flags
& TLB_DISCARD_WRITE
)) {
2945 /* Swap to host endian if necessary, then store. */
2946 if (memop
& MO_BSWAP
) {
2949 store_atom_8(env
, ra
, p
->haddr
, memop
, val
);
2953 void helper_stb_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
2954 MemOpIdx oi
, uintptr_t ra
)
2959 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_8
);
2960 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
2961 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2962 tcg_debug_assert(!crosspage
);
2964 do_st_1(env
, &l
.page
[0], val
, l
.mmu_idx
, ra
);
2967 static void do_st2_mmu(CPUArchState
*env
, vaddr addr
, uint16_t val
,
2968 MemOpIdx oi
, uintptr_t ra
)
2974 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
2975 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
2976 if (likely(!crosspage
)) {
2977 do_st_2(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
2981 if ((l
.memop
& MO_BSWAP
) == MO_LE
) {
2982 a
= val
, b
= val
>> 8;
2984 b
= val
, a
= val
>> 8;
2986 do_st_1(env
, &l
.page
[0], a
, l
.mmu_idx
, ra
);
2987 do_st_1(env
, &l
.page
[1], b
, l
.mmu_idx
, ra
);
2990 void helper_stw_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
2991 MemOpIdx oi
, uintptr_t retaddr
)
2993 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
2994 do_st2_mmu(env
, addr
, val
, oi
, retaddr
);
2997 static void do_st4_mmu(CPUArchState
*env
, vaddr addr
, uint32_t val
,
2998 MemOpIdx oi
, uintptr_t ra
)
3003 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
3004 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
3005 if (likely(!crosspage
)) {
3006 do_st_4(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
3010 /* Swap to little endian for simplicity, then store by bytes. */
3011 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
3014 val
= do_st_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
3015 (void) do_st_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
3018 void helper_stl_mmu(CPUArchState
*env
, uint64_t addr
, uint32_t val
,
3019 MemOpIdx oi
, uintptr_t retaddr
)
3021 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
3022 do_st4_mmu(env
, addr
, val
, oi
, retaddr
);
3025 static void do_st8_mmu(CPUArchState
*env
, vaddr addr
, uint64_t val
,
3026 MemOpIdx oi
, uintptr_t ra
)
3031 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
3032 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
3033 if (likely(!crosspage
)) {
3034 do_st_8(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
3038 /* Swap to little endian for simplicity, then store by bytes. */
3039 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
3042 val
= do_st_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
3043 (void) do_st_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
3046 void helper_stq_mmu(CPUArchState
*env
, uint64_t addr
, uint64_t val
,
3047 MemOpIdx oi
, uintptr_t retaddr
)
3049 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
3050 do_st8_mmu(env
, addr
, val
, oi
, retaddr
);
3053 static void do_st16_mmu(CPUArchState
*env
, vaddr addr
, Int128 val
,
3054 MemOpIdx oi
, uintptr_t ra
)
3061 cpu_req_mo(TCG_MO_LD_ST
| TCG_MO_ST_ST
);
3062 crosspage
= mmu_lookup(env
, addr
, oi
, ra
, MMU_DATA_STORE
, &l
);
3063 if (likely(!crosspage
)) {
3064 if (unlikely(l
.page
[0].flags
& TLB_MMIO
)) {
3065 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
3066 val
= bswap128(val
);
3068 a
= int128_getlo(val
);
3069 b
= int128_gethi(val
);
3070 QEMU_IOTHREAD_LOCK_GUARD();
3071 do_st_mmio_leN(env
, l
.page
[0].full
, a
, addr
, 8, l
.mmu_idx
, ra
);
3072 do_st_mmio_leN(env
, l
.page
[0].full
, b
, addr
+ 8, 8, l
.mmu_idx
, ra
);
3073 } else if (unlikely(l
.page
[0].flags
& TLB_DISCARD_WRITE
)) {
3076 /* Swap to host endian if necessary, then store. */
3077 if (l
.memop
& MO_BSWAP
) {
3078 val
= bswap128(val
);
3080 store_atom_16(env
, ra
, l
.page
[0].haddr
, l
.memop
, val
);
3085 first
= l
.page
[0].size
;
3087 MemOp mop8
= (l
.memop
& ~(MO_SIZE
| MO_BSWAP
)) | MO_64
;
3089 if (l
.memop
& MO_BSWAP
) {
3090 val
= bswap128(val
);
3092 if (HOST_BIG_ENDIAN
) {
3093 b
= int128_getlo(val
), a
= int128_gethi(val
);
3095 a
= int128_getlo(val
), b
= int128_gethi(val
);
3097 do_st_8(env
, &l
.page
[0], a
, l
.mmu_idx
, mop8
, ra
);
3098 do_st_8(env
, &l
.page
[1], b
, l
.mmu_idx
, mop8
, ra
);
3102 if ((l
.memop
& MO_BSWAP
) != MO_LE
) {
3103 val
= bswap128(val
);
3106 do_st_leN(env
, &l
.page
[0], int128_getlo(val
), l
.mmu_idx
, l
.memop
, ra
);
3107 val
= int128_urshift(val
, first
* 8);
3108 do_st16_leN(env
, &l
.page
[1], val
, l
.mmu_idx
, l
.memop
, ra
);
3110 b
= do_st16_leN(env
, &l
.page
[0], val
, l
.mmu_idx
, l
.memop
, ra
);
3111 do_st_leN(env
, &l
.page
[1], b
, l
.mmu_idx
, l
.memop
, ra
);
3115 void helper_st16_mmu(CPUArchState
*env
, uint64_t addr
, Int128 val
,
3116 MemOpIdx oi
, uintptr_t retaddr
)
3118 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
3119 do_st16_mmu(env
, addr
, val
, oi
, retaddr
);
3122 void helper_st_i128(CPUArchState
*env
, uint64_t addr
, Int128 val
, MemOpIdx oi
)
3124 helper_st16_mmu(env
, addr
, val
, oi
, GETPC());
3128 * Store Helpers for cpu_ldst.h
3131 static void plugin_store_cb(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
)
3133 qemu_plugin_vcpu_mem_cb(env_cpu(env
), addr
, oi
, QEMU_PLUGIN_MEM_W
);
3136 void cpu_stb_mmu(CPUArchState
*env
, abi_ptr addr
, uint8_t val
,
3137 MemOpIdx oi
, uintptr_t retaddr
)
3139 helper_stb_mmu(env
, addr
, val
, oi
, retaddr
);
3140 plugin_store_cb(env
, addr
, oi
);
3143 void cpu_stw_mmu(CPUArchState
*env
, abi_ptr addr
, uint16_t val
,
3144 MemOpIdx oi
, uintptr_t retaddr
)
3146 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_16
);
3147 do_st2_mmu(env
, addr
, val
, oi
, retaddr
);
3148 plugin_store_cb(env
, addr
, oi
);
3151 void cpu_stl_mmu(CPUArchState
*env
, abi_ptr addr
, uint32_t val
,
3152 MemOpIdx oi
, uintptr_t retaddr
)
3154 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_32
);
3155 do_st4_mmu(env
, addr
, val
, oi
, retaddr
);
3156 plugin_store_cb(env
, addr
, oi
);
3159 void cpu_stq_mmu(CPUArchState
*env
, abi_ptr addr
, uint64_t val
,
3160 MemOpIdx oi
, uintptr_t retaddr
)
3162 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_64
);
3163 do_st8_mmu(env
, addr
, val
, oi
, retaddr
);
3164 plugin_store_cb(env
, addr
, oi
);
3167 void cpu_st16_mmu(CPUArchState
*env
, abi_ptr addr
, Int128 val
,
3168 MemOpIdx oi
, uintptr_t retaddr
)
3170 tcg_debug_assert((get_memop(oi
) & MO_SIZE
) == MO_128
);
3171 do_st16_mmu(env
, addr
, val
, oi
, retaddr
);
3172 plugin_store_cb(env
, addr
, oi
);
3175 #include "ldst_common.c.inc"
3178 * First set of functions passes in OI and RETADDR.
3179 * This makes them callable from other helpers.
3182 #define ATOMIC_NAME(X) \
3183 glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
3185 #define ATOMIC_MMU_CLEANUP
3187 #include "atomic_common.c.inc"
3190 #include "atomic_template.h"
3193 #include "atomic_template.h"
3196 #include "atomic_template.h"
3198 #ifdef CONFIG_ATOMIC64
3200 #include "atomic_template.h"
3203 #if defined(CONFIG_ATOMIC128) || HAVE_CMPXCHG128
3204 #define DATA_SIZE 16
3205 #include "atomic_template.h"
3208 /* Code access functions. */
3210 uint32_t cpu_ldub_code(CPUArchState
*env
, abi_ptr addr
)
3212 MemOpIdx oi
= make_memop_idx(MO_UB
, cpu_mmu_index(env
, true));
3213 return do_ld1_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3216 uint32_t cpu_lduw_code(CPUArchState
*env
, abi_ptr addr
)
3218 MemOpIdx oi
= make_memop_idx(MO_TEUW
, cpu_mmu_index(env
, true));
3219 return do_ld2_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3222 uint32_t cpu_ldl_code(CPUArchState
*env
, abi_ptr addr
)
3224 MemOpIdx oi
= make_memop_idx(MO_TEUL
, cpu_mmu_index(env
, true));
3225 return do_ld4_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3228 uint64_t cpu_ldq_code(CPUArchState
*env
, abi_ptr addr
)
3230 MemOpIdx oi
= make_memop_idx(MO_TEUQ
, cpu_mmu_index(env
, true));
3231 return do_ld8_mmu(env
, addr
, oi
, 0, MMU_INST_FETCH
);
3234 uint8_t cpu_ldb_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3235 MemOpIdx oi
, uintptr_t retaddr
)
3237 return do_ld1_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3240 uint16_t cpu_ldw_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3241 MemOpIdx oi
, uintptr_t retaddr
)
3243 return do_ld2_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3246 uint32_t cpu_ldl_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3247 MemOpIdx oi
, uintptr_t retaddr
)
3249 return do_ld4_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);
3252 uint64_t cpu_ldq_code_mmu(CPUArchState
*env
, abi_ptr addr
,
3253 MemOpIdx oi
, uintptr_t retaddr
)
3255 return do_ld8_mmu(env
, addr
, oi
, retaddr
, MMU_INST_FETCH
);