2 * Common CPU TLB handling
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
22 #include "hw/core/tcg-cpu-ops.h"
23 #include "exec/exec-all.h"
24 #include "exec/memory.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/cputlb.h"
27 #include "exec/memory-internal.h"
28 #include "exec/ram_addr.h"
30 #include "qemu/error-report.h"
32 #include "exec/helper-proto.h"
33 #include "qemu/atomic.h"
34 #include "qemu/atomic128.h"
35 #include "exec/translate-all.h"
36 #include "trace/trace-root.h"
40 #include "qemu/plugin-memory.h"
42 #include "tcg/tcg-ldst.h"
44 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
45 /* #define DEBUG_TLB */
46 /* #define DEBUG_TLB_LOG */
49 # define DEBUG_TLB_GATE 1
51 # define DEBUG_TLB_LOG_GATE 1
53 # define DEBUG_TLB_LOG_GATE 0
56 # define DEBUG_TLB_GATE 0
57 # define DEBUG_TLB_LOG_GATE 0
60 #define tlb_debug(fmt, ...) do { \
61 if (DEBUG_TLB_LOG_GATE) { \
62 qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
64 } else if (DEBUG_TLB_GATE) { \
65 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
69 #define assert_cpu_is_self(cpu) do { \
70 if (DEBUG_TLB_GATE) { \
71 g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \
75 /* run_on_cpu_data.target_ptr should always be big enough for a
76 * target_ulong even on 32 bit builds */
77 QEMU_BUILD_BUG_ON(sizeof(target_ulong
) > sizeof(run_on_cpu_data
));
79 /* We currently can't handle more than 16 bits in the MMUIDX bitmask.
81 QEMU_BUILD_BUG_ON(NB_MMU_MODES
> 16);
82 #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
84 static inline size_t tlb_n_entries(CPUTLBDescFast
*fast
)
86 return (fast
->mask
>> CPU_TLB_ENTRY_BITS
) + 1;
89 static inline size_t sizeof_tlb(CPUTLBDescFast
*fast
)
91 return fast
->mask
+ (1 << CPU_TLB_ENTRY_BITS
);
94 static void tlb_window_reset(CPUTLBDesc
*desc
, int64_t ns
,
97 desc
->window_begin_ns
= ns
;
98 desc
->window_max_entries
= max_entries
;
101 static void tb_jmp_cache_clear_page(CPUState
*cpu
, target_ulong page_addr
)
103 unsigned int i
, i0
= tb_jmp_cache_hash_page(page_addr
);
105 for (i
= 0; i
< TB_JMP_PAGE_SIZE
; i
++) {
106 qatomic_set(&cpu
->tb_jmp_cache
[i0
+ i
], NULL
);
111 * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
112 * @desc: The CPUTLBDesc portion of the TLB
113 * @fast: The CPUTLBDescFast portion of the same TLB
115 * Called with tlb_lock_held.
117 * We have two main constraints when resizing a TLB: (1) we only resize it
118 * on a TLB flush (otherwise we'd have to take a perf hit by either rehashing
119 * the array or unnecessarily flushing it), which means we do not control how
120 * frequently the resizing can occur; (2) we don't have access to the guest's
121 * future scheduling decisions, and therefore have to decide the magnitude of
122 * the resize based on past observations.
124 * In general, a memory-hungry process can benefit greatly from an appropriately
125 * sized TLB, since a guest TLB miss is very expensive. This doesn't mean that
126 * we just have to make the TLB as large as possible; while an oversized TLB
127 * results in minimal TLB miss rates, it also takes longer to be flushed
128 * (flushes can be _very_ frequent), and the reduced locality can also hurt
131 * To achieve near-optimal performance for all kinds of workloads, we:
133 * 1. Aggressively increase the size of the TLB when the use rate of the
134 * TLB being flushed is high, since it is likely that in the near future this
135 * memory-hungry process will execute again, and its memory hungriness will
136 * probably be similar.
138 * 2. Slowly reduce the size of the TLB as the use rate declines over a
139 * reasonably large time window. The rationale is that if in such a time window
140 * we have not observed a high TLB use rate, it is likely that we won't observe
141 * it in the near future. In that case, once a time window expires we downsize
142 * the TLB to match the maximum use rate observed in the window.
144 * 3. Try to keep the maximum use rate in a time window in the 30-70% range,
145 * since in that range performance is likely near-optimal. Recall that the TLB
146 * is direct mapped, so we want the use rate to be low (or at least not too
147 * high), since otherwise we are likely to have a significant amount of
150 static void tlb_mmu_resize_locked(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
,
153 size_t old_size
= tlb_n_entries(fast
);
155 size_t new_size
= old_size
;
156 int64_t window_len_ms
= 100;
157 int64_t window_len_ns
= window_len_ms
* 1000 * 1000;
158 bool window_expired
= now
> desc
->window_begin_ns
+ window_len_ns
;
160 if (desc
->n_used_entries
> desc
->window_max_entries
) {
161 desc
->window_max_entries
= desc
->n_used_entries
;
163 rate
= desc
->window_max_entries
* 100 / old_size
;
166 new_size
= MIN(old_size
<< 1, 1 << CPU_TLB_DYN_MAX_BITS
);
167 } else if (rate
< 30 && window_expired
) {
168 size_t ceil
= pow2ceil(desc
->window_max_entries
);
169 size_t expected_rate
= desc
->window_max_entries
* 100 / ceil
;
172 * Avoid undersizing when the max number of entries seen is just below
173 * a pow2. For instance, if max_entries == 1025, the expected use rate
174 * would be 1025/2048==50%. However, if max_entries == 1023, we'd get
175 * 1023/1024==99.9% use rate, so we'd likely end up doubling the size
176 * later. Thus, make sure that the expected use rate remains below 70%.
177 * (and since we double the size, that means the lowest rate we'd
178 * expect to get is 35%, which is still in the 30-70% range where
179 * we consider that the size is appropriate.)
181 if (expected_rate
> 70) {
184 new_size
= MAX(ceil
, 1 << CPU_TLB_DYN_MIN_BITS
);
187 if (new_size
== old_size
) {
188 if (window_expired
) {
189 tlb_window_reset(desc
, now
, desc
->n_used_entries
);
195 g_free(desc
->fulltlb
);
197 tlb_window_reset(desc
, now
, 0);
198 /* desc->n_used_entries is cleared by the caller */
199 fast
->mask
= (new_size
- 1) << CPU_TLB_ENTRY_BITS
;
200 fast
->table
= g_try_new(CPUTLBEntry
, new_size
);
201 desc
->fulltlb
= g_try_new(CPUTLBEntryFull
, new_size
);
204 * If the allocations fail, try smaller sizes. We just freed some
205 * memory, so going back to half of new_size has a good chance of working.
206 * Increased memory pressure elsewhere in the system might cause the
207 * allocations to fail though, so we progressively reduce the allocation
208 * size, aborting if we cannot even allocate the smallest TLB we support.
210 while (fast
->table
== NULL
|| desc
->fulltlb
== NULL
) {
211 if (new_size
== (1 << CPU_TLB_DYN_MIN_BITS
)) {
212 error_report("%s: %s", __func__
, strerror(errno
));
215 new_size
= MAX(new_size
>> 1, 1 << CPU_TLB_DYN_MIN_BITS
);
216 fast
->mask
= (new_size
- 1) << CPU_TLB_ENTRY_BITS
;
219 g_free(desc
->fulltlb
);
220 fast
->table
= g_try_new(CPUTLBEntry
, new_size
);
221 desc
->fulltlb
= g_try_new(CPUTLBEntryFull
, new_size
);
225 static void tlb_mmu_flush_locked(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
)
227 desc
->n_used_entries
= 0;
228 desc
->large_page_addr
= -1;
229 desc
->large_page_mask
= -1;
231 memset(fast
->table
, -1, sizeof_tlb(fast
));
232 memset(desc
->vtable
, -1, sizeof(desc
->vtable
));
235 static void tlb_flush_one_mmuidx_locked(CPUArchState
*env
, int mmu_idx
,
238 CPUTLBDesc
*desc
= &env_tlb(env
)->d
[mmu_idx
];
239 CPUTLBDescFast
*fast
= &env_tlb(env
)->f
[mmu_idx
];
241 tlb_mmu_resize_locked(desc
, fast
, now
);
242 tlb_mmu_flush_locked(desc
, fast
);
245 static void tlb_mmu_init(CPUTLBDesc
*desc
, CPUTLBDescFast
*fast
, int64_t now
)
247 size_t n_entries
= 1 << CPU_TLB_DYN_DEFAULT_BITS
;
249 tlb_window_reset(desc
, now
, 0);
250 desc
->n_used_entries
= 0;
251 fast
->mask
= (n_entries
- 1) << CPU_TLB_ENTRY_BITS
;
252 fast
->table
= g_new(CPUTLBEntry
, n_entries
);
253 desc
->fulltlb
= g_new(CPUTLBEntryFull
, n_entries
);
254 tlb_mmu_flush_locked(desc
, fast
);
257 static inline void tlb_n_used_entries_inc(CPUArchState
*env
, uintptr_t mmu_idx
)
259 env_tlb(env
)->d
[mmu_idx
].n_used_entries
++;
262 static inline void tlb_n_used_entries_dec(CPUArchState
*env
, uintptr_t mmu_idx
)
264 env_tlb(env
)->d
[mmu_idx
].n_used_entries
--;
267 void tlb_init(CPUState
*cpu
)
269 CPUArchState
*env
= cpu
->env_ptr
;
270 int64_t now
= get_clock_realtime();
273 qemu_spin_init(&env_tlb(env
)->c
.lock
);
275 /* All tlbs are initialized flushed. */
276 env_tlb(env
)->c
.dirty
= 0;
278 for (i
= 0; i
< NB_MMU_MODES
; i
++) {
279 tlb_mmu_init(&env_tlb(env
)->d
[i
], &env_tlb(env
)->f
[i
], now
);
283 void tlb_destroy(CPUState
*cpu
)
285 CPUArchState
*env
= cpu
->env_ptr
;
288 qemu_spin_destroy(&env_tlb(env
)->c
.lock
);
289 for (i
= 0; i
< NB_MMU_MODES
; i
++) {
290 CPUTLBDesc
*desc
= &env_tlb(env
)->d
[i
];
291 CPUTLBDescFast
*fast
= &env_tlb(env
)->f
[i
];
294 g_free(desc
->fulltlb
);
298 /* flush_all_helper: run fn across all cpus
300 * If the wait flag is set then the src cpu's helper will be queued as
301 * "safe" work and the loop exited creating a synchronisation point
302 * where all queued work will be finished before execution starts
305 static void flush_all_helper(CPUState
*src
, run_on_cpu_func fn
,
312 async_run_on_cpu(cpu
, fn
, d
);
317 void tlb_flush_counts(size_t *pfull
, size_t *ppart
, size_t *pelide
)
320 size_t full
= 0, part
= 0, elide
= 0;
323 CPUArchState
*env
= cpu
->env_ptr
;
325 full
+= qatomic_read(&env_tlb(env
)->c
.full_flush_count
);
326 part
+= qatomic_read(&env_tlb(env
)->c
.part_flush_count
);
327 elide
+= qatomic_read(&env_tlb(env
)->c
.elide_flush_count
);
334 static void tlb_flush_by_mmuidx_async_work(CPUState
*cpu
, run_on_cpu_data data
)
336 CPUArchState
*env
= cpu
->env_ptr
;
337 uint16_t asked
= data
.host_int
;
338 uint16_t all_dirty
, work
, to_clean
;
339 int64_t now
= get_clock_realtime();
341 assert_cpu_is_self(cpu
);
343 tlb_debug("mmu_idx:0x%04" PRIx16
"\n", asked
);
345 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
347 all_dirty
= env_tlb(env
)->c
.dirty
;
348 to_clean
= asked
& all_dirty
;
349 all_dirty
&= ~to_clean
;
350 env_tlb(env
)->c
.dirty
= all_dirty
;
352 for (work
= to_clean
; work
!= 0; work
&= work
- 1) {
353 int mmu_idx
= ctz32(work
);
354 tlb_flush_one_mmuidx_locked(env
, mmu_idx
, now
);
357 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
359 cpu_tb_jmp_cache_clear(cpu
);
361 if (to_clean
== ALL_MMUIDX_BITS
) {
362 qatomic_set(&env_tlb(env
)->c
.full_flush_count
,
363 env_tlb(env
)->c
.full_flush_count
+ 1);
365 qatomic_set(&env_tlb(env
)->c
.part_flush_count
,
366 env_tlb(env
)->c
.part_flush_count
+ ctpop16(to_clean
));
367 if (to_clean
!= asked
) {
368 qatomic_set(&env_tlb(env
)->c
.elide_flush_count
,
369 env_tlb(env
)->c
.elide_flush_count
+
370 ctpop16(asked
& ~to_clean
));
375 void tlb_flush_by_mmuidx(CPUState
*cpu
, uint16_t idxmap
)
377 tlb_debug("mmu_idx: 0x%" PRIx16
"\n", idxmap
);
379 if (cpu
->created
&& !qemu_cpu_is_self(cpu
)) {
380 async_run_on_cpu(cpu
, tlb_flush_by_mmuidx_async_work
,
381 RUN_ON_CPU_HOST_INT(idxmap
));
383 tlb_flush_by_mmuidx_async_work(cpu
, RUN_ON_CPU_HOST_INT(idxmap
));
387 void tlb_flush(CPUState
*cpu
)
389 tlb_flush_by_mmuidx(cpu
, ALL_MMUIDX_BITS
);
392 void tlb_flush_by_mmuidx_all_cpus(CPUState
*src_cpu
, uint16_t idxmap
)
394 const run_on_cpu_func fn
= tlb_flush_by_mmuidx_async_work
;
396 tlb_debug("mmu_idx: 0x%"PRIx16
"\n", idxmap
);
398 flush_all_helper(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
399 fn(src_cpu
, RUN_ON_CPU_HOST_INT(idxmap
));
402 void tlb_flush_all_cpus(CPUState
*src_cpu
)
404 tlb_flush_by_mmuidx_all_cpus(src_cpu
, ALL_MMUIDX_BITS
);
407 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
, uint16_t idxmap
)
409 const run_on_cpu_func fn
= tlb_flush_by_mmuidx_async_work
;
411 tlb_debug("mmu_idx: 0x%"PRIx16
"\n", idxmap
);
413 flush_all_helper(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
414 async_safe_run_on_cpu(src_cpu
, fn
, RUN_ON_CPU_HOST_INT(idxmap
));
417 void tlb_flush_all_cpus_synced(CPUState
*src_cpu
)
419 tlb_flush_by_mmuidx_all_cpus_synced(src_cpu
, ALL_MMUIDX_BITS
);
422 static bool tlb_hit_page_mask_anyprot(CPUTLBEntry
*tlb_entry
,
423 target_ulong page
, target_ulong mask
)
426 mask
&= TARGET_PAGE_MASK
| TLB_INVALID_MASK
;
428 return (page
== (tlb_entry
->addr_read
& mask
) ||
429 page
== (tlb_addr_write(tlb_entry
) & mask
) ||
430 page
== (tlb_entry
->addr_code
& mask
));
433 static inline bool tlb_hit_page_anyprot(CPUTLBEntry
*tlb_entry
,
436 return tlb_hit_page_mask_anyprot(tlb_entry
, page
, -1);
440 * tlb_entry_is_empty - return true if the entry is not in use
441 * @te: pointer to CPUTLBEntry
443 static inline bool tlb_entry_is_empty(const CPUTLBEntry
*te
)
445 return te
->addr_read
== -1 && te
->addr_write
== -1 && te
->addr_code
== -1;
448 /* Called with tlb_c.lock held */
449 static bool tlb_flush_entry_mask_locked(CPUTLBEntry
*tlb_entry
,
453 if (tlb_hit_page_mask_anyprot(tlb_entry
, page
, mask
)) {
454 memset(tlb_entry
, -1, sizeof(*tlb_entry
));
460 static inline bool tlb_flush_entry_locked(CPUTLBEntry
*tlb_entry
,
463 return tlb_flush_entry_mask_locked(tlb_entry
, page
, -1);
466 /* Called with tlb_c.lock held */
467 static void tlb_flush_vtlb_page_mask_locked(CPUArchState
*env
, int mmu_idx
,
471 CPUTLBDesc
*d
= &env_tlb(env
)->d
[mmu_idx
];
474 assert_cpu_is_self(env_cpu(env
));
475 for (k
= 0; k
< CPU_VTLB_SIZE
; k
++) {
476 if (tlb_flush_entry_mask_locked(&d
->vtable
[k
], page
, mask
)) {
477 tlb_n_used_entries_dec(env
, mmu_idx
);
482 static inline void tlb_flush_vtlb_page_locked(CPUArchState
*env
, int mmu_idx
,
485 tlb_flush_vtlb_page_mask_locked(env
, mmu_idx
, page
, -1);
488 static void tlb_flush_page_locked(CPUArchState
*env
, int midx
,
491 target_ulong lp_addr
= env_tlb(env
)->d
[midx
].large_page_addr
;
492 target_ulong lp_mask
= env_tlb(env
)->d
[midx
].large_page_mask
;
494 /* Check if we need to flush due to large pages. */
495 if ((page
& lp_mask
) == lp_addr
) {
496 tlb_debug("forcing full flush midx %d ("
497 TARGET_FMT_lx
"/" TARGET_FMT_lx
")\n",
498 midx
, lp_addr
, lp_mask
);
499 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
501 if (tlb_flush_entry_locked(tlb_entry(env
, midx
, page
), page
)) {
502 tlb_n_used_entries_dec(env
, midx
);
504 tlb_flush_vtlb_page_locked(env
, midx
, page
);
509 * tlb_flush_page_by_mmuidx_async_0:
510 * @cpu: cpu on which to flush
511 * @addr: page of virtual address to flush
512 * @idxmap: set of mmu_idx to flush
514 * Helper for tlb_flush_page_by_mmuidx and friends, flush one page
515 * at @addr from the tlbs indicated by @idxmap from @cpu.
517 static void tlb_flush_page_by_mmuidx_async_0(CPUState
*cpu
,
521 CPUArchState
*env
= cpu
->env_ptr
;
524 assert_cpu_is_self(cpu
);
526 tlb_debug("page addr:" TARGET_FMT_lx
" mmu_map:0x%x\n", addr
, idxmap
);
528 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
529 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
530 if ((idxmap
>> mmu_idx
) & 1) {
531 tlb_flush_page_locked(env
, mmu_idx
, addr
);
534 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
537 * Discard jump cache entries for any tb which might potentially
538 * overlap the flushed page, which includes the previous.
540 tb_jmp_cache_clear_page(cpu
, addr
- TARGET_PAGE_SIZE
);
541 tb_jmp_cache_clear_page(cpu
, addr
);
545 * tlb_flush_page_by_mmuidx_async_1:
546 * @cpu: cpu on which to flush
547 * @data: encoded addr + idxmap
549 * Helper for tlb_flush_page_by_mmuidx and friends, called through
550 * async_run_on_cpu. The idxmap parameter is encoded in the page
551 * offset of the target_ptr field. This limits the set of mmu_idx
552 * that can be passed via this method.
554 static void tlb_flush_page_by_mmuidx_async_1(CPUState
*cpu
,
555 run_on_cpu_data data
)
557 target_ulong addr_and_idxmap
= (target_ulong
) data
.target_ptr
;
558 target_ulong addr
= addr_and_idxmap
& TARGET_PAGE_MASK
;
559 uint16_t idxmap
= addr_and_idxmap
& ~TARGET_PAGE_MASK
;
561 tlb_flush_page_by_mmuidx_async_0(cpu
, addr
, idxmap
);
567 } TLBFlushPageByMMUIdxData
;
570 * tlb_flush_page_by_mmuidx_async_2:
571 * @cpu: cpu on which to flush
572 * @data: allocated addr + idxmap
574 * Helper for tlb_flush_page_by_mmuidx and friends, called through
575 * async_run_on_cpu. The addr+idxmap parameters are stored in a
576 * TLBFlushPageByMMUIdxData structure that has been allocated
577 * specifically for this helper. Free the structure when done.
579 static void tlb_flush_page_by_mmuidx_async_2(CPUState
*cpu
,
580 run_on_cpu_data data
)
582 TLBFlushPageByMMUIdxData
*d
= data
.host_ptr
;
584 tlb_flush_page_by_mmuidx_async_0(cpu
, d
->addr
, d
->idxmap
);
588 void tlb_flush_page_by_mmuidx(CPUState
*cpu
, target_ulong addr
, uint16_t idxmap
)
590 tlb_debug("addr: "TARGET_FMT_lx
" mmu_idx:%" PRIx16
"\n", addr
, idxmap
);
592 /* This should already be page aligned */
593 addr
&= TARGET_PAGE_MASK
;
595 if (qemu_cpu_is_self(cpu
)) {
596 tlb_flush_page_by_mmuidx_async_0(cpu
, addr
, idxmap
);
597 } else if (idxmap
< TARGET_PAGE_SIZE
) {
599 * Most targets have only a few mmu_idx. In the case where
600 * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid
601 * allocating memory for this operation.
603 async_run_on_cpu(cpu
, tlb_flush_page_by_mmuidx_async_1
,
604 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
606 TLBFlushPageByMMUIdxData
*d
= g_new(TLBFlushPageByMMUIdxData
, 1);
608 /* Otherwise allocate a structure, freed by the worker. */
611 async_run_on_cpu(cpu
, tlb_flush_page_by_mmuidx_async_2
,
612 RUN_ON_CPU_HOST_PTR(d
));
616 void tlb_flush_page(CPUState
*cpu
, target_ulong addr
)
618 tlb_flush_page_by_mmuidx(cpu
, addr
, ALL_MMUIDX_BITS
);
621 void tlb_flush_page_by_mmuidx_all_cpus(CPUState
*src_cpu
, target_ulong addr
,
624 tlb_debug("addr: "TARGET_FMT_lx
" mmu_idx:%"PRIx16
"\n", addr
, idxmap
);
626 /* This should already be page aligned */
627 addr
&= TARGET_PAGE_MASK
;
630 * Allocate memory to hold addr+idxmap only when needed.
631 * See tlb_flush_page_by_mmuidx for details.
633 if (idxmap
< TARGET_PAGE_SIZE
) {
634 flush_all_helper(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
635 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
639 /* Allocate a separate data block for each destination cpu. */
640 CPU_FOREACH(dst_cpu
) {
641 if (dst_cpu
!= src_cpu
) {
642 TLBFlushPageByMMUIdxData
*d
643 = g_new(TLBFlushPageByMMUIdxData
, 1);
647 async_run_on_cpu(dst_cpu
, tlb_flush_page_by_mmuidx_async_2
,
648 RUN_ON_CPU_HOST_PTR(d
));
653 tlb_flush_page_by_mmuidx_async_0(src_cpu
, addr
, idxmap
);
656 void tlb_flush_page_all_cpus(CPUState
*src
, target_ulong addr
)
658 tlb_flush_page_by_mmuidx_all_cpus(src
, addr
, ALL_MMUIDX_BITS
);
661 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
665 tlb_debug("addr: "TARGET_FMT_lx
" mmu_idx:%"PRIx16
"\n", addr
, idxmap
);
667 /* This should already be page aligned */
668 addr
&= TARGET_PAGE_MASK
;
671 * Allocate memory to hold addr+idxmap only when needed.
672 * See tlb_flush_page_by_mmuidx for details.
674 if (idxmap
< TARGET_PAGE_SIZE
) {
675 flush_all_helper(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
676 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
677 async_safe_run_on_cpu(src_cpu
, tlb_flush_page_by_mmuidx_async_1
,
678 RUN_ON_CPU_TARGET_PTR(addr
| idxmap
));
681 TLBFlushPageByMMUIdxData
*d
;
683 /* Allocate a separate data block for each destination cpu. */
684 CPU_FOREACH(dst_cpu
) {
685 if (dst_cpu
!= src_cpu
) {
686 d
= g_new(TLBFlushPageByMMUIdxData
, 1);
689 async_run_on_cpu(dst_cpu
, tlb_flush_page_by_mmuidx_async_2
,
690 RUN_ON_CPU_HOST_PTR(d
));
694 d
= g_new(TLBFlushPageByMMUIdxData
, 1);
697 async_safe_run_on_cpu(src_cpu
, tlb_flush_page_by_mmuidx_async_2
,
698 RUN_ON_CPU_HOST_PTR(d
));
702 void tlb_flush_page_all_cpus_synced(CPUState
*src
, target_ulong addr
)
704 tlb_flush_page_by_mmuidx_all_cpus_synced(src
, addr
, ALL_MMUIDX_BITS
);
707 static void tlb_flush_range_locked(CPUArchState
*env
, int midx
,
708 target_ulong addr
, target_ulong len
,
711 CPUTLBDesc
*d
= &env_tlb(env
)->d
[midx
];
712 CPUTLBDescFast
*f
= &env_tlb(env
)->f
[midx
];
713 target_ulong mask
= MAKE_64BIT_MASK(0, bits
);
716 * If @bits is smaller than the tlb size, there may be multiple entries
717 * within the TLB; otherwise all addresses that match under @mask hit
718 * the same TLB entry.
719 * TODO: Perhaps allow bits to be a few bits less than the size.
720 * For now, just flush the entire TLB.
722 * If @len is larger than the tlb size, then it will take longer to
723 * test all of the entries in the TLB than it will to flush it all.
725 if (mask
< f
->mask
|| len
> f
->mask
) {
726 tlb_debug("forcing full flush midx %d ("
727 TARGET_FMT_lx
"/" TARGET_FMT_lx
"+" TARGET_FMT_lx
")\n",
728 midx
, addr
, mask
, len
);
729 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
734 * Check if we need to flush due to large pages.
735 * Because large_page_mask contains all 1's from the msb,
736 * we only need to test the end of the range.
738 if (((addr
+ len
- 1) & d
->large_page_mask
) == d
->large_page_addr
) {
739 tlb_debug("forcing full flush midx %d ("
740 TARGET_FMT_lx
"/" TARGET_FMT_lx
")\n",
741 midx
, d
->large_page_addr
, d
->large_page_mask
);
742 tlb_flush_one_mmuidx_locked(env
, midx
, get_clock_realtime());
746 for (target_ulong i
= 0; i
< len
; i
+= TARGET_PAGE_SIZE
) {
747 target_ulong page
= addr
+ i
;
748 CPUTLBEntry
*entry
= tlb_entry(env
, midx
, page
);
750 if (tlb_flush_entry_mask_locked(entry
, page
, mask
)) {
751 tlb_n_used_entries_dec(env
, midx
);
753 tlb_flush_vtlb_page_mask_locked(env
, midx
, page
, mask
);
764 static void tlb_flush_range_by_mmuidx_async_0(CPUState
*cpu
,
767 CPUArchState
*env
= cpu
->env_ptr
;
770 assert_cpu_is_self(cpu
);
772 tlb_debug("range:" TARGET_FMT_lx
"/%u+" TARGET_FMT_lx
" mmu_map:0x%x\n",
773 d
.addr
, d
.bits
, d
.len
, d
.idxmap
);
775 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
776 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
777 if ((d
.idxmap
>> mmu_idx
) & 1) {
778 tlb_flush_range_locked(env
, mmu_idx
, d
.addr
, d
.len
, d
.bits
);
781 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
784 * If the length is larger than the jump cache size, then it will take
785 * longer to clear each entry individually than it will to clear it all.
787 if (d
.len
>= (TARGET_PAGE_SIZE
* TB_JMP_CACHE_SIZE
)) {
788 cpu_tb_jmp_cache_clear(cpu
);
793 * Discard jump cache entries for any tb which might potentially
794 * overlap the flushed pages, which includes the previous.
796 d
.addr
-= TARGET_PAGE_SIZE
;
797 for (target_ulong i
= 0, n
= d
.len
/ TARGET_PAGE_SIZE
+ 1; i
< n
; i
++) {
798 tb_jmp_cache_clear_page(cpu
, d
.addr
);
799 d
.addr
+= TARGET_PAGE_SIZE
;
803 static void tlb_flush_range_by_mmuidx_async_1(CPUState
*cpu
,
804 run_on_cpu_data data
)
806 TLBFlushRangeData
*d
= data
.host_ptr
;
807 tlb_flush_range_by_mmuidx_async_0(cpu
, *d
);
811 void tlb_flush_range_by_mmuidx(CPUState
*cpu
, target_ulong addr
,
812 target_ulong len
, uint16_t idxmap
,
818 * If all bits are significant, and len is small,
819 * this devolves to tlb_flush_page.
821 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
822 tlb_flush_page_by_mmuidx(cpu
, addr
, idxmap
);
825 /* If no page bits are significant, this devolves to tlb_flush. */
826 if (bits
< TARGET_PAGE_BITS
) {
827 tlb_flush_by_mmuidx(cpu
, idxmap
);
831 /* This should already be page aligned */
832 d
.addr
= addr
& TARGET_PAGE_MASK
;
837 if (qemu_cpu_is_self(cpu
)) {
838 tlb_flush_range_by_mmuidx_async_0(cpu
, d
);
840 /* Otherwise allocate a structure, freed by the worker. */
841 TLBFlushRangeData
*p
= g_memdup(&d
, sizeof(d
));
842 async_run_on_cpu(cpu
, tlb_flush_range_by_mmuidx_async_1
,
843 RUN_ON_CPU_HOST_PTR(p
));
847 void tlb_flush_page_bits_by_mmuidx(CPUState
*cpu
, target_ulong addr
,
848 uint16_t idxmap
, unsigned bits
)
850 tlb_flush_range_by_mmuidx(cpu
, addr
, TARGET_PAGE_SIZE
, idxmap
, bits
);
853 void tlb_flush_range_by_mmuidx_all_cpus(CPUState
*src_cpu
,
854 target_ulong addr
, target_ulong len
,
855 uint16_t idxmap
, unsigned bits
)
861 * If all bits are significant, and len is small,
862 * this devolves to tlb_flush_page.
864 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
865 tlb_flush_page_by_mmuidx_all_cpus(src_cpu
, addr
, idxmap
);
868 /* If no page bits are significant, this devolves to tlb_flush. */
869 if (bits
< TARGET_PAGE_BITS
) {
870 tlb_flush_by_mmuidx_all_cpus(src_cpu
, idxmap
);
874 /* This should already be page aligned */
875 d
.addr
= addr
& TARGET_PAGE_MASK
;
880 /* Allocate a separate data block for each destination cpu. */
881 CPU_FOREACH(dst_cpu
) {
882 if (dst_cpu
!= src_cpu
) {
883 TLBFlushRangeData
*p
= g_memdup(&d
, sizeof(d
));
884 async_run_on_cpu(dst_cpu
,
885 tlb_flush_range_by_mmuidx_async_1
,
886 RUN_ON_CPU_HOST_PTR(p
));
890 tlb_flush_range_by_mmuidx_async_0(src_cpu
, d
);
893 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState
*src_cpu
,
895 uint16_t idxmap
, unsigned bits
)
897 tlb_flush_range_by_mmuidx_all_cpus(src_cpu
, addr
, TARGET_PAGE_SIZE
,
901 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
907 TLBFlushRangeData d
, *p
;
911 * If all bits are significant, and len is small,
912 * this devolves to tlb_flush_page.
914 if (bits
>= TARGET_LONG_BITS
&& len
<= TARGET_PAGE_SIZE
) {
915 tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu
, addr
, idxmap
);
918 /* If no page bits are significant, this devolves to tlb_flush. */
919 if (bits
< TARGET_PAGE_BITS
) {
920 tlb_flush_by_mmuidx_all_cpus_synced(src_cpu
, idxmap
);
924 /* This should already be page aligned */
925 d
.addr
= addr
& TARGET_PAGE_MASK
;
930 /* Allocate a separate data block for each destination cpu. */
931 CPU_FOREACH(dst_cpu
) {
932 if (dst_cpu
!= src_cpu
) {
933 p
= g_memdup(&d
, sizeof(d
));
934 async_run_on_cpu(dst_cpu
, tlb_flush_range_by_mmuidx_async_1
,
935 RUN_ON_CPU_HOST_PTR(p
));
939 p
= g_memdup(&d
, sizeof(d
));
940 async_safe_run_on_cpu(src_cpu
, tlb_flush_range_by_mmuidx_async_1
,
941 RUN_ON_CPU_HOST_PTR(p
));
944 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState
*src_cpu
,
949 tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu
, addr
, TARGET_PAGE_SIZE
,
953 /* update the TLBs so that writes to code in the virtual page 'addr'
955 void tlb_protect_code(ram_addr_t ram_addr
)
957 cpu_physical_memory_test_and_clear_dirty(ram_addr
& TARGET_PAGE_MASK
,
962 /* update the TLB so that writes in physical page 'phys_addr' are no longer
963 tested for self modifying code */
964 void tlb_unprotect_code(ram_addr_t ram_addr
)
966 cpu_physical_memory_set_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
);
971 * Dirty write flag handling
973 * When the TCG code writes to a location it looks up the address in
974 * the TLB and uses that data to compute the final address. If any of
975 * the lower bits of the address are set then the slow path is forced.
976 * There are a number of reasons to do this but for normal RAM the
977 * most usual is detecting writes to code regions which may invalidate
980 * Other vCPUs might be reading their TLBs during guest execution, so we update
981 * te->addr_write with qatomic_set. We don't need to worry about this for
982 * oversized guests as MTTCG is disabled for them.
984 * Called with tlb_c.lock held.
986 static void tlb_reset_dirty_range_locked(CPUTLBEntry
*tlb_entry
,
987 uintptr_t start
, uintptr_t length
)
989 uintptr_t addr
= tlb_entry
->addr_write
;
991 if ((addr
& (TLB_INVALID_MASK
| TLB_MMIO
|
992 TLB_DISCARD_WRITE
| TLB_NOTDIRTY
)) == 0) {
993 addr
&= TARGET_PAGE_MASK
;
994 addr
+= tlb_entry
->addend
;
995 if ((addr
- start
) < length
) {
996 #if TCG_OVERSIZED_GUEST
997 tlb_entry
->addr_write
|= TLB_NOTDIRTY
;
999 qatomic_set(&tlb_entry
->addr_write
,
1000 tlb_entry
->addr_write
| TLB_NOTDIRTY
);
1007 * Called with tlb_c.lock held.
1008 * Called only from the vCPU context, i.e. the TLB's owner thread.
1010 static inline void copy_tlb_helper_locked(CPUTLBEntry
*d
, const CPUTLBEntry
*s
)
1015 /* This is a cross vCPU call (i.e. another vCPU resetting the flags of
1017 * We must take tlb_c.lock to avoid racing with another vCPU update. The only
1018 * thing actually updated is the target TLB entry ->addr_write flags.
1020 void tlb_reset_dirty(CPUState
*cpu
, ram_addr_t start1
, ram_addr_t length
)
1027 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1028 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1030 unsigned int n
= tlb_n_entries(&env_tlb(env
)->f
[mmu_idx
]);
1032 for (i
= 0; i
< n
; i
++) {
1033 tlb_reset_dirty_range_locked(&env_tlb(env
)->f
[mmu_idx
].table
[i
],
1037 for (i
= 0; i
< CPU_VTLB_SIZE
; i
++) {
1038 tlb_reset_dirty_range_locked(&env_tlb(env
)->d
[mmu_idx
].vtable
[i
],
1042 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1045 /* Called with tlb_c.lock held */
1046 static inline void tlb_set_dirty1_locked(CPUTLBEntry
*tlb_entry
,
1049 if (tlb_entry
->addr_write
== (vaddr
| TLB_NOTDIRTY
)) {
1050 tlb_entry
->addr_write
= vaddr
;
1054 /* update the TLB corresponding to virtual page vaddr
1055 so that it is no longer dirty */
1056 void tlb_set_dirty(CPUState
*cpu
, target_ulong vaddr
)
1058 CPUArchState
*env
= cpu
->env_ptr
;
1061 assert_cpu_is_self(cpu
);
1063 vaddr
&= TARGET_PAGE_MASK
;
1064 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1065 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1066 tlb_set_dirty1_locked(tlb_entry(env
, mmu_idx
, vaddr
), vaddr
);
1069 for (mmu_idx
= 0; mmu_idx
< NB_MMU_MODES
; mmu_idx
++) {
1071 for (k
= 0; k
< CPU_VTLB_SIZE
; k
++) {
1072 tlb_set_dirty1_locked(&env_tlb(env
)->d
[mmu_idx
].vtable
[k
], vaddr
);
1075 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1078 /* Our TLB does not support large pages, so remember the area covered by
1079 large pages and trigger a full TLB flush if these are invalidated. */
1080 static void tlb_add_large_page(CPUArchState
*env
, int mmu_idx
,
1081 target_ulong vaddr
, target_ulong size
)
1083 target_ulong lp_addr
= env_tlb(env
)->d
[mmu_idx
].large_page_addr
;
1084 target_ulong lp_mask
= ~(size
- 1);
1086 if (lp_addr
== (target_ulong
)-1) {
1087 /* No previous large page. */
1090 /* Extend the existing region to include the new page.
1091 This is a compromise between unnecessary flushes and
1092 the cost of maintaining a full variable size TLB. */
1093 lp_mask
&= env_tlb(env
)->d
[mmu_idx
].large_page_mask
;
1094 while (((lp_addr
^ vaddr
) & lp_mask
) != 0) {
1098 env_tlb(env
)->d
[mmu_idx
].large_page_addr
= lp_addr
& lp_mask
;
1099 env_tlb(env
)->d
[mmu_idx
].large_page_mask
= lp_mask
;
1103 * Add a new TLB entry. At most one entry for a given virtual address
1104 * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
1105 * supplied size is only used by tlb_flush_page.
1107 * Called from TCG-generated code, which is under an RCU read-side
1110 void tlb_set_page_full(CPUState
*cpu
, int mmu_idx
,
1111 target_ulong vaddr
, CPUTLBEntryFull
*full
)
1113 CPUArchState
*env
= cpu
->env_ptr
;
1114 CPUTLB
*tlb
= env_tlb(env
);
1115 CPUTLBDesc
*desc
= &tlb
->d
[mmu_idx
];
1116 MemoryRegionSection
*section
;
1118 target_ulong address
;
1119 target_ulong write_address
;
1121 CPUTLBEntry
*te
, tn
;
1122 hwaddr iotlb
, xlat
, sz
, paddr_page
;
1123 target_ulong vaddr_page
;
1124 int asidx
, wp_flags
, prot
;
1125 bool is_ram
, is_romd
;
1127 assert_cpu_is_self(cpu
);
1129 if (full
->lg_page_size
<= TARGET_PAGE_BITS
) {
1130 sz
= TARGET_PAGE_SIZE
;
1132 sz
= (hwaddr
)1 << full
->lg_page_size
;
1133 tlb_add_large_page(env
, mmu_idx
, vaddr
, sz
);
1135 vaddr_page
= vaddr
& TARGET_PAGE_MASK
;
1136 paddr_page
= full
->phys_addr
& TARGET_PAGE_MASK
;
1139 asidx
= cpu_asidx_from_attrs(cpu
, full
->attrs
);
1140 section
= address_space_translate_for_iotlb(cpu
, asidx
, paddr_page
,
1141 &xlat
, &sz
, full
->attrs
, &prot
);
1142 assert(sz
>= TARGET_PAGE_SIZE
);
1144 tlb_debug("vaddr=" TARGET_FMT_lx
" paddr=0x" TARGET_FMT_plx
1145 " prot=%x idx=%d\n",
1146 vaddr
, full
->phys_addr
, prot
, mmu_idx
);
1148 address
= vaddr_page
;
1149 if (full
->lg_page_size
< TARGET_PAGE_BITS
) {
1150 /* Repeat the MMU check and TLB fill on every access. */
1151 address
|= TLB_INVALID_MASK
;
1153 if (full
->attrs
.byte_swap
) {
1154 address
|= TLB_BSWAP
;
1157 is_ram
= memory_region_is_ram(section
->mr
);
1158 is_romd
= memory_region_is_romd(section
->mr
);
1160 if (is_ram
|| is_romd
) {
1161 /* RAM and ROMD both have associated host memory. */
1162 addend
= (uintptr_t)memory_region_get_ram_ptr(section
->mr
) + xlat
;
1164 /* I/O does not; force the host address to NULL. */
1168 write_address
= address
;
1170 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1172 * Computing is_clean is expensive; avoid all that unless
1173 * the page is actually writable.
1175 if (prot
& PAGE_WRITE
) {
1176 if (section
->readonly
) {
1177 write_address
|= TLB_DISCARD_WRITE
;
1178 } else if (cpu_physical_memory_is_clean(iotlb
)) {
1179 write_address
|= TLB_NOTDIRTY
;
1184 iotlb
= memory_region_section_get_iotlb(cpu
, section
) + xlat
;
1186 * Writes to romd devices must go through MMIO to enable write.
1187 * Reads to romd devices go through the ram_ptr found above,
1188 * but of course reads to I/O must go through MMIO.
1190 write_address
|= TLB_MMIO
;
1192 address
= write_address
;
1196 wp_flags
= cpu_watchpoint_address_matches(cpu
, vaddr_page
,
1199 index
= tlb_index(env
, mmu_idx
, vaddr_page
);
1200 te
= tlb_entry(env
, mmu_idx
, vaddr_page
);
1203 * Hold the TLB lock for the rest of the function. We could acquire/release
1204 * the lock several times in the function, but it is faster to amortize the
1205 * acquisition cost by acquiring it just once. Note that this leads to
1206 * a longer critical section, but this is not a concern since the TLB lock
1207 * is unlikely to be contended.
1209 qemu_spin_lock(&tlb
->c
.lock
);
1211 /* Note that the tlb is no longer clean. */
1212 tlb
->c
.dirty
|= 1 << mmu_idx
;
1214 /* Make sure there's no cached translation for the new page. */
1215 tlb_flush_vtlb_page_locked(env
, mmu_idx
, vaddr_page
);
1218 * Only evict the old entry to the victim tlb if it's for a
1219 * different page; otherwise just overwrite the stale data.
1221 if (!tlb_hit_page_anyprot(te
, vaddr_page
) && !tlb_entry_is_empty(te
)) {
1222 unsigned vidx
= desc
->vindex
++ % CPU_VTLB_SIZE
;
1223 CPUTLBEntry
*tv
= &desc
->vtable
[vidx
];
1225 /* Evict the old entry into the victim tlb. */
1226 copy_tlb_helper_locked(tv
, te
);
1227 desc
->vfulltlb
[vidx
] = desc
->fulltlb
[index
];
1228 tlb_n_used_entries_dec(env
, mmu_idx
);
1231 /* refill the tlb */
1233 * At this point iotlb contains a physical section number in the lower
1234 * TARGET_PAGE_BITS, and either
1235 * + the ram_addr_t of the page base of the target RAM (RAM)
1236 * + the offset within section->mr of the page base (I/O, ROMD)
1237 * We subtract the vaddr_page (which is page aligned and thus won't
1238 * disturb the low bits) to give an offset which can be added to the
1239 * (non-page-aligned) vaddr of the eventual memory access to get
1240 * the MemoryRegion offset for the access. Note that the vaddr we
1241 * subtract here is that of the page base, and not the same as the
1242 * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
1244 desc
->fulltlb
[index
] = *full
;
1245 desc
->fulltlb
[index
].xlat_section
= iotlb
- vaddr_page
;
1246 desc
->fulltlb
[index
].phys_addr
= paddr_page
;
1247 desc
->fulltlb
[index
].prot
= prot
;
1249 /* Now calculate the new entry */
1250 tn
.addend
= addend
- vaddr_page
;
1251 if (prot
& PAGE_READ
) {
1252 tn
.addr_read
= address
;
1253 if (wp_flags
& BP_MEM_READ
) {
1254 tn
.addr_read
|= TLB_WATCHPOINT
;
1260 if (prot
& PAGE_EXEC
) {
1261 tn
.addr_code
= address
;
1267 if (prot
& PAGE_WRITE
) {
1268 tn
.addr_write
= write_address
;
1269 if (prot
& PAGE_WRITE_INV
) {
1270 tn
.addr_write
|= TLB_INVALID_MASK
;
1272 if (wp_flags
& BP_MEM_WRITE
) {
1273 tn
.addr_write
|= TLB_WATCHPOINT
;
1277 copy_tlb_helper_locked(te
, &tn
);
1278 tlb_n_used_entries_inc(env
, mmu_idx
);
1279 qemu_spin_unlock(&tlb
->c
.lock
);
1282 void tlb_set_page_with_attrs(CPUState
*cpu
, target_ulong vaddr
,
1283 hwaddr paddr
, MemTxAttrs attrs
, int prot
,
1284 int mmu_idx
, target_ulong size
)
1286 CPUTLBEntryFull full
= {
1290 .lg_page_size
= ctz64(size
)
1293 assert(is_power_of_2(size
));
1294 tlb_set_page_full(cpu
, mmu_idx
, vaddr
, &full
);
1297 void tlb_set_page(CPUState
*cpu
, target_ulong vaddr
,
1298 hwaddr paddr
, int prot
,
1299 int mmu_idx
, target_ulong size
)
1301 tlb_set_page_with_attrs(cpu
, vaddr
, paddr
, MEMTXATTRS_UNSPECIFIED
,
1302 prot
, mmu_idx
, size
);
1306 * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
1307 * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
1308 * be discarded and looked up again (e.g. via tlb_entry()).
1310 static void tlb_fill(CPUState
*cpu
, target_ulong addr
, int size
,
1311 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
1316 * This is not a probe, so only valid return is success; failure
1317 * should result in exception + longjmp to the cpu loop.
1319 ok
= cpu
->cc
->tcg_ops
->tlb_fill(cpu
, addr
, size
,
1320 access_type
, mmu_idx
, false, retaddr
);
1324 static inline void cpu_unaligned_access(CPUState
*cpu
, vaddr addr
,
1325 MMUAccessType access_type
,
1326 int mmu_idx
, uintptr_t retaddr
)
1328 cpu
->cc
->tcg_ops
->do_unaligned_access(cpu
, addr
, access_type
,
1332 static inline void cpu_transaction_failed(CPUState
*cpu
, hwaddr physaddr
,
1333 vaddr addr
, unsigned size
,
1334 MMUAccessType access_type
,
1335 int mmu_idx
, MemTxAttrs attrs
,
1336 MemTxResult response
,
1339 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
1341 if (!cpu
->ignore_memory_transaction_failures
&&
1342 cc
->tcg_ops
->do_transaction_failed
) {
1343 cc
->tcg_ops
->do_transaction_failed(cpu
, physaddr
, addr
, size
,
1344 access_type
, mmu_idx
, attrs
,
1349 static uint64_t io_readx(CPUArchState
*env
, CPUTLBEntryFull
*full
,
1350 int mmu_idx
, target_ulong addr
, uintptr_t retaddr
,
1351 MMUAccessType access_type
, MemOp op
)
1353 CPUState
*cpu
= env_cpu(env
);
1355 MemoryRegionSection
*section
;
1358 bool locked
= false;
1361 section
= iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1363 mr_offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1364 cpu
->mem_io_pc
= retaddr
;
1365 if (!cpu
->can_do_io
) {
1366 cpu_io_recompile(cpu
, retaddr
);
1369 if (!qemu_mutex_iothread_locked()) {
1370 qemu_mutex_lock_iothread();
1373 r
= memory_region_dispatch_read(mr
, mr_offset
, &val
, op
, full
->attrs
);
1374 if (r
!= MEMTX_OK
) {
1375 hwaddr physaddr
= mr_offset
+
1376 section
->offset_within_address_space
-
1377 section
->offset_within_region
;
1379 cpu_transaction_failed(cpu
, physaddr
, addr
, memop_size(op
), access_type
,
1380 mmu_idx
, full
->attrs
, r
, retaddr
);
1383 qemu_mutex_unlock_iothread();
1390 * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin.
1391 * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
1392 * because of the side effect of io_writex changing memory layout.
1394 static void save_iotlb_data(CPUState
*cs
, MemoryRegionSection
*section
,
1397 #ifdef CONFIG_PLUGIN
1398 SavedIOTLB
*saved
= &cs
->saved_iotlb
;
1399 saved
->section
= section
;
1400 saved
->mr_offset
= mr_offset
;
1404 static void io_writex(CPUArchState
*env
, CPUTLBEntryFull
*full
,
1405 int mmu_idx
, uint64_t val
, target_ulong addr
,
1406 uintptr_t retaddr
, MemOp op
)
1408 CPUState
*cpu
= env_cpu(env
);
1410 MemoryRegionSection
*section
;
1412 bool locked
= false;
1415 section
= iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1417 mr_offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1418 if (!cpu
->can_do_io
) {
1419 cpu_io_recompile(cpu
, retaddr
);
1421 cpu
->mem_io_pc
= retaddr
;
1424 * The memory_region_dispatch may trigger a flush/resize
1425 * so for plugins we save the iotlb_data just in case.
1427 save_iotlb_data(cpu
, section
, mr_offset
);
1429 if (!qemu_mutex_iothread_locked()) {
1430 qemu_mutex_lock_iothread();
1433 r
= memory_region_dispatch_write(mr
, mr_offset
, val
, op
, full
->attrs
);
1434 if (r
!= MEMTX_OK
) {
1435 hwaddr physaddr
= mr_offset
+
1436 section
->offset_within_address_space
-
1437 section
->offset_within_region
;
1439 cpu_transaction_failed(cpu
, physaddr
, addr
, memop_size(op
),
1440 MMU_DATA_STORE
, mmu_idx
, full
->attrs
, r
,
1444 qemu_mutex_unlock_iothread();
1448 static inline target_ulong
tlb_read_ofs(CPUTLBEntry
*entry
, size_t ofs
)
1450 #if TCG_OVERSIZED_GUEST
1451 return *(target_ulong
*)((uintptr_t)entry
+ ofs
);
1453 /* ofs might correspond to .addr_write, so use qatomic_read */
1454 return qatomic_read((target_ulong
*)((uintptr_t)entry
+ ofs
));
1458 /* Return true if ADDR is present in the victim tlb, and has been copied
1459 back to the main tlb. */
1460 static bool victim_tlb_hit(CPUArchState
*env
, size_t mmu_idx
, size_t index
,
1461 size_t elt_ofs
, target_ulong page
)
1465 assert_cpu_is_self(env_cpu(env
));
1466 for (vidx
= 0; vidx
< CPU_VTLB_SIZE
; ++vidx
) {
1467 CPUTLBEntry
*vtlb
= &env_tlb(env
)->d
[mmu_idx
].vtable
[vidx
];
1470 /* elt_ofs might correspond to .addr_write, so use qatomic_read */
1471 #if TCG_OVERSIZED_GUEST
1472 cmp
= *(target_ulong
*)((uintptr_t)vtlb
+ elt_ofs
);
1474 cmp
= qatomic_read((target_ulong
*)((uintptr_t)vtlb
+ elt_ofs
));
1478 /* Found entry in victim tlb, swap tlb and iotlb. */
1479 CPUTLBEntry tmptlb
, *tlb
= &env_tlb(env
)->f
[mmu_idx
].table
[index
];
1481 qemu_spin_lock(&env_tlb(env
)->c
.lock
);
1482 copy_tlb_helper_locked(&tmptlb
, tlb
);
1483 copy_tlb_helper_locked(tlb
, vtlb
);
1484 copy_tlb_helper_locked(vtlb
, &tmptlb
);
1485 qemu_spin_unlock(&env_tlb(env
)->c
.lock
);
1487 CPUTLBEntryFull
*f1
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1488 CPUTLBEntryFull
*f2
= &env_tlb(env
)->d
[mmu_idx
].vfulltlb
[vidx
];
1489 CPUTLBEntryFull tmpf
;
1490 tmpf
= *f1
; *f1
= *f2
; *f2
= tmpf
;
1497 /* Macro to call the above, with local variables from the use context. */
1498 #define VICTIM_TLB_HIT(TY, ADDR) \
1499 victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \
1500 (ADDR) & TARGET_PAGE_MASK)
1502 static void notdirty_write(CPUState
*cpu
, vaddr mem_vaddr
, unsigned size
,
1503 CPUTLBEntryFull
*full
, uintptr_t retaddr
)
1505 ram_addr_t ram_addr
= mem_vaddr
+ full
->xlat_section
;
1507 trace_memory_notdirty_write_access(mem_vaddr
, ram_addr
, size
);
1509 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
1510 struct page_collection
*pages
1511 = page_collection_lock(ram_addr
, ram_addr
+ size
);
1512 tb_invalidate_phys_page_fast(pages
, ram_addr
, size
, retaddr
);
1513 page_collection_unlock(pages
);
1517 * Set both VGA and migration bits for simplicity and to remove
1518 * the notdirty callback faster.
1520 cpu_physical_memory_set_dirty_range(ram_addr
, size
, DIRTY_CLIENTS_NOCODE
);
1522 /* We remove the notdirty callback only if the code has been flushed. */
1523 if (!cpu_physical_memory_is_clean(ram_addr
)) {
1524 trace_memory_notdirty_set_dirty(mem_vaddr
);
1525 tlb_set_dirty(cpu
, mem_vaddr
);
1529 static int probe_access_internal(CPUArchState
*env
, target_ulong addr
,
1530 int fault_size
, MMUAccessType access_type
,
1531 int mmu_idx
, bool nonfault
,
1532 void **phost
, CPUTLBEntryFull
**pfull
,
1535 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1536 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
1537 target_ulong tlb_addr
, page_addr
;
1541 switch (access_type
) {
1543 elt_ofs
= offsetof(CPUTLBEntry
, addr_read
);
1545 case MMU_DATA_STORE
:
1546 elt_ofs
= offsetof(CPUTLBEntry
, addr_write
);
1548 case MMU_INST_FETCH
:
1549 elt_ofs
= offsetof(CPUTLBEntry
, addr_code
);
1552 g_assert_not_reached();
1554 tlb_addr
= tlb_read_ofs(entry
, elt_ofs
);
1556 flags
= TLB_FLAGS_MASK
;
1557 page_addr
= addr
& TARGET_PAGE_MASK
;
1558 if (!tlb_hit_page(tlb_addr
, page_addr
)) {
1559 if (!victim_tlb_hit(env
, mmu_idx
, index
, elt_ofs
, page_addr
)) {
1560 CPUState
*cs
= env_cpu(env
);
1562 if (!cs
->cc
->tcg_ops
->tlb_fill(cs
, addr
, fault_size
, access_type
,
1563 mmu_idx
, nonfault
, retaddr
)) {
1564 /* Non-faulting page table read failed. */
1567 return TLB_INVALID_MASK
;
1570 /* TLB resize via tlb_fill may have moved the entry. */
1571 index
= tlb_index(env
, mmu_idx
, addr
);
1572 entry
= tlb_entry(env
, mmu_idx
, addr
);
1575 * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
1576 * to force the next access through tlb_fill. We've just
1577 * called tlb_fill, so we know that this entry *is* valid.
1579 flags
&= ~TLB_INVALID_MASK
;
1581 tlb_addr
= tlb_read_ofs(entry
, elt_ofs
);
1585 *pfull
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1587 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
1588 if (unlikely(flags
& ~(TLB_WATCHPOINT
| TLB_NOTDIRTY
))) {
1593 /* Everything else is RAM. */
1594 *phost
= (void *)((uintptr_t)addr
+ entry
->addend
);
1598 int probe_access_full(CPUArchState
*env
, target_ulong addr
,
1599 MMUAccessType access_type
, int mmu_idx
,
1600 bool nonfault
, void **phost
, CPUTLBEntryFull
**pfull
,
1603 int flags
= probe_access_internal(env
, addr
, 0, access_type
, mmu_idx
,
1604 nonfault
, phost
, pfull
, retaddr
);
1606 /* Handle clean RAM pages. */
1607 if (unlikely(flags
& TLB_NOTDIRTY
)) {
1608 notdirty_write(env_cpu(env
), addr
, 1, *pfull
, retaddr
);
1609 flags
&= ~TLB_NOTDIRTY
;
1615 int probe_access_flags(CPUArchState
*env
, target_ulong addr
,
1616 MMUAccessType access_type
, int mmu_idx
,
1617 bool nonfault
, void **phost
, uintptr_t retaddr
)
1619 CPUTLBEntryFull
*full
;
1621 return probe_access_full(env
, addr
, access_type
, mmu_idx
,
1622 nonfault
, phost
, &full
, retaddr
);
1625 void *probe_access(CPUArchState
*env
, target_ulong addr
, int size
,
1626 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
1628 CPUTLBEntryFull
*full
;
1632 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
1634 flags
= probe_access_internal(env
, addr
, size
, access_type
, mmu_idx
,
1635 false, &host
, &full
, retaddr
);
1637 /* Per the interface, size == 0 merely faults the access. */
1642 if (unlikely(flags
& (TLB_NOTDIRTY
| TLB_WATCHPOINT
))) {
1643 /* Handle watchpoints. */
1644 if (flags
& TLB_WATCHPOINT
) {
1645 int wp_access
= (access_type
== MMU_DATA_STORE
1646 ? BP_MEM_WRITE
: BP_MEM_READ
);
1647 cpu_check_watchpoint(env_cpu(env
), addr
, size
,
1648 full
->attrs
, wp_access
, retaddr
);
1651 /* Handle clean RAM pages. */
1652 if (flags
& TLB_NOTDIRTY
) {
1653 notdirty_write(env_cpu(env
), addr
, 1, full
, retaddr
);
1660 void *tlb_vaddr_to_host(CPUArchState
*env
, abi_ptr addr
,
1661 MMUAccessType access_type
, int mmu_idx
)
1663 CPUTLBEntryFull
*full
;
1667 flags
= probe_access_internal(env
, addr
, 0, access_type
,
1668 mmu_idx
, true, &host
, &full
, 0);
1670 /* No combination of flags are expected by the caller. */
1671 return flags
? NULL
: host
;
1675 * Return a ram_addr_t for the virtual address for execution.
1677 * Return -1 if we can't translate and execute from an entire page
1678 * of RAM. This will force us to execute by loading and translating
1679 * one insn at a time, without caching.
1681 * NOTE: This function will trigger an exception if the page is
1684 tb_page_addr_t
get_page_addr_code_hostp(CPUArchState
*env
, target_ulong addr
,
1687 CPUTLBEntryFull
*full
;
1690 (void)probe_access_internal(env
, addr
, 1, MMU_INST_FETCH
,
1691 cpu_mmu_index(env
, true), false, &p
, &full
, 0);
1698 return qemu_ram_addr_from_host_nofail(p
);
1701 #ifdef CONFIG_PLUGIN
1703 * Perform a TLB lookup and populate the qemu_plugin_hwaddr structure.
1704 * This should be a hot path as we will have just looked this path up
1705 * in the softmmu lookup code (or helper). We don't handle re-fills or
1706 * checking the victim table. This is purely informational.
1708 * This almost never fails as the memory access being instrumented
1709 * should have just filled the TLB. The one corner case is io_writex
1710 * which can cause TLB flushes and potential resizing of the TLBs
1711 * losing the information we need. In those cases we need to recover
1712 * data from a copy of the CPUTLBEntryFull. As long as this always occurs
1713 * from the same thread (which a mem callback will be) this is safe.
1716 bool tlb_plugin_lookup(CPUState
*cpu
, target_ulong addr
, int mmu_idx
,
1717 bool is_store
, struct qemu_plugin_hwaddr
*data
)
1719 CPUArchState
*env
= cpu
->env_ptr
;
1720 CPUTLBEntry
*tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1721 uintptr_t index
= tlb_index(env
, mmu_idx
, addr
);
1722 target_ulong tlb_addr
= is_store
? tlb_addr_write(tlbe
) : tlbe
->addr_read
;
1724 if (likely(tlb_hit(tlb_addr
, addr
))) {
1725 /* We must have an iotlb entry for MMIO */
1726 if (tlb_addr
& TLB_MMIO
) {
1727 CPUTLBEntryFull
*full
;
1728 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1730 data
->v
.io
.section
=
1731 iotlb_to_section(cpu
, full
->xlat_section
, full
->attrs
);
1732 data
->v
.io
.offset
= (full
->xlat_section
& TARGET_PAGE_MASK
) + addr
;
1734 data
->is_io
= false;
1735 data
->v
.ram
.hostaddr
= (void *)((uintptr_t)addr
+ tlbe
->addend
);
1739 SavedIOTLB
*saved
= &cpu
->saved_iotlb
;
1741 data
->v
.io
.section
= saved
->section
;
1742 data
->v
.io
.offset
= saved
->mr_offset
;
1750 * Probe for an atomic operation. Do not allow unaligned operations,
1751 * or io operations to proceed. Return the host address.
1753 * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
1755 static void *atomic_mmu_lookup(CPUArchState
*env
, target_ulong addr
,
1756 MemOpIdx oi
, int size
, int prot
,
1759 uintptr_t mmu_idx
= get_mmuidx(oi
);
1760 MemOp mop
= get_memop(oi
);
1761 int a_bits
= get_alignment_bits(mop
);
1764 target_ulong tlb_addr
;
1767 tcg_debug_assert(mmu_idx
< NB_MMU_MODES
);
1769 /* Adjust the given return address. */
1770 retaddr
-= GETPC_ADJ
;
1772 /* Enforce guest required alignment. */
1773 if (unlikely(a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)))) {
1774 /* ??? Maybe indicate atomic op to cpu_unaligned_access */
1775 cpu_unaligned_access(env_cpu(env
), addr
, MMU_DATA_STORE
,
1779 /* Enforce qemu required alignment. */
1780 if (unlikely(addr
& (size
- 1))) {
1781 /* We get here if guest alignment was not requested,
1782 or was not enforced by cpu_unaligned_access above.
1783 We might widen the access and emulate, but for now
1784 mark an exception and exit the cpu loop. */
1785 goto stop_the_world
;
1788 index
= tlb_index(env
, mmu_idx
, addr
);
1789 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1791 /* Check TLB entry and enforce page permissions. */
1792 if (prot
& PAGE_WRITE
) {
1793 tlb_addr
= tlb_addr_write(tlbe
);
1794 if (!tlb_hit(tlb_addr
, addr
)) {
1795 if (!VICTIM_TLB_HIT(addr_write
, addr
)) {
1796 tlb_fill(env_cpu(env
), addr
, size
,
1797 MMU_DATA_STORE
, mmu_idx
, retaddr
);
1798 index
= tlb_index(env
, mmu_idx
, addr
);
1799 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1801 tlb_addr
= tlb_addr_write(tlbe
) & ~TLB_INVALID_MASK
;
1804 /* Let the guest notice RMW on a write-only page. */
1805 if ((prot
& PAGE_READ
) &&
1806 unlikely(tlbe
->addr_read
!= (tlb_addr
& ~TLB_NOTDIRTY
))) {
1807 tlb_fill(env_cpu(env
), addr
, size
,
1808 MMU_DATA_LOAD
, mmu_idx
, retaddr
);
1810 * Since we don't support reads and writes to different addresses,
1811 * and we do have the proper page loaded for write, this shouldn't
1812 * ever return. But just in case, handle via stop-the-world.
1814 goto stop_the_world
;
1816 } else /* if (prot & PAGE_READ) */ {
1817 tlb_addr
= tlbe
->addr_read
;
1818 if (!tlb_hit(tlb_addr
, addr
)) {
1819 if (!VICTIM_TLB_HIT(addr_write
, addr
)) {
1820 tlb_fill(env_cpu(env
), addr
, size
,
1821 MMU_DATA_LOAD
, mmu_idx
, retaddr
);
1822 index
= tlb_index(env
, mmu_idx
, addr
);
1823 tlbe
= tlb_entry(env
, mmu_idx
, addr
);
1825 tlb_addr
= tlbe
->addr_read
& ~TLB_INVALID_MASK
;
1829 /* Notice an IO access or a needs-MMU-lookup access */
1830 if (unlikely(tlb_addr
& TLB_MMIO
)) {
1831 /* There's really nothing that can be done to
1832 support this apart from stop-the-world. */
1833 goto stop_the_world
;
1836 hostaddr
= (void *)((uintptr_t)addr
+ tlbe
->addend
);
1838 if (unlikely(tlb_addr
& TLB_NOTDIRTY
)) {
1839 notdirty_write(env_cpu(env
), addr
, size
,
1840 &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
], retaddr
);
1846 cpu_loop_exit_atomic(env_cpu(env
), retaddr
);
1850 * Verify that we have passed the correct MemOp to the correct function.
1852 * In the case of the helper_*_mmu functions, we will have done this by
1853 * using the MemOp to look up the helper during code generation.
1855 * In the case of the cpu_*_mmu functions, this is up to the caller.
1856 * We could present one function to target code, and dispatch based on
1857 * the MemOp, but so far we have worked hard to avoid an indirect function
1858 * call along the memory path.
1860 static void validate_memop(MemOpIdx oi
, MemOp expected
)
1862 #ifdef CONFIG_DEBUG_TCG
1863 MemOp have
= get_memop(oi
) & (MO_SIZE
| MO_BSWAP
);
1864 assert(have
== expected
);
1871 * We support two different access types. SOFTMMU_CODE_ACCESS is
1872 * specifically for reading instructions from system memory. It is
1873 * called by the translation loop and in some helpers where the code
1874 * is disassembled. It shouldn't be called directly by guest code.
1877 typedef uint64_t FullLoadHelper(CPUArchState
*env
, target_ulong addr
,
1878 MemOpIdx oi
, uintptr_t retaddr
);
1880 static inline uint64_t QEMU_ALWAYS_INLINE
1881 load_memop(const void *haddr
, MemOp op
)
1885 return ldub_p(haddr
);
1887 return lduw_be_p(haddr
);
1889 return lduw_le_p(haddr
);
1891 return (uint32_t)ldl_be_p(haddr
);
1893 return (uint32_t)ldl_le_p(haddr
);
1895 return ldq_be_p(haddr
);
1897 return ldq_le_p(haddr
);
1899 qemu_build_not_reached();
1903 static inline uint64_t QEMU_ALWAYS_INLINE
1904 load_helper(CPUArchState
*env
, target_ulong addr
, MemOpIdx oi
,
1905 uintptr_t retaddr
, MemOp op
, bool code_read
,
1906 FullLoadHelper
*full_load
)
1908 const size_t tlb_off
= code_read
?
1909 offsetof(CPUTLBEntry
, addr_code
) : offsetof(CPUTLBEntry
, addr_read
);
1910 const MMUAccessType access_type
=
1911 code_read
? MMU_INST_FETCH
: MMU_DATA_LOAD
;
1912 const unsigned a_bits
= get_alignment_bits(get_memop(oi
));
1913 const size_t size
= memop_size(op
);
1914 uintptr_t mmu_idx
= get_mmuidx(oi
);
1917 target_ulong tlb_addr
;
1921 tcg_debug_assert(mmu_idx
< NB_MMU_MODES
);
1923 /* Handle CPU specific unaligned behaviour */
1924 if (addr
& ((1 << a_bits
) - 1)) {
1925 cpu_unaligned_access(env_cpu(env
), addr
, access_type
,
1929 index
= tlb_index(env
, mmu_idx
, addr
);
1930 entry
= tlb_entry(env
, mmu_idx
, addr
);
1931 tlb_addr
= code_read
? entry
->addr_code
: entry
->addr_read
;
1933 /* If the TLB entry is for a different page, reload and try again. */
1934 if (!tlb_hit(tlb_addr
, addr
)) {
1935 if (!victim_tlb_hit(env
, mmu_idx
, index
, tlb_off
,
1936 addr
& TARGET_PAGE_MASK
)) {
1937 tlb_fill(env_cpu(env
), addr
, size
,
1938 access_type
, mmu_idx
, retaddr
);
1939 index
= tlb_index(env
, mmu_idx
, addr
);
1940 entry
= tlb_entry(env
, mmu_idx
, addr
);
1942 tlb_addr
= code_read
? entry
->addr_code
: entry
->addr_read
;
1943 tlb_addr
&= ~TLB_INVALID_MASK
;
1946 /* Handle anything that isn't just a straight memory access. */
1947 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
1948 CPUTLBEntryFull
*full
;
1951 /* For anything that is unaligned, recurse through full_load. */
1952 if ((addr
& (size
- 1)) != 0) {
1953 goto do_unaligned_access
;
1956 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
1958 /* Handle watchpoints. */
1959 if (unlikely(tlb_addr
& TLB_WATCHPOINT
)) {
1960 /* On watchpoint hit, this will longjmp out. */
1961 cpu_check_watchpoint(env_cpu(env
), addr
, size
,
1962 full
->attrs
, BP_MEM_READ
, retaddr
);
1965 need_swap
= size
> 1 && (tlb_addr
& TLB_BSWAP
);
1967 /* Handle I/O access. */
1968 if (likely(tlb_addr
& TLB_MMIO
)) {
1969 return io_readx(env
, full
, mmu_idx
, addr
, retaddr
,
1970 access_type
, op
^ (need_swap
* MO_BSWAP
));
1973 haddr
= (void *)((uintptr_t)addr
+ entry
->addend
);
1976 * Keep these two load_memop separate to ensure that the compiler
1977 * is able to fold the entire function to a single instruction.
1978 * There is a build-time assert inside to remind you of this. ;-)
1980 if (unlikely(need_swap
)) {
1981 return load_memop(haddr
, op
^ MO_BSWAP
);
1983 return load_memop(haddr
, op
);
1986 /* Handle slow unaligned access (it spans two pages or IO). */
1988 && unlikely((addr
& ~TARGET_PAGE_MASK
) + size
- 1
1989 >= TARGET_PAGE_SIZE
)) {
1990 target_ulong addr1
, addr2
;
1993 do_unaligned_access
:
1994 addr1
= addr
& ~((target_ulong
)size
- 1);
1995 addr2
= addr1
+ size
;
1996 r1
= full_load(env
, addr1
, oi
, retaddr
);
1997 r2
= full_load(env
, addr2
, oi
, retaddr
);
1998 shift
= (addr
& (size
- 1)) * 8;
2000 if (memop_big_endian(op
)) {
2001 /* Big-endian combine. */
2002 res
= (r1
<< shift
) | (r2
>> ((size
* 8) - shift
));
2004 /* Little-endian combine. */
2005 res
= (r1
>> shift
) | (r2
<< ((size
* 8) - shift
));
2007 return res
& MAKE_64BIT_MASK(0, size
* 8);
2010 haddr
= (void *)((uintptr_t)addr
+ entry
->addend
);
2011 return load_memop(haddr
, op
);
2015 * For the benefit of TCG generated code, we want to avoid the
2016 * complication of ABI-specific return type promotion and always
2017 * return a value extended to the register size of the host. This is
2018 * tcg_target_long, except in the case of a 32-bit host and 64-bit
2019 * data, and for that we always have uint64_t.
2021 * We don't bother with this widened value for SOFTMMU_CODE_ACCESS.
2024 static uint64_t full_ldub_mmu(CPUArchState
*env
, target_ulong addr
,
2025 MemOpIdx oi
, uintptr_t retaddr
)
2027 validate_memop(oi
, MO_UB
);
2028 return load_helper(env
, addr
, oi
, retaddr
, MO_UB
, false, full_ldub_mmu
);
2031 tcg_target_ulong
helper_ret_ldub_mmu(CPUArchState
*env
, target_ulong addr
,
2032 MemOpIdx oi
, uintptr_t retaddr
)
2034 return full_ldub_mmu(env
, addr
, oi
, retaddr
);
2037 static uint64_t full_le_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
2038 MemOpIdx oi
, uintptr_t retaddr
)
2040 validate_memop(oi
, MO_LEUW
);
2041 return load_helper(env
, addr
, oi
, retaddr
, MO_LEUW
, false,
2045 tcg_target_ulong
helper_le_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
2046 MemOpIdx oi
, uintptr_t retaddr
)
2048 return full_le_lduw_mmu(env
, addr
, oi
, retaddr
);
2051 static uint64_t full_be_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
2052 MemOpIdx oi
, uintptr_t retaddr
)
2054 validate_memop(oi
, MO_BEUW
);
2055 return load_helper(env
, addr
, oi
, retaddr
, MO_BEUW
, false,
2059 tcg_target_ulong
helper_be_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
2060 MemOpIdx oi
, uintptr_t retaddr
)
2062 return full_be_lduw_mmu(env
, addr
, oi
, retaddr
);
2065 static uint64_t full_le_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
2066 MemOpIdx oi
, uintptr_t retaddr
)
2068 validate_memop(oi
, MO_LEUL
);
2069 return load_helper(env
, addr
, oi
, retaddr
, MO_LEUL
, false,
2073 tcg_target_ulong
helper_le_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
2074 MemOpIdx oi
, uintptr_t retaddr
)
2076 return full_le_ldul_mmu(env
, addr
, oi
, retaddr
);
2079 static uint64_t full_be_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
2080 MemOpIdx oi
, uintptr_t retaddr
)
2082 validate_memop(oi
, MO_BEUL
);
2083 return load_helper(env
, addr
, oi
, retaddr
, MO_BEUL
, false,
2087 tcg_target_ulong
helper_be_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
2088 MemOpIdx oi
, uintptr_t retaddr
)
2090 return full_be_ldul_mmu(env
, addr
, oi
, retaddr
);
2093 uint64_t helper_le_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
2094 MemOpIdx oi
, uintptr_t retaddr
)
2096 validate_memop(oi
, MO_LEUQ
);
2097 return load_helper(env
, addr
, oi
, retaddr
, MO_LEUQ
, false,
2101 uint64_t helper_be_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
2102 MemOpIdx oi
, uintptr_t retaddr
)
2104 validate_memop(oi
, MO_BEUQ
);
2105 return load_helper(env
, addr
, oi
, retaddr
, MO_BEUQ
, false,
2110 * Provide signed versions of the load routines as well. We can of course
2111 * avoid this for 64-bit data, or for 32-bit data on 32-bit host.
2115 tcg_target_ulong
helper_ret_ldsb_mmu(CPUArchState
*env
, target_ulong addr
,
2116 MemOpIdx oi
, uintptr_t retaddr
)
2118 return (int8_t)helper_ret_ldub_mmu(env
, addr
, oi
, retaddr
);
2121 tcg_target_ulong
helper_le_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
2122 MemOpIdx oi
, uintptr_t retaddr
)
2124 return (int16_t)helper_le_lduw_mmu(env
, addr
, oi
, retaddr
);
2127 tcg_target_ulong
helper_be_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
2128 MemOpIdx oi
, uintptr_t retaddr
)
2130 return (int16_t)helper_be_lduw_mmu(env
, addr
, oi
, retaddr
);
2133 tcg_target_ulong
helper_le_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
2134 MemOpIdx oi
, uintptr_t retaddr
)
2136 return (int32_t)helper_le_ldul_mmu(env
, addr
, oi
, retaddr
);
2139 tcg_target_ulong
helper_be_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
2140 MemOpIdx oi
, uintptr_t retaddr
)
2142 return (int32_t)helper_be_ldul_mmu(env
, addr
, oi
, retaddr
);
2146 * Load helpers for cpu_ldst.h.
2149 static inline uint64_t cpu_load_helper(CPUArchState
*env
, abi_ptr addr
,
2150 MemOpIdx oi
, uintptr_t retaddr
,
2151 FullLoadHelper
*full_load
)
2155 ret
= full_load(env
, addr
, oi
, retaddr
);
2156 qemu_plugin_vcpu_mem_cb(env_cpu(env
), addr
, oi
, QEMU_PLUGIN_MEM_R
);
2160 uint8_t cpu_ldb_mmu(CPUArchState
*env
, abi_ptr addr
, MemOpIdx oi
, uintptr_t ra
)
2162 return cpu_load_helper(env
, addr
, oi
, ra
, full_ldub_mmu
);
2165 uint16_t cpu_ldw_be_mmu(CPUArchState
*env
, abi_ptr addr
,
2166 MemOpIdx oi
, uintptr_t ra
)
2168 return cpu_load_helper(env
, addr
, oi
, ra
, full_be_lduw_mmu
);
2171 uint32_t cpu_ldl_be_mmu(CPUArchState
*env
, abi_ptr addr
,
2172 MemOpIdx oi
, uintptr_t ra
)
2174 return cpu_load_helper(env
, addr
, oi
, ra
, full_be_ldul_mmu
);
2177 uint64_t cpu_ldq_be_mmu(CPUArchState
*env
, abi_ptr addr
,
2178 MemOpIdx oi
, uintptr_t ra
)
2180 return cpu_load_helper(env
, addr
, oi
, ra
, helper_be_ldq_mmu
);
2183 uint16_t cpu_ldw_le_mmu(CPUArchState
*env
, abi_ptr addr
,
2184 MemOpIdx oi
, uintptr_t ra
)
2186 return cpu_load_helper(env
, addr
, oi
, ra
, full_le_lduw_mmu
);
2189 uint32_t cpu_ldl_le_mmu(CPUArchState
*env
, abi_ptr addr
,
2190 MemOpIdx oi
, uintptr_t ra
)
2192 return cpu_load_helper(env
, addr
, oi
, ra
, full_le_ldul_mmu
);
2195 uint64_t cpu_ldq_le_mmu(CPUArchState
*env
, abi_ptr addr
,
2196 MemOpIdx oi
, uintptr_t ra
)
2198 return cpu_load_helper(env
, addr
, oi
, ra
, helper_le_ldq_mmu
);
2205 static inline void QEMU_ALWAYS_INLINE
2206 store_memop(void *haddr
, uint64_t val
, MemOp op
)
2213 stw_be_p(haddr
, val
);
2216 stw_le_p(haddr
, val
);
2219 stl_be_p(haddr
, val
);
2222 stl_le_p(haddr
, val
);
2225 stq_be_p(haddr
, val
);
2228 stq_le_p(haddr
, val
);
2231 qemu_build_not_reached();
2235 static void full_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2236 MemOpIdx oi
, uintptr_t retaddr
);
2238 static void __attribute__((noinline
))
2239 store_helper_unaligned(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2240 uintptr_t retaddr
, size_t size
, uintptr_t mmu_idx
,
2243 const size_t tlb_off
= offsetof(CPUTLBEntry
, addr_write
);
2244 uintptr_t index
, index2
;
2245 CPUTLBEntry
*entry
, *entry2
;
2246 target_ulong page1
, page2
, tlb_addr
, tlb_addr2
;
2252 * Ensure the second page is in the TLB. Note that the first page
2253 * is already guaranteed to be filled, and that the second page
2254 * cannot evict the first. An exception to this rule is PAGE_WRITE_INV
2255 * handling: the first page could have evicted itself.
2257 page1
= addr
& TARGET_PAGE_MASK
;
2258 page2
= (addr
+ size
) & TARGET_PAGE_MASK
;
2259 size2
= (addr
+ size
) & ~TARGET_PAGE_MASK
;
2260 index2
= tlb_index(env
, mmu_idx
, page2
);
2261 entry2
= tlb_entry(env
, mmu_idx
, page2
);
2263 tlb_addr2
= tlb_addr_write(entry2
);
2264 if (page1
!= page2
&& !tlb_hit_page(tlb_addr2
, page2
)) {
2265 if (!victim_tlb_hit(env
, mmu_idx
, index2
, tlb_off
, page2
)) {
2266 tlb_fill(env_cpu(env
), page2
, size2
, MMU_DATA_STORE
,
2268 index2
= tlb_index(env
, mmu_idx
, page2
);
2269 entry2
= tlb_entry(env
, mmu_idx
, page2
);
2271 tlb_addr2
= tlb_addr_write(entry2
);
2274 index
= tlb_index(env
, mmu_idx
, addr
);
2275 entry
= tlb_entry(env
, mmu_idx
, addr
);
2276 tlb_addr
= tlb_addr_write(entry
);
2279 * Handle watchpoints. Since this may trap, all checks
2280 * must happen before any store.
2282 if (unlikely(tlb_addr
& TLB_WATCHPOINT
)) {
2283 cpu_check_watchpoint(env_cpu(env
), addr
, size
- size2
,
2284 env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
].attrs
,
2285 BP_MEM_WRITE
, retaddr
);
2287 if (unlikely(tlb_addr2
& TLB_WATCHPOINT
)) {
2288 cpu_check_watchpoint(env_cpu(env
), page2
, size2
,
2289 env_tlb(env
)->d
[mmu_idx
].fulltlb
[index2
].attrs
,
2290 BP_MEM_WRITE
, retaddr
);
2294 * XXX: not efficient, but simple.
2295 * This loop must go in the forward direction to avoid issues
2296 * with self-modifying code in Windows 64-bit.
2298 oi
= make_memop_idx(MO_UB
, mmu_idx
);
2300 for (i
= 0; i
< size
; ++i
) {
2301 /* Big-endian extract. */
2302 uint8_t val8
= val
>> (((size
- 1) * 8) - (i
* 8));
2303 full_stb_mmu(env
, addr
+ i
, val8
, oi
, retaddr
);
2306 for (i
= 0; i
< size
; ++i
) {
2307 /* Little-endian extract. */
2308 uint8_t val8
= val
>> (i
* 8);
2309 full_stb_mmu(env
, addr
+ i
, val8
, oi
, retaddr
);
2314 static inline void QEMU_ALWAYS_INLINE
2315 store_helper(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2316 MemOpIdx oi
, uintptr_t retaddr
, MemOp op
)
2318 const size_t tlb_off
= offsetof(CPUTLBEntry
, addr_write
);
2319 const unsigned a_bits
= get_alignment_bits(get_memop(oi
));
2320 const size_t size
= memop_size(op
);
2321 uintptr_t mmu_idx
= get_mmuidx(oi
);
2324 target_ulong tlb_addr
;
2327 tcg_debug_assert(mmu_idx
< NB_MMU_MODES
);
2329 /* Handle CPU specific unaligned behaviour */
2330 if (addr
& ((1 << a_bits
) - 1)) {
2331 cpu_unaligned_access(env_cpu(env
), addr
, MMU_DATA_STORE
,
2335 index
= tlb_index(env
, mmu_idx
, addr
);
2336 entry
= tlb_entry(env
, mmu_idx
, addr
);
2337 tlb_addr
= tlb_addr_write(entry
);
2339 /* If the TLB entry is for a different page, reload and try again. */
2340 if (!tlb_hit(tlb_addr
, addr
)) {
2341 if (!victim_tlb_hit(env
, mmu_idx
, index
, tlb_off
,
2342 addr
& TARGET_PAGE_MASK
)) {
2343 tlb_fill(env_cpu(env
), addr
, size
, MMU_DATA_STORE
,
2345 index
= tlb_index(env
, mmu_idx
, addr
);
2346 entry
= tlb_entry(env
, mmu_idx
, addr
);
2348 tlb_addr
= tlb_addr_write(entry
) & ~TLB_INVALID_MASK
;
2351 /* Handle anything that isn't just a straight memory access. */
2352 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
2353 CPUTLBEntryFull
*full
;
2356 /* For anything that is unaligned, recurse through byte stores. */
2357 if ((addr
& (size
- 1)) != 0) {
2358 goto do_unaligned_access
;
2361 full
= &env_tlb(env
)->d
[mmu_idx
].fulltlb
[index
];
2363 /* Handle watchpoints. */
2364 if (unlikely(tlb_addr
& TLB_WATCHPOINT
)) {
2365 /* On watchpoint hit, this will longjmp out. */
2366 cpu_check_watchpoint(env_cpu(env
), addr
, size
,
2367 full
->attrs
, BP_MEM_WRITE
, retaddr
);
2370 need_swap
= size
> 1 && (tlb_addr
& TLB_BSWAP
);
2372 /* Handle I/O access. */
2373 if (tlb_addr
& TLB_MMIO
) {
2374 io_writex(env
, full
, mmu_idx
, val
, addr
, retaddr
,
2375 op
^ (need_swap
* MO_BSWAP
));
2379 /* Ignore writes to ROM. */
2380 if (unlikely(tlb_addr
& TLB_DISCARD_WRITE
)) {
2384 /* Handle clean RAM pages. */
2385 if (tlb_addr
& TLB_NOTDIRTY
) {
2386 notdirty_write(env_cpu(env
), addr
, size
, full
, retaddr
);
2389 haddr
= (void *)((uintptr_t)addr
+ entry
->addend
);
2392 * Keep these two store_memop separate to ensure that the compiler
2393 * is able to fold the entire function to a single instruction.
2394 * There is a build-time assert inside to remind you of this. ;-)
2396 if (unlikely(need_swap
)) {
2397 store_memop(haddr
, val
, op
^ MO_BSWAP
);
2399 store_memop(haddr
, val
, op
);
2404 /* Handle slow unaligned access (it spans two pages or IO). */
2406 && unlikely((addr
& ~TARGET_PAGE_MASK
) + size
- 1
2407 >= TARGET_PAGE_SIZE
)) {
2408 do_unaligned_access
:
2409 store_helper_unaligned(env
, addr
, val
, retaddr
, size
,
2410 mmu_idx
, memop_big_endian(op
));
2414 haddr
= (void *)((uintptr_t)addr
+ entry
->addend
);
2415 store_memop(haddr
, val
, op
);
2418 static void __attribute__((noinline
))
2419 full_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2420 MemOpIdx oi
, uintptr_t retaddr
)
2422 validate_memop(oi
, MO_UB
);
2423 store_helper(env
, addr
, val
, oi
, retaddr
, MO_UB
);
2426 void helper_ret_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint8_t val
,
2427 MemOpIdx oi
, uintptr_t retaddr
)
2429 full_stb_mmu(env
, addr
, val
, oi
, retaddr
);
2432 static void full_le_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2433 MemOpIdx oi
, uintptr_t retaddr
)
2435 validate_memop(oi
, MO_LEUW
);
2436 store_helper(env
, addr
, val
, oi
, retaddr
, MO_LEUW
);
2439 void helper_le_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
2440 MemOpIdx oi
, uintptr_t retaddr
)
2442 full_le_stw_mmu(env
, addr
, val
, oi
, retaddr
);
2445 static void full_be_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2446 MemOpIdx oi
, uintptr_t retaddr
)
2448 validate_memop(oi
, MO_BEUW
);
2449 store_helper(env
, addr
, val
, oi
, retaddr
, MO_BEUW
);
2452 void helper_be_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
2453 MemOpIdx oi
, uintptr_t retaddr
)
2455 full_be_stw_mmu(env
, addr
, val
, oi
, retaddr
);
2458 static void full_le_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2459 MemOpIdx oi
, uintptr_t retaddr
)
2461 validate_memop(oi
, MO_LEUL
);
2462 store_helper(env
, addr
, val
, oi
, retaddr
, MO_LEUL
);
2465 void helper_le_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
2466 MemOpIdx oi
, uintptr_t retaddr
)
2468 full_le_stl_mmu(env
, addr
, val
, oi
, retaddr
);
2471 static void full_be_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2472 MemOpIdx oi
, uintptr_t retaddr
)
2474 validate_memop(oi
, MO_BEUL
);
2475 store_helper(env
, addr
, val
, oi
, retaddr
, MO_BEUL
);
2478 void helper_be_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
2479 MemOpIdx oi
, uintptr_t retaddr
)
2481 full_be_stl_mmu(env
, addr
, val
, oi
, retaddr
);
2484 void helper_le_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2485 MemOpIdx oi
, uintptr_t retaddr
)
2487 validate_memop(oi
, MO_LEUQ
);
2488 store_helper(env
, addr
, val
, oi
, retaddr
, MO_LEUQ
);
2491 void helper_be_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2492 MemOpIdx oi
, uintptr_t retaddr
)
2494 validate_memop(oi
, MO_BEUQ
);
2495 store_helper(env
, addr
, val
, oi
, retaddr
, MO_BEUQ
);
2499 * Store Helpers for cpu_ldst.h
2502 typedef void FullStoreHelper(CPUArchState
*env
, target_ulong addr
,
2503 uint64_t val
, MemOpIdx oi
, uintptr_t retaddr
);
2505 static inline void cpu_store_helper(CPUArchState
*env
, target_ulong addr
,
2506 uint64_t val
, MemOpIdx oi
, uintptr_t ra
,
2507 FullStoreHelper
*full_store
)
2509 full_store(env
, addr
, val
, oi
, ra
);
2510 qemu_plugin_vcpu_mem_cb(env_cpu(env
), addr
, oi
, QEMU_PLUGIN_MEM_W
);
2513 void cpu_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint8_t val
,
2514 MemOpIdx oi
, uintptr_t retaddr
)
2516 cpu_store_helper(env
, addr
, val
, oi
, retaddr
, full_stb_mmu
);
2519 void cpu_stw_be_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
2520 MemOpIdx oi
, uintptr_t retaddr
)
2522 cpu_store_helper(env
, addr
, val
, oi
, retaddr
, full_be_stw_mmu
);
2525 void cpu_stl_be_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
2526 MemOpIdx oi
, uintptr_t retaddr
)
2528 cpu_store_helper(env
, addr
, val
, oi
, retaddr
, full_be_stl_mmu
);
2531 void cpu_stq_be_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2532 MemOpIdx oi
, uintptr_t retaddr
)
2534 cpu_store_helper(env
, addr
, val
, oi
, retaddr
, helper_be_stq_mmu
);
2537 void cpu_stw_le_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
2538 MemOpIdx oi
, uintptr_t retaddr
)
2540 cpu_store_helper(env
, addr
, val
, oi
, retaddr
, full_le_stw_mmu
);
2543 void cpu_stl_le_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
2544 MemOpIdx oi
, uintptr_t retaddr
)
2546 cpu_store_helper(env
, addr
, val
, oi
, retaddr
, full_le_stl_mmu
);
2549 void cpu_stq_le_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
2550 MemOpIdx oi
, uintptr_t retaddr
)
2552 cpu_store_helper(env
, addr
, val
, oi
, retaddr
, helper_le_stq_mmu
);
2555 #include "ldst_common.c.inc"
2558 * First set of functions passes in OI and RETADDR.
2559 * This makes them callable from other helpers.
2562 #define ATOMIC_NAME(X) \
2563 glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
2565 #define ATOMIC_MMU_CLEANUP
2567 #include "atomic_common.c.inc"
2570 #include "atomic_template.h"
2573 #include "atomic_template.h"
2576 #include "atomic_template.h"
2578 #ifdef CONFIG_ATOMIC64
2580 #include "atomic_template.h"
2583 #if HAVE_CMPXCHG128 || HAVE_ATOMIC128
2584 #define DATA_SIZE 16
2585 #include "atomic_template.h"
2588 /* Code access functions. */
2590 static uint64_t full_ldub_code(CPUArchState
*env
, target_ulong addr
,
2591 MemOpIdx oi
, uintptr_t retaddr
)
2593 return load_helper(env
, addr
, oi
, retaddr
, MO_8
, true, full_ldub_code
);
2596 uint32_t cpu_ldub_code(CPUArchState
*env
, abi_ptr addr
)
2598 MemOpIdx oi
= make_memop_idx(MO_UB
, cpu_mmu_index(env
, true));
2599 return full_ldub_code(env
, addr
, oi
, 0);
2602 static uint64_t full_lduw_code(CPUArchState
*env
, target_ulong addr
,
2603 MemOpIdx oi
, uintptr_t retaddr
)
2605 return load_helper(env
, addr
, oi
, retaddr
, MO_TEUW
, true, full_lduw_code
);
2608 uint32_t cpu_lduw_code(CPUArchState
*env
, abi_ptr addr
)
2610 MemOpIdx oi
= make_memop_idx(MO_TEUW
, cpu_mmu_index(env
, true));
2611 return full_lduw_code(env
, addr
, oi
, 0);
2614 static uint64_t full_ldl_code(CPUArchState
*env
, target_ulong addr
,
2615 MemOpIdx oi
, uintptr_t retaddr
)
2617 return load_helper(env
, addr
, oi
, retaddr
, MO_TEUL
, true, full_ldl_code
);
2620 uint32_t cpu_ldl_code(CPUArchState
*env
, abi_ptr addr
)
2622 MemOpIdx oi
= make_memop_idx(MO_TEUL
, cpu_mmu_index(env
, true));
2623 return full_ldl_code(env
, addr
, oi
, 0);
2626 static uint64_t full_ldq_code(CPUArchState
*env
, target_ulong addr
,
2627 MemOpIdx oi
, uintptr_t retaddr
)
2629 return load_helper(env
, addr
, oi
, retaddr
, MO_TEUQ
, true, full_ldq_code
);
2632 uint64_t cpu_ldq_code(CPUArchState
*env
, abi_ptr addr
)
2634 MemOpIdx oi
= make_memop_idx(MO_TEUQ
, cpu_mmu_index(env
, true));
2635 return full_ldq_code(env
, addr
, oi
, 0);