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git.proxmox.com Git - mirror_qemu.git/blob - accel/tcg/user-exec.c
2 * User emulator execution
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "disas/disas.h"
22 #include "exec/exec-all.h"
24 #include "qemu/bitops.h"
25 #include "exec/cpu_ldst.h"
26 #include "translate-all.h"
27 #include "exec/helper-proto.h"
39 #include <sys/ucontext.h>
42 __thread
uintptr_t helper_retaddr
;
44 //#define DEBUG_SIGNAL
46 /* exit the current TB from a signal handler. The host registers are
47 restored in a state compatible with the CPU emulator
49 static void cpu_exit_tb_from_sighandler(CPUState
*cpu
, sigset_t
*old_set
)
51 /* XXX: use siglongjmp ? */
52 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
53 cpu_loop_exit_noexc(cpu
);
56 /* 'pc' is the host PC at which the exception was raised. 'address' is
57 the effective address of the memory exception. 'is_write' is 1 if a
58 write caused the exception and otherwise 0'. 'old_set' is the
59 signal set which should be restored */
60 static inline int handle_cpu_signal(uintptr_t pc
, unsigned long address
,
61 int is_write
, sigset_t
*old_set
)
63 CPUState
*cpu
= current_cpu
;
67 /* We must handle PC addresses from two different sources:
68 * a call return address and a signal frame address.
70 * Within cpu_restore_state_from_tb we assume the former and adjust
71 * the address by -GETPC_ADJ so that the address is within the call
72 * insn so that addr does not accidentally match the beginning of the
75 * However, when the PC comes from the signal frame, it points to
76 * the actual faulting host insn and not a call insn. Subtracting
77 * GETPC_ADJ in that case may accidentally match the previous guest insn.
79 * So for the later case, adjust forward to compensate for what
80 * will be done later by cpu_restore_state_from_tb.
88 /* For synchronous signals we expect to be coming from the vCPU
89 * thread (so current_cpu should be valid) and either from running
90 * code or during translation which can fault as we cross pages.
92 * If neither is true then something has gone wrong and we should
93 * abort rather than try and restart the vCPU execution.
95 if (!cpu
|| !cpu
->running
) {
96 printf("qemu:%s received signal outside vCPU context @ pc=0x%"
97 PRIxPTR
"\n", __func__
, pc
);
101 #if defined(DEBUG_SIGNAL)
102 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
103 pc
, address
, is_write
, *(unsigned long *)old_set
);
105 /* XXX: locking issue */
106 if (is_write
&& h2g_valid(address
)) {
107 switch (page_unprotect(h2g(address
), pc
)) {
109 /* Fault not caused by a page marked unwritable to protect
110 * cached translations, must be the guest binary's problem.
114 /* Fault caused by protection of cached translation; TBs
115 * invalidated, so resume execution. Retain helper_retaddr
116 * for a possible second fault.
120 /* Fault caused by protection of cached translation, and the
121 * currently executing TB was modified and must be exited
122 * immediately. Clear helper_retaddr for next execution.
125 cpu_exit_tb_from_sighandler(cpu
, old_set
);
129 g_assert_not_reached();
133 /* Convert forcefully to guest address space, invalid addresses
134 are still valid segv ones */
135 address
= h2g_nocheck(address
);
137 cc
= CPU_GET_CLASS(cpu
);
138 /* see if it is an MMU fault */
139 g_assert(cc
->handle_mmu_fault
);
140 ret
= cc
->handle_mmu_fault(cpu
, address
, is_write
, MMU_USER_IDX
);
143 /* The MMU fault was handled without causing real CPU fault.
144 * Retain helper_retaddr for a possible second fault.
149 /* All other paths lead to cpu_exit; clear helper_retaddr
150 * for next execution.
155 return 0; /* not an MMU fault */
158 /* Now we have a real cpu fault. */
159 cpu_restore_state(cpu
, pc
);
161 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
164 /* never comes here */
168 #if defined(__i386__)
170 #if defined(__NetBSD__)
171 #include <ucontext.h>
173 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
174 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
175 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
176 #define MASK_sig(context) ((context)->uc_sigmask)
177 #elif defined(__FreeBSD__) || defined(__DragonFly__)
178 #include <ucontext.h>
180 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
181 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
182 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
183 #define MASK_sig(context) ((context)->uc_sigmask)
184 #elif defined(__OpenBSD__)
185 #define EIP_sig(context) ((context)->sc_eip)
186 #define TRAP_sig(context) ((context)->sc_trapno)
187 #define ERROR_sig(context) ((context)->sc_err)
188 #define MASK_sig(context) ((context)->sc_mask)
190 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
191 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
192 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
193 #define MASK_sig(context) ((context)->uc_sigmask)
196 int cpu_signal_handler(int host_signum
, void *pinfo
,
199 siginfo_t
*info
= pinfo
;
200 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
201 ucontext_t
*uc
= puc
;
202 #elif defined(__OpenBSD__)
203 struct sigcontext
*uc
= puc
;
205 ucontext_t
*uc
= puc
;
214 #define REG_TRAPNO TRAPNO
217 trapno
= TRAP_sig(uc
);
218 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
220 (ERROR_sig(uc
) >> 1) & 1 : 0,
224 #elif defined(__x86_64__)
227 #define PC_sig(context) _UC_MACHINE_PC(context)
228 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
229 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
230 #define MASK_sig(context) ((context)->uc_sigmask)
231 #elif defined(__OpenBSD__)
232 #define PC_sig(context) ((context)->sc_rip)
233 #define TRAP_sig(context) ((context)->sc_trapno)
234 #define ERROR_sig(context) ((context)->sc_err)
235 #define MASK_sig(context) ((context)->sc_mask)
236 #elif defined(__FreeBSD__) || defined(__DragonFly__)
237 #include <ucontext.h>
239 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
240 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
241 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
242 #define MASK_sig(context) ((context)->uc_sigmask)
244 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
245 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
246 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
247 #define MASK_sig(context) ((context)->uc_sigmask)
250 int cpu_signal_handler(int host_signum
, void *pinfo
,
253 siginfo_t
*info
= pinfo
;
255 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
256 ucontext_t
*uc
= puc
;
257 #elif defined(__OpenBSD__)
258 struct sigcontext
*uc
= puc
;
260 ucontext_t
*uc
= puc
;
264 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
265 TRAP_sig(uc
) == 0xe ?
266 (ERROR_sig(uc
) >> 1) & 1 : 0,
270 #elif defined(_ARCH_PPC)
272 /***********************************************************************
273 * signal context platform-specific definitions
277 /* All Registers access - only for local access */
278 #define REG_sig(reg_name, context) \
279 ((context)->uc_mcontext.regs->reg_name)
280 /* Gpr Registers access */
281 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
282 /* Program counter */
283 #define IAR_sig(context) REG_sig(nip, context)
284 /* Machine State Register (Supervisor) */
285 #define MSR_sig(context) REG_sig(msr, context)
287 #define CTR_sig(context) REG_sig(ctr, context)
288 /* User's integer exception register */
289 #define XER_sig(context) REG_sig(xer, context)
291 #define LR_sig(context) REG_sig(link, context)
292 /* Condition register */
293 #define CR_sig(context) REG_sig(ccr, context)
295 /* Float Registers access */
296 #define FLOAT_sig(reg_num, context) \
297 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
298 #define FPSCR_sig(context) \
299 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
300 /* Exception Registers access */
301 #define DAR_sig(context) REG_sig(dar, context)
302 #define DSISR_sig(context) REG_sig(dsisr, context)
303 #define TRAP_sig(context) REG_sig(trap, context)
306 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
307 #include <ucontext.h>
308 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
309 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
310 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
311 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
312 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
313 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
314 /* Exception Registers access */
315 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
316 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
317 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
318 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
320 int cpu_signal_handler(int host_signum
, void *pinfo
,
323 siginfo_t
*info
= pinfo
;
324 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
325 ucontext_t
*uc
= puc
;
327 ucontext_t
*uc
= puc
;
336 if (DSISR_sig(uc
) & 0x00800000) {
340 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000)) {
344 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
345 is_write
, &uc
->uc_sigmask
);
348 #elif defined(__alpha__)
350 int cpu_signal_handler(int host_signum
, void *pinfo
,
353 siginfo_t
*info
= pinfo
;
354 ucontext_t
*uc
= puc
;
355 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
359 /* XXX: need kernel patch to get write flag faster */
360 switch (insn
>> 26) {
363 case 0x0f: /* stq_u */
370 case 0x2e: /* stl_c */
371 case 0x2f: /* stq_c */
375 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
376 is_write
, &uc
->uc_sigmask
);
378 #elif defined(__sparc__)
380 int cpu_signal_handler(int host_signum
, void *pinfo
,
383 siginfo_t
*info
= pinfo
;
386 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
387 uint32_t *regs
= (uint32_t *)(info
+ 1);
388 void *sigmask
= (regs
+ 20);
389 /* XXX: is there a standard glibc define ? */
390 unsigned long pc
= regs
[1];
393 struct sigcontext
*sc
= puc
;
394 unsigned long pc
= sc
->sigc_regs
.tpc
;
395 void *sigmask
= (void *)sc
->sigc_mask
;
396 #elif defined(__OpenBSD__)
397 struct sigcontext
*uc
= puc
;
398 unsigned long pc
= uc
->sc_pc
;
399 void *sigmask
= (void *)(long)uc
->sc_mask
;
400 #elif defined(__NetBSD__)
401 ucontext_t
*uc
= puc
;
402 unsigned long pc
= _UC_MACHINE_PC(uc
);
403 void *sigmask
= (void *)&uc
->uc_sigmask
;
407 /* XXX: need kernel patch to get write flag faster */
409 insn
= *(uint32_t *)pc
;
410 if ((insn
>> 30) == 3) {
411 switch ((insn
>> 19) & 0x3f) {
413 case 0x15: /* stba */
415 case 0x16: /* stha */
419 case 0x17: /* stda */
421 case 0x1e: /* stxa */
423 case 0x34: /* stfa */
424 case 0x27: /* stdf */
425 case 0x37: /* stdfa */
426 case 0x26: /* stqf */
427 case 0x36: /* stqfa */
428 case 0x25: /* stfsr */
429 case 0x3c: /* casa */
430 case 0x3e: /* casxa */
435 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
439 #elif defined(__arm__)
441 #if defined(__NetBSD__)
442 #include <ucontext.h>
445 int cpu_signal_handler(int host_signum
, void *pinfo
,
448 siginfo_t
*info
= pinfo
;
449 #if defined(__NetBSD__)
450 ucontext_t
*uc
= puc
;
452 ucontext_t
*uc
= puc
;
457 #if defined(__NetBSD__)
458 pc
= uc
->uc_mcontext
.__gregs
[_REG_R15
];
459 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
460 pc
= uc
->uc_mcontext
.gregs
[R15
];
462 pc
= uc
->uc_mcontext
.arm_pc
;
465 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
466 * later processor; on v5 we will always report this as a read).
468 is_write
= extract32(uc
->uc_mcontext
.error_code
, 11, 1);
469 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
474 #elif defined(__aarch64__)
476 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
478 siginfo_t
*info
= pinfo
;
479 ucontext_t
*uc
= puc
;
480 uintptr_t pc
= uc
->uc_mcontext
.pc
;
481 uint32_t insn
= *(uint32_t *)pc
;
484 /* XXX: need kernel patch to get write flag faster. */
485 is_write
= ( (insn
& 0xbfff0000) == 0x0c000000 /* C3.3.1 */
486 || (insn
& 0xbfe00000) == 0x0c800000 /* C3.3.2 */
487 || (insn
& 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
488 || (insn
& 0xbfc00000) == 0x0d800000 /* C3.3.4 */
489 || (insn
& 0x3f400000) == 0x08000000 /* C3.3.6 */
490 || (insn
& 0x3bc00000) == 0x39000000 /* C3.3.13 */
491 || (insn
& 0x3fc00000) == 0x3d800000 /* ... 128bit */
492 /* Ingore bits 10, 11 & 21, controlling indexing. */
493 || (insn
& 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
494 || (insn
& 0x3fe00000) == 0x3c800000 /* ... 128bit */
495 /* Ignore bits 23 & 24, controlling indexing. */
496 || (insn
& 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
498 return handle_cpu_signal(pc
, (uintptr_t)info
->si_addr
,
499 is_write
, &uc
->uc_sigmask
);
502 #elif defined(__ia64)
505 /* This ought to be in <bits/siginfo.h>... */
506 # define __ISR_VALID 1
509 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
511 siginfo_t
*info
= pinfo
;
512 ucontext_t
*uc
= puc
;
516 ip
= uc
->uc_mcontext
.sc_ip
;
517 switch (host_signum
) {
523 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
)) {
524 /* ISR.W (write-access) is bit 33: */
525 is_write
= (info
->si_isr
>> 33) & 1;
532 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
534 (sigset_t
*)&uc
->uc_sigmask
);
537 #elif defined(__s390__)
539 int cpu_signal_handler(int host_signum
, void *pinfo
,
542 siginfo_t
*info
= pinfo
;
543 ucontext_t
*uc
= puc
;
548 pc
= uc
->uc_mcontext
.psw
.addr
;
550 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
551 of the normal 2 arguments. The 3rd argument contains the "int_code"
552 from the hardware which does in fact contain the is_write value.
553 The rt signal handler, as far as I can tell, does not give this value
554 at all. Not that we could get to it from here even if it were. */
555 /* ??? This is not even close to complete, since it ignores all
556 of the read-modify-write instructions. */
557 pinsn
= (uint16_t *)pc
;
558 switch (pinsn
[0] >> 8) {
564 case 0xc4: /* RIL format insns */
565 switch (pinsn
[0] & 0xf) {
567 case 0xb: /* STGRL */
568 case 0x7: /* STHRL */
572 case 0xe3: /* RXY format insns */
573 switch (pinsn
[2] & 0xff) {
576 case 0x72: /* STCY */
577 case 0x70: /* STHY */
578 case 0x8e: /* STPQ */
579 case 0x3f: /* STRVH */
580 case 0x3e: /* STRV */
581 case 0x2f: /* STRVG */
586 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
587 is_write
, &uc
->uc_sigmask
);
590 #elif defined(__mips__)
592 int cpu_signal_handler(int host_signum
, void *pinfo
,
595 siginfo_t
*info
= pinfo
;
596 ucontext_t
*uc
= puc
;
597 greg_t pc
= uc
->uc_mcontext
.pc
;
600 /* XXX: compute is_write */
602 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
603 is_write
, &uc
->uc_sigmask
);
608 #error host CPU specific signal handler needed
612 /* The softmmu versions of these helpers are in cputlb.c. */
614 /* Do not allow unaligned operations to proceed. Return the host address. */
615 static void *atomic_mmu_lookup(CPUArchState
*env
, target_ulong addr
,
616 int size
, uintptr_t retaddr
)
618 /* Enforce qemu required alignment. */
619 if (unlikely(addr
& (size
- 1))) {
620 cpu_loop_exit_atomic(ENV_GET_CPU(env
), retaddr
);
622 helper_retaddr
= retaddr
;
626 /* Macro to call the above, with local variables from the use context. */
627 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
628 #define ATOMIC_MMU_CLEANUP do { helper_retaddr = 0; } while (0)
630 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
634 #include "atomic_template.h"
637 #include "atomic_template.h"
640 #include "atomic_template.h"
642 #ifdef CONFIG_ATOMIC64
644 #include "atomic_template.h"
647 /* The following is only callable from other helpers, and matches up
648 with the softmmu version. */
650 #ifdef CONFIG_ATOMIC128
654 #undef ATOMIC_MMU_LOOKUP
656 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr
657 #define ATOMIC_NAME(X) \
658 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
659 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
662 #include "atomic_template.h"
663 #endif /* CONFIG_ATOMIC128 */