2 * User emulator execution
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "disas/disas.h"
22 #include "exec/exec-all.h"
24 #include "qemu/bitops.h"
25 #include "exec/cpu_ldst.h"
26 #include "translate-all.h"
27 #include "exec/helper-proto.h"
28 #include "qemu/atomic128.h"
29 #include "trace-root.h"
30 #include "trace/mem.h"
42 #include <sys/ucontext.h>
45 __thread
uintptr_t helper_retaddr
;
47 //#define DEBUG_SIGNAL
49 /* exit the current TB from a signal handler. The host registers are
50 restored in a state compatible with the CPU emulator
52 static void cpu_exit_tb_from_sighandler(CPUState
*cpu
, sigset_t
*old_set
)
54 /* XXX: use siglongjmp ? */
55 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
56 cpu_loop_exit_noexc(cpu
);
59 /* 'pc' is the host PC at which the exception was raised. 'address' is
60 the effective address of the memory exception. 'is_write' is 1 if a
61 write caused the exception and otherwise 0'. 'old_set' is the
62 signal set which should be restored */
63 static inline int handle_cpu_signal(uintptr_t pc
, siginfo_t
*info
,
64 int is_write
, sigset_t
*old_set
)
66 CPUState
*cpu
= current_cpu
;
68 unsigned long address
= (unsigned long)info
->si_addr
;
69 MMUAccessType access_type
= is_write
? MMU_DATA_STORE
: MMU_DATA_LOAD
;
71 switch (helper_retaddr
) {
74 * Fault during host memory operation within a helper function.
75 * The helper's host return address, saved here, gives us a
76 * pointer into the generated code that will unwind to the
84 * Fault during host memory operation within generated code.
85 * (Or, a unrelated bug within qemu, but we can't tell from here).
87 * We take the host pc from the signal frame. However, we cannot
88 * use that value directly. Within cpu_restore_state_from_tb, we
89 * assume PC comes from GETPC(), as used by the helper functions,
90 * so we adjust the address by -GETPC_ADJ to form an address that
91 * is within the call insn, so that the address does not accidentially
92 * match the beginning of the next guest insn. However, when the
93 * pc comes from the signal frame it points to the actual faulting
94 * host memory insn and not the return from a call insn.
96 * Therefore, adjust to compensate for what will be done later
97 * by cpu_restore_state_from_tb.
104 * Fault during host read for translation, or loosely, "execution".
106 * The guest pc is already pointing to the start of the TB for which
107 * code is being generated. If the guest translator manages the
108 * page crossings correctly, this is exactly the correct address
109 * (and if the translator doesn't handle page boundaries correctly
110 * there's little we can do about that here). Therefore, do not
111 * trigger the unwinder.
113 * Like tb_gen_code, release the memory lock before cpu_loop_exit.
116 access_type
= MMU_INST_FETCH
;
121 /* For synchronous signals we expect to be coming from the vCPU
122 * thread (so current_cpu should be valid) and either from running
123 * code or during translation which can fault as we cross pages.
125 * If neither is true then something has gone wrong and we should
126 * abort rather than try and restart the vCPU execution.
128 if (!cpu
|| !cpu
->running
) {
129 printf("qemu:%s received signal outside vCPU context @ pc=0x%"
130 PRIxPTR
"\n", __func__
, pc
);
134 #if defined(DEBUG_SIGNAL)
135 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
136 pc
, address
, is_write
, *(unsigned long *)old_set
);
138 /* XXX: locking issue */
139 /* Note that it is important that we don't call page_unprotect() unless
140 * this is really a "write to nonwriteable page" fault, because
141 * page_unprotect() assumes that if it is called for an access to
142 * a page that's writeable this means we had two threads racing and
143 * another thread got there first and already made the page writeable;
144 * so we will retry the access. If we were to call page_unprotect()
145 * for some other kind of fault that should really be passed to the
146 * guest, we'd end up in an infinite loop of retrying the faulting
149 if (is_write
&& info
->si_signo
== SIGSEGV
&& info
->si_code
== SEGV_ACCERR
&&
150 h2g_valid(address
)) {
151 switch (page_unprotect(h2g(address
), pc
)) {
153 /* Fault not caused by a page marked unwritable to protect
154 * cached translations, must be the guest binary's problem.
158 /* Fault caused by protection of cached translation; TBs
159 * invalidated, so resume execution. Retain helper_retaddr
160 * for a possible second fault.
164 /* Fault caused by protection of cached translation, and the
165 * currently executing TB was modified and must be exited
166 * immediately. Clear helper_retaddr for next execution.
168 clear_helper_retaddr();
169 cpu_exit_tb_from_sighandler(cpu
, old_set
);
173 g_assert_not_reached();
177 /* Convert forcefully to guest address space, invalid addresses
178 are still valid segv ones */
179 address
= h2g_nocheck(address
);
182 * There is no way the target can handle this other than raising
183 * an exception. Undo signal and retaddr state prior to longjmp.
185 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
186 clear_helper_retaddr();
188 cc
= CPU_GET_CLASS(cpu
);
189 cc
->tlb_fill(cpu
, address
, 0, access_type
, MMU_USER_IDX
, false, pc
);
190 g_assert_not_reached();
193 static int probe_access_internal(CPUArchState
*env
, target_ulong addr
,
194 int fault_size
, MMUAccessType access_type
,
195 bool nonfault
, uintptr_t ra
)
199 switch (access_type
) {
210 g_assert_not_reached();
213 if (!guest_addr_valid(addr
) || page_check_range(addr
, 1, flags
) < 0) {
215 return TLB_INVALID_MASK
;
217 CPUState
*cpu
= env_cpu(env
);
218 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
219 cc
->tlb_fill(cpu
, addr
, fault_size
, access_type
,
220 MMU_USER_IDX
, false, ra
);
221 g_assert_not_reached();
227 int probe_access_flags(CPUArchState
*env
, target_ulong addr
,
228 MMUAccessType access_type
, int mmu_idx
,
229 bool nonfault
, void **phost
, uintptr_t ra
)
233 flags
= probe_access_internal(env
, addr
, 0, access_type
, nonfault
, ra
);
234 *phost
= flags
? NULL
: g2h(addr
);
238 void *probe_access(CPUArchState
*env
, target_ulong addr
, int size
,
239 MMUAccessType access_type
, int mmu_idx
, uintptr_t ra
)
243 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
244 flags
= probe_access_internal(env
, addr
, size
, access_type
, false, ra
);
245 g_assert(flags
== 0);
247 return size
? g2h(addr
) : NULL
;
250 #if defined(__i386__)
252 #if defined(__NetBSD__)
253 #include <ucontext.h>
255 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
256 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
257 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
258 #define MASK_sig(context) ((context)->uc_sigmask)
259 #elif defined(__FreeBSD__) || defined(__DragonFly__)
260 #include <ucontext.h>
262 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
263 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
264 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
265 #define MASK_sig(context) ((context)->uc_sigmask)
266 #elif defined(__OpenBSD__)
267 #define EIP_sig(context) ((context)->sc_eip)
268 #define TRAP_sig(context) ((context)->sc_trapno)
269 #define ERROR_sig(context) ((context)->sc_err)
270 #define MASK_sig(context) ((context)->sc_mask)
272 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
273 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
274 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
275 #define MASK_sig(context) ((context)->uc_sigmask)
278 int cpu_signal_handler(int host_signum
, void *pinfo
,
281 siginfo_t
*info
= pinfo
;
282 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
283 ucontext_t
*uc
= puc
;
284 #elif defined(__OpenBSD__)
285 struct sigcontext
*uc
= puc
;
287 ucontext_t
*uc
= puc
;
296 #define REG_TRAPNO TRAPNO
299 trapno
= TRAP_sig(uc
);
300 return handle_cpu_signal(pc
, info
,
301 trapno
== 0xe ? (ERROR_sig(uc
) >> 1) & 1 : 0,
305 #elif defined(__x86_64__)
308 #define PC_sig(context) _UC_MACHINE_PC(context)
309 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
310 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
311 #define MASK_sig(context) ((context)->uc_sigmask)
312 #elif defined(__OpenBSD__)
313 #define PC_sig(context) ((context)->sc_rip)
314 #define TRAP_sig(context) ((context)->sc_trapno)
315 #define ERROR_sig(context) ((context)->sc_err)
316 #define MASK_sig(context) ((context)->sc_mask)
317 #elif defined(__FreeBSD__) || defined(__DragonFly__)
318 #include <ucontext.h>
320 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
321 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
322 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
323 #define MASK_sig(context) ((context)->uc_sigmask)
325 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
326 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
327 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
328 #define MASK_sig(context) ((context)->uc_sigmask)
331 int cpu_signal_handler(int host_signum
, void *pinfo
,
334 siginfo_t
*info
= pinfo
;
336 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
337 ucontext_t
*uc
= puc
;
338 #elif defined(__OpenBSD__)
339 struct sigcontext
*uc
= puc
;
341 ucontext_t
*uc
= puc
;
345 return handle_cpu_signal(pc
, info
,
346 TRAP_sig(uc
) == 0xe ? (ERROR_sig(uc
) >> 1) & 1 : 0,
350 #elif defined(_ARCH_PPC)
352 /***********************************************************************
353 * signal context platform-specific definitions
357 /* All Registers access - only for local access */
358 #define REG_sig(reg_name, context) \
359 ((context)->uc_mcontext.regs->reg_name)
360 /* Gpr Registers access */
361 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
362 /* Program counter */
363 #define IAR_sig(context) REG_sig(nip, context)
364 /* Machine State Register (Supervisor) */
365 #define MSR_sig(context) REG_sig(msr, context)
367 #define CTR_sig(context) REG_sig(ctr, context)
368 /* User's integer exception register */
369 #define XER_sig(context) REG_sig(xer, context)
371 #define LR_sig(context) REG_sig(link, context)
372 /* Condition register */
373 #define CR_sig(context) REG_sig(ccr, context)
375 /* Float Registers access */
376 #define FLOAT_sig(reg_num, context) \
377 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
378 #define FPSCR_sig(context) \
379 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
380 /* Exception Registers access */
381 #define DAR_sig(context) REG_sig(dar, context)
382 #define DSISR_sig(context) REG_sig(dsisr, context)
383 #define TRAP_sig(context) REG_sig(trap, context)
386 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
387 #include <ucontext.h>
388 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
389 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
390 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
391 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
392 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
393 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
394 /* Exception Registers access */
395 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
396 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
397 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
398 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
400 int cpu_signal_handler(int host_signum
, void *pinfo
,
403 siginfo_t
*info
= pinfo
;
404 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
405 ucontext_t
*uc
= puc
;
407 ucontext_t
*uc
= puc
;
416 if (DSISR_sig(uc
) & 0x00800000) {
420 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000)) {
424 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
427 #elif defined(__alpha__)
429 int cpu_signal_handler(int host_signum
, void *pinfo
,
432 siginfo_t
*info
= pinfo
;
433 ucontext_t
*uc
= puc
;
434 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
438 /* XXX: need kernel patch to get write flag faster */
439 switch (insn
>> 26) {
442 case 0x0f: /* stq_u */
449 case 0x2e: /* stl_c */
450 case 0x2f: /* stq_c */
454 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
456 #elif defined(__sparc__)
458 int cpu_signal_handler(int host_signum
, void *pinfo
,
461 siginfo_t
*info
= pinfo
;
464 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
465 uint32_t *regs
= (uint32_t *)(info
+ 1);
466 void *sigmask
= (regs
+ 20);
467 /* XXX: is there a standard glibc define ? */
468 unsigned long pc
= regs
[1];
471 struct sigcontext
*sc
= puc
;
472 unsigned long pc
= sc
->sigc_regs
.tpc
;
473 void *sigmask
= (void *)sc
->sigc_mask
;
474 #elif defined(__OpenBSD__)
475 struct sigcontext
*uc
= puc
;
476 unsigned long pc
= uc
->sc_pc
;
477 void *sigmask
= (void *)(long)uc
->sc_mask
;
478 #elif defined(__NetBSD__)
479 ucontext_t
*uc
= puc
;
480 unsigned long pc
= _UC_MACHINE_PC(uc
);
481 void *sigmask
= (void *)&uc
->uc_sigmask
;
485 /* XXX: need kernel patch to get write flag faster */
487 insn
= *(uint32_t *)pc
;
488 if ((insn
>> 30) == 3) {
489 switch ((insn
>> 19) & 0x3f) {
491 case 0x15: /* stba */
493 case 0x16: /* stha */
497 case 0x17: /* stda */
499 case 0x1e: /* stxa */
501 case 0x34: /* stfa */
502 case 0x27: /* stdf */
503 case 0x37: /* stdfa */
504 case 0x26: /* stqf */
505 case 0x36: /* stqfa */
506 case 0x25: /* stfsr */
507 case 0x3c: /* casa */
508 case 0x3e: /* casxa */
513 return handle_cpu_signal(pc
, info
, is_write
, sigmask
);
516 #elif defined(__arm__)
518 #if defined(__NetBSD__)
519 #include <ucontext.h>
522 int cpu_signal_handler(int host_signum
, void *pinfo
,
525 siginfo_t
*info
= pinfo
;
526 #if defined(__NetBSD__)
527 ucontext_t
*uc
= puc
;
529 ucontext_t
*uc
= puc
;
534 #if defined(__NetBSD__)
535 pc
= uc
->uc_mcontext
.__gregs
[_REG_R15
];
536 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
537 pc
= uc
->uc_mcontext
.gregs
[R15
];
539 pc
= uc
->uc_mcontext
.arm_pc
;
542 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
543 * later processor; on v5 we will always report this as a read).
545 is_write
= extract32(uc
->uc_mcontext
.error_code
, 11, 1);
546 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
549 #elif defined(__aarch64__)
552 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
553 #define ESR_MAGIC 0x45535201
555 struct _aarch64_ctx head
;
560 static inline struct _aarch64_ctx
*first_ctx(ucontext_t
*uc
)
562 return (struct _aarch64_ctx
*)&uc
->uc_mcontext
.__reserved
;
565 static inline struct _aarch64_ctx
*next_ctx(struct _aarch64_ctx
*hdr
)
567 return (struct _aarch64_ctx
*)((char *)hdr
+ hdr
->size
);
570 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
572 siginfo_t
*info
= pinfo
;
573 ucontext_t
*uc
= puc
;
574 uintptr_t pc
= uc
->uc_mcontext
.pc
;
576 struct _aarch64_ctx
*hdr
;
577 struct esr_context
const *esrctx
= NULL
;
579 /* Find the esr_context, which has the WnR bit in it */
580 for (hdr
= first_ctx(uc
); hdr
->magic
; hdr
= next_ctx(hdr
)) {
581 if (hdr
->magic
== ESR_MAGIC
) {
582 esrctx
= (struct esr_context
const *)hdr
;
588 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
589 uint64_t esr
= esrctx
->esr
;
590 is_write
= extract32(esr
, 27, 5) == 0x12 && extract32(esr
, 6, 1) == 1;
593 * Fall back to parsing instructions; will only be needed
594 * for really ancient (pre-3.16) kernels.
596 uint32_t insn
= *(uint32_t *)pc
;
598 is_write
= ((insn
& 0xbfff0000) == 0x0c000000 /* C3.3.1 */
599 || (insn
& 0xbfe00000) == 0x0c800000 /* C3.3.2 */
600 || (insn
& 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
601 || (insn
& 0xbfc00000) == 0x0d800000 /* C3.3.4 */
602 || (insn
& 0x3f400000) == 0x08000000 /* C3.3.6 */
603 || (insn
& 0x3bc00000) == 0x39000000 /* C3.3.13 */
604 || (insn
& 0x3fc00000) == 0x3d800000 /* ... 128bit */
605 /* Ignore bits 10, 11 & 21, controlling indexing. */
606 || (insn
& 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
607 || (insn
& 0x3fe00000) == 0x3c800000 /* ... 128bit */
608 /* Ignore bits 23 & 24, controlling indexing. */
609 || (insn
& 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
611 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
614 #elif defined(__s390__)
616 int cpu_signal_handler(int host_signum
, void *pinfo
,
619 siginfo_t
*info
= pinfo
;
620 ucontext_t
*uc
= puc
;
625 pc
= uc
->uc_mcontext
.psw
.addr
;
627 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
628 of the normal 2 arguments. The 3rd argument contains the "int_code"
629 from the hardware which does in fact contain the is_write value.
630 The rt signal handler, as far as I can tell, does not give this value
631 at all. Not that we could get to it from here even if it were. */
632 /* ??? This is not even close to complete, since it ignores all
633 of the read-modify-write instructions. */
634 pinsn
= (uint16_t *)pc
;
635 switch (pinsn
[0] >> 8) {
641 case 0xc4: /* RIL format insns */
642 switch (pinsn
[0] & 0xf) {
644 case 0xb: /* STGRL */
645 case 0x7: /* STHRL */
649 case 0xe3: /* RXY format insns */
650 switch (pinsn
[2] & 0xff) {
653 case 0x72: /* STCY */
654 case 0x70: /* STHY */
655 case 0x8e: /* STPQ */
656 case 0x3f: /* STRVH */
657 case 0x3e: /* STRV */
658 case 0x2f: /* STRVG */
663 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
666 #elif defined(__mips__)
668 int cpu_signal_handler(int host_signum
, void *pinfo
,
671 siginfo_t
*info
= pinfo
;
672 ucontext_t
*uc
= puc
;
673 greg_t pc
= uc
->uc_mcontext
.pc
;
676 /* XXX: compute is_write */
678 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
681 #elif defined(__riscv)
683 int cpu_signal_handler(int host_signum
, void *pinfo
,
686 siginfo_t
*info
= pinfo
;
687 ucontext_t
*uc
= puc
;
688 greg_t pc
= uc
->uc_mcontext
.__gregs
[REG_PC
];
689 uint32_t insn
= *(uint32_t *)pc
;
692 /* Detect store by reading the instruction at the program
693 counter. Note: we currently only generate 32-bit
694 instructions so we thus only detect 32-bit stores */
695 switch (((insn
>> 0) & 0b11)) {
697 switch (((insn
>> 2) & 0b11111)) {
699 switch (((insn
>> 12) & 0b111)) {
712 switch (((insn
>> 12) & 0b111)) {
727 /* Check for compressed instructions */
728 switch (((insn
>> 13) & 0b111)) {
730 switch (insn
& 0b11) {
740 switch (insn
& 0b11) {
753 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
758 #error host CPU specific signal handler needed
762 /* The softmmu versions of these helpers are in cputlb.c. */
764 uint32_t cpu_ldub_data(CPUArchState
*env
, abi_ptr ptr
)
767 uint16_t meminfo
= trace_mem_get_info(MO_UB
, MMU_USER_IDX
, false);
769 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
770 ret
= ldub_p(g2h(ptr
));
771 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
775 int cpu_ldsb_data(CPUArchState
*env
, abi_ptr ptr
)
778 uint16_t meminfo
= trace_mem_get_info(MO_SB
, MMU_USER_IDX
, false);
780 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
781 ret
= ldsb_p(g2h(ptr
));
782 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
786 uint32_t cpu_lduw_be_data(CPUArchState
*env
, abi_ptr ptr
)
789 uint16_t meminfo
= trace_mem_get_info(MO_BEUW
, MMU_USER_IDX
, false);
791 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
792 ret
= lduw_be_p(g2h(ptr
));
793 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
797 int cpu_ldsw_be_data(CPUArchState
*env
, abi_ptr ptr
)
800 uint16_t meminfo
= trace_mem_get_info(MO_BESW
, MMU_USER_IDX
, false);
802 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
803 ret
= ldsw_be_p(g2h(ptr
));
804 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
808 uint32_t cpu_ldl_be_data(CPUArchState
*env
, abi_ptr ptr
)
811 uint16_t meminfo
= trace_mem_get_info(MO_BEUL
, MMU_USER_IDX
, false);
813 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
814 ret
= ldl_be_p(g2h(ptr
));
815 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
819 uint64_t cpu_ldq_be_data(CPUArchState
*env
, abi_ptr ptr
)
822 uint16_t meminfo
= trace_mem_get_info(MO_BEQ
, MMU_USER_IDX
, false);
824 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
825 ret
= ldq_be_p(g2h(ptr
));
826 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
830 uint32_t cpu_lduw_le_data(CPUArchState
*env
, abi_ptr ptr
)
833 uint16_t meminfo
= trace_mem_get_info(MO_LEUW
, MMU_USER_IDX
, false);
835 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
836 ret
= lduw_le_p(g2h(ptr
));
837 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
841 int cpu_ldsw_le_data(CPUArchState
*env
, abi_ptr ptr
)
844 uint16_t meminfo
= trace_mem_get_info(MO_LESW
, MMU_USER_IDX
, false);
846 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
847 ret
= ldsw_le_p(g2h(ptr
));
848 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
852 uint32_t cpu_ldl_le_data(CPUArchState
*env
, abi_ptr ptr
)
855 uint16_t meminfo
= trace_mem_get_info(MO_LEUL
, MMU_USER_IDX
, false);
857 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
858 ret
= ldl_le_p(g2h(ptr
));
859 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
863 uint64_t cpu_ldq_le_data(CPUArchState
*env
, abi_ptr ptr
)
866 uint16_t meminfo
= trace_mem_get_info(MO_LEQ
, MMU_USER_IDX
, false);
868 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
869 ret
= ldq_le_p(g2h(ptr
));
870 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
874 uint32_t cpu_ldub_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
878 set_helper_retaddr(retaddr
);
879 ret
= cpu_ldub_data(env
, ptr
);
880 clear_helper_retaddr();
884 int cpu_ldsb_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
888 set_helper_retaddr(retaddr
);
889 ret
= cpu_ldsb_data(env
, ptr
);
890 clear_helper_retaddr();
894 uint32_t cpu_lduw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
898 set_helper_retaddr(retaddr
);
899 ret
= cpu_lduw_be_data(env
, ptr
);
900 clear_helper_retaddr();
904 int cpu_ldsw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
908 set_helper_retaddr(retaddr
);
909 ret
= cpu_ldsw_be_data(env
, ptr
);
910 clear_helper_retaddr();
914 uint32_t cpu_ldl_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
918 set_helper_retaddr(retaddr
);
919 ret
= cpu_ldl_be_data(env
, ptr
);
920 clear_helper_retaddr();
924 uint64_t cpu_ldq_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
928 set_helper_retaddr(retaddr
);
929 ret
= cpu_ldq_be_data(env
, ptr
);
930 clear_helper_retaddr();
934 uint32_t cpu_lduw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
938 set_helper_retaddr(retaddr
);
939 ret
= cpu_lduw_le_data(env
, ptr
);
940 clear_helper_retaddr();
944 int cpu_ldsw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
948 set_helper_retaddr(retaddr
);
949 ret
= cpu_ldsw_le_data(env
, ptr
);
950 clear_helper_retaddr();
954 uint32_t cpu_ldl_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
958 set_helper_retaddr(retaddr
);
959 ret
= cpu_ldl_le_data(env
, ptr
);
960 clear_helper_retaddr();
964 uint64_t cpu_ldq_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
968 set_helper_retaddr(retaddr
);
969 ret
= cpu_ldq_le_data(env
, ptr
);
970 clear_helper_retaddr();
974 void cpu_stb_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
976 uint16_t meminfo
= trace_mem_get_info(MO_UB
, MMU_USER_IDX
, true);
978 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
979 stb_p(g2h(ptr
), val
);
980 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
983 void cpu_stw_be_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
985 uint16_t meminfo
= trace_mem_get_info(MO_BEUW
, MMU_USER_IDX
, true);
987 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
988 stw_be_p(g2h(ptr
), val
);
989 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
992 void cpu_stl_be_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
994 uint16_t meminfo
= trace_mem_get_info(MO_BEUL
, MMU_USER_IDX
, true);
996 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
997 stl_be_p(g2h(ptr
), val
);
998 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1001 void cpu_stq_be_data(CPUArchState
*env
, abi_ptr ptr
, uint64_t val
)
1003 uint16_t meminfo
= trace_mem_get_info(MO_BEQ
, MMU_USER_IDX
, true);
1005 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1006 stq_be_p(g2h(ptr
), val
);
1007 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1010 void cpu_stw_le_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1012 uint16_t meminfo
= trace_mem_get_info(MO_LEUW
, MMU_USER_IDX
, true);
1014 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1015 stw_le_p(g2h(ptr
), val
);
1016 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1019 void cpu_stl_le_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1021 uint16_t meminfo
= trace_mem_get_info(MO_LEUL
, MMU_USER_IDX
, true);
1023 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1024 stl_le_p(g2h(ptr
), val
);
1025 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1028 void cpu_stq_le_data(CPUArchState
*env
, abi_ptr ptr
, uint64_t val
)
1030 uint16_t meminfo
= trace_mem_get_info(MO_LEQ
, MMU_USER_IDX
, true);
1032 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1033 stq_le_p(g2h(ptr
), val
);
1034 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1037 void cpu_stb_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1038 uint32_t val
, uintptr_t retaddr
)
1040 set_helper_retaddr(retaddr
);
1041 cpu_stb_data(env
, ptr
, val
);
1042 clear_helper_retaddr();
1045 void cpu_stw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1046 uint32_t val
, uintptr_t retaddr
)
1048 set_helper_retaddr(retaddr
);
1049 cpu_stw_be_data(env
, ptr
, val
);
1050 clear_helper_retaddr();
1053 void cpu_stl_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1054 uint32_t val
, uintptr_t retaddr
)
1056 set_helper_retaddr(retaddr
);
1057 cpu_stl_be_data(env
, ptr
, val
);
1058 clear_helper_retaddr();
1061 void cpu_stq_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1062 uint64_t val
, uintptr_t retaddr
)
1064 set_helper_retaddr(retaddr
);
1065 cpu_stq_be_data(env
, ptr
, val
);
1066 clear_helper_retaddr();
1069 void cpu_stw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1070 uint32_t val
, uintptr_t retaddr
)
1072 set_helper_retaddr(retaddr
);
1073 cpu_stw_le_data(env
, ptr
, val
);
1074 clear_helper_retaddr();
1077 void cpu_stl_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1078 uint32_t val
, uintptr_t retaddr
)
1080 set_helper_retaddr(retaddr
);
1081 cpu_stl_le_data(env
, ptr
, val
);
1082 clear_helper_retaddr();
1085 void cpu_stq_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1086 uint64_t val
, uintptr_t retaddr
)
1088 set_helper_retaddr(retaddr
);
1089 cpu_stq_le_data(env
, ptr
, val
);
1090 clear_helper_retaddr();
1093 uint32_t cpu_ldub_code(CPUArchState
*env
, abi_ptr ptr
)
1097 set_helper_retaddr(1);
1098 ret
= ldub_p(g2h(ptr
));
1099 clear_helper_retaddr();
1103 uint32_t cpu_lduw_code(CPUArchState
*env
, abi_ptr ptr
)
1107 set_helper_retaddr(1);
1108 ret
= lduw_p(g2h(ptr
));
1109 clear_helper_retaddr();
1113 uint32_t cpu_ldl_code(CPUArchState
*env
, abi_ptr ptr
)
1117 set_helper_retaddr(1);
1118 ret
= ldl_p(g2h(ptr
));
1119 clear_helper_retaddr();
1123 uint64_t cpu_ldq_code(CPUArchState
*env
, abi_ptr ptr
)
1127 set_helper_retaddr(1);
1128 ret
= ldq_p(g2h(ptr
));
1129 clear_helper_retaddr();
1133 /* Do not allow unaligned operations to proceed. Return the host address. */
1134 static void *atomic_mmu_lookup(CPUArchState
*env
, target_ulong addr
,
1135 int size
, uintptr_t retaddr
)
1137 /* Enforce qemu required alignment. */
1138 if (unlikely(addr
& (size
- 1))) {
1139 cpu_loop_exit_atomic(env_cpu(env
), retaddr
);
1141 void *ret
= g2h(addr
);
1142 set_helper_retaddr(retaddr
);
1146 /* Macro to call the above, with local variables from the use context. */
1147 #define ATOMIC_MMU_DECLS do {} while (0)
1148 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
1149 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
1150 #define ATOMIC_MMU_IDX MMU_USER_IDX
1152 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
1155 #include "atomic_common.inc.c"
1158 #include "atomic_template.h"
1161 #include "atomic_template.h"
1164 #include "atomic_template.h"
1166 #ifdef CONFIG_ATOMIC64
1168 #include "atomic_template.h"
1171 /* The following is only callable from other helpers, and matches up
1172 with the softmmu version. */
1174 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128
1178 #undef ATOMIC_MMU_LOOKUP
1180 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr
1181 #define ATOMIC_NAME(X) \
1182 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
1183 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
1185 #define DATA_SIZE 16
1186 #include "atomic_template.h"