accel/tcg/user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "exec/exec-all.h"
  23 #include "tcg.h"
  24 #include "qemu/bitops.h"
  25 #include "exec/cpu_ldst.h"
  26 #include "translate-all.h"
  27 #include "exec/helper-proto.h"
  28 #include "qemu/atomic128.h"
  29
  30 #undef EAX
  31 #undef ECX
  32 #undef EDX
  33 #undef EBX
  34 #undef ESP
  35 #undef EBP
  36 #undef ESI
  37 #undef EDI
  38 #undef EIP
  39 #ifdef __linux__
  40 #include <sys/ucontext.h>
  41 #endif
  42
  43 __thread uintptr_t helper_retaddr;
  44
  45 //#define DEBUG_SIGNAL
  46
  47 /* exit the current TB from a signal handler. The host registers are
  48    restored in a state compatible with the CPU emulator
  49  */
  50 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
  51 {
  52     /* XXX: use siglongjmp ? */
  53     sigprocmask(SIG_SETMASK, old_set, NULL);
  54     cpu_loop_exit_noexc(cpu);
  55 }
  56
  57 /* 'pc' is the host PC at which the exception was raised. 'address' is
  58    the effective address of the memory exception. 'is_write' is 1 if a
  59    write caused the exception and otherwise 0'. 'old_set' is the
  60    signal set which should be restored */
  61 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
  62                                     int is_write, sigset_t *old_set)
  63 {
  64     CPUState *cpu = current_cpu;
  65     CPUClass *cc;
  66     int ret;
  67     unsigned long address = (unsigned long)info->si_addr;
  68     MMUAccessType access_type;
  69
  70     /* We must handle PC addresses from two different sources:
  71      * a call return address and a signal frame address.
  72      *
  73      * Within cpu_restore_state_from_tb we assume the former and adjust
  74      * the address by -GETPC_ADJ so that the address is within the call
  75      * insn so that addr does not accidentally match the beginning of the
  76      * next guest insn.
  77      *
  78      * However, when the PC comes from the signal frame, it points to
  79      * the actual faulting host insn and not a call insn.  Subtracting
  80      * GETPC_ADJ in that case may accidentally match the previous guest insn.
  81      *
  82      * So for the later case, adjust forward to compensate for what
  83      * will be done later by cpu_restore_state_from_tb.
  84      */
  85     if (helper_retaddr) {
  86         pc = helper_retaddr;
  87     } else {
  88         pc += GETPC_ADJ;
  89     }
  90
  91     /* For synchronous signals we expect to be coming from the vCPU
  92      * thread (so current_cpu should be valid) and either from running
  93      * code or during translation which can fault as we cross pages.
  94      *
  95      * If neither is true then something has gone wrong and we should
  96      * abort rather than try and restart the vCPU execution.
  97      */
  98     if (!cpu || !cpu->running) {
  99         printf("qemu:%s received signal outside vCPU context @ pc=0x%"
 100                PRIxPTR "\n",  __func__, pc);
 101         abort();
 102     }
 103
 104 #if defined(DEBUG_SIGNAL)
 105     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 106            pc, address, is_write, *(unsigned long *)old_set);
 107 #endif
 108     /* XXX: locking issue */
 109     /* Note that it is important that we don't call page_unprotect() unless
 110      * this is really a "write to nonwriteable page" fault, because
 111      * page_unprotect() assumes that if it is called for an access to
 112      * a page that's writeable this means we had two threads racing and
 113      * another thread got there first and already made the page writeable;
 114      * so we will retry the access. If we were to call page_unprotect()
 115      * for some other kind of fault that should really be passed to the
 116      * guest, we'd end up in an infinite loop of retrying the faulting
 117      * access.
 118      */
 119     if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR &&
 120         h2g_valid(address)) {
 121         switch (page_unprotect(h2g(address), pc)) {
 122         case 0:
 123             /* Fault not caused by a page marked unwritable to protect
 124              * cached translations, must be the guest binary's problem.
 125              */
 126             break;
 127         case 1:
 128             /* Fault caused by protection of cached translation; TBs
 129              * invalidated, so resume execution.  Retain helper_retaddr
 130              * for a possible second fault.
 131              */
 132             return 1;
 133         case 2:
 134             /* Fault caused by protection of cached translation, and the
 135              * currently executing TB was modified and must be exited
 136              * immediately.  Clear helper_retaddr for next execution.
 137              */
 138             helper_retaddr = 0;
 139             cpu_exit_tb_from_sighandler(cpu, old_set);
 140             /* NORETURN */
 141
 142         default:
 143             g_assert_not_reached();
 144         }
 145     }
 146
 147     /* Convert forcefully to guest address space, invalid addresses
 148        are still valid segv ones */
 149     address = h2g_nocheck(address);
 150
 151     /*
 152      * There is no way the target can handle this other than raising
 153      * an exception.  Undo signal and retaddr state prior to longjmp.
 154      */
 155     sigprocmask(SIG_SETMASK, old_set, NULL);
 156     helper_retaddr = 0;
 157
 158     cc = CPU_GET_CLASS(cpu);
 159     if (cc->tlb_fill) {
 160         access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
 161         cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
 162         g_assert_not_reached();
 163     } else {
 164         ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX);
 165         g_assert(ret > 0);
 166         cpu_loop_exit_restore(cpu, pc);
 167     }
 168 }
 169
 170 #if defined(__i386__)
 171
 172 #if defined(__NetBSD__)
 173 #include <ucontext.h>
 174
 175 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 176 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 177 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 178 #define MASK_sig(context)    ((context)->uc_sigmask)
 179 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 180 #include <ucontext.h>
 181
 182 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 183 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 184 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 185 #define MASK_sig(context)    ((context)->uc_sigmask)
 186 #elif defined(__OpenBSD__)
 187 #define EIP_sig(context)     ((context)->sc_eip)
 188 #define TRAP_sig(context)    ((context)->sc_trapno)
 189 #define ERROR_sig(context)   ((context)->sc_err)
 190 #define MASK_sig(context)    ((context)->sc_mask)
 191 #else
 192 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 193 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 194 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 195 #define MASK_sig(context)    ((context)->uc_sigmask)
 196 #endif
 197
 198 int cpu_signal_handler(int host_signum, void *pinfo,
 199                        void *puc)
 200 {
 201     siginfo_t *info = pinfo;
 202 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 203     ucontext_t *uc = puc;
 204 #elif defined(__OpenBSD__)
 205     struct sigcontext *uc = puc;
 206 #else
 207     ucontext_t *uc = puc;
 208 #endif
 209     unsigned long pc;
 210     int trapno;
 211
 212 #ifndef REG_EIP
 213 /* for glibc 2.1 */
 214 #define REG_EIP    EIP
 215 #define REG_ERR    ERR
 216 #define REG_TRAPNO TRAPNO
 217 #endif
 218     pc = EIP_sig(uc);
 219     trapno = TRAP_sig(uc);
 220     return handle_cpu_signal(pc, info,
 221                              trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
 222                              &MASK_sig(uc));
 223 }
 224
 225 #elif defined(__x86_64__)
 226
 227 #ifdef __NetBSD__
 228 #define PC_sig(context)       _UC_MACHINE_PC(context)
 229 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 230 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 231 #define MASK_sig(context)     ((context)->uc_sigmask)
 232 #elif defined(__OpenBSD__)
 233 #define PC_sig(context)       ((context)->sc_rip)
 234 #define TRAP_sig(context)     ((context)->sc_trapno)
 235 #define ERROR_sig(context)    ((context)->sc_err)
 236 #define MASK_sig(context)     ((context)->sc_mask)
 237 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 238 #include <ucontext.h>
 239
 240 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 241 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 242 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 243 #define MASK_sig(context)     ((context)->uc_sigmask)
 244 #else
 245 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 246 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 247 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 248 #define MASK_sig(context)     ((context)->uc_sigmask)
 249 #endif
 250
 251 int cpu_signal_handler(int host_signum, void *pinfo,
 252                        void *puc)
 253 {
 254     siginfo_t *info = pinfo;
 255     unsigned long pc;
 256 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 257     ucontext_t *uc = puc;
 258 #elif defined(__OpenBSD__)
 259     struct sigcontext *uc = puc;
 260 #else
 261     ucontext_t *uc = puc;
 262 #endif
 263
 264     pc = PC_sig(uc);
 265     return handle_cpu_signal(pc, info,
 266                              TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
 267                              &MASK_sig(uc));
 268 }
 269
 270 #elif defined(_ARCH_PPC)
 271
 272 /***********************************************************************
 273  * signal context platform-specific definitions
 274  * From Wine
 275  */
 276 #ifdef linux
 277 /* All Registers access - only for local access */
 278 #define REG_sig(reg_name, context)              \
 279     ((context)->uc_mcontext.regs->reg_name)
 280 /* Gpr Registers access  */
 281 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 282 /* Program counter */
 283 #define IAR_sig(context)                       REG_sig(nip, context)
 284 /* Machine State Register (Supervisor) */
 285 #define MSR_sig(context)                       REG_sig(msr, context)
 286 /* Count register */
 287 #define CTR_sig(context)                       REG_sig(ctr, context)
 288 /* User's integer exception register */
 289 #define XER_sig(context)                       REG_sig(xer, context)
 290 /* Link register */
 291 #define LR_sig(context)                        REG_sig(link, context)
 292 /* Condition register */
 293 #define CR_sig(context)                        REG_sig(ccr, context)
 294
 295 /* Float Registers access  */
 296 #define FLOAT_sig(reg_num, context)                                     \
 297     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 298 #define FPSCR_sig(context) \
 299     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 300 /* Exception Registers access */
 301 #define DAR_sig(context)                       REG_sig(dar, context)
 302 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 303 #define TRAP_sig(context)                      REG_sig(trap, context)
 304 #endif /* linux */
 305
 306 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 307 #include <ucontext.h>
 308 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 309 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 310 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 311 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 312 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 313 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 314 /* Exception Registers access */
 315 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 316 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 317 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 318 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 319
 320 int cpu_signal_handler(int host_signum, void *pinfo,
 321                        void *puc)
 322 {
 323     siginfo_t *info = pinfo;
 324 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 325     ucontext_t *uc = puc;
 326 #else
 327     ucontext_t *uc = puc;
 328 #endif
 329     unsigned long pc;
 330     int is_write;
 331
 332     pc = IAR_sig(uc);
 333     is_write = 0;
 334 #if 0
 335     /* ppc 4xx case */
 336     if (DSISR_sig(uc) & 0x00800000) {
 337         is_write = 1;
 338     }
 339 #else
 340     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 341         is_write = 1;
 342     }
 343 #endif
 344     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 345 }
 346
 347 #elif defined(__alpha__)
 348
 349 int cpu_signal_handler(int host_signum, void *pinfo,
 350                            void *puc)
 351 {
 352     siginfo_t *info = pinfo;
 353     ucontext_t *uc = puc;
 354     uint32_t *pc = uc->uc_mcontext.sc_pc;
 355     uint32_t insn = *pc;
 356     int is_write = 0;
 357
 358     /* XXX: need kernel patch to get write flag faster */
 359     switch (insn >> 26) {
 360     case 0x0d: /* stw */
 361     case 0x0e: /* stb */
 362     case 0x0f: /* stq_u */
 363     case 0x24: /* stf */
 364     case 0x25: /* stg */
 365     case 0x26: /* sts */
 366     case 0x27: /* stt */
 367     case 0x2c: /* stl */
 368     case 0x2d: /* stq */
 369     case 0x2e: /* stl_c */
 370     case 0x2f: /* stq_c */
 371         is_write = 1;
 372     }
 373
 374     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 375 }
 376 #elif defined(__sparc__)
 377
 378 int cpu_signal_handler(int host_signum, void *pinfo,
 379                        void *puc)
 380 {
 381     siginfo_t *info = pinfo;
 382     int is_write;
 383     uint32_t insn;
 384 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 385     uint32_t *regs = (uint32_t *)(info + 1);
 386     void *sigmask = (regs + 20);
 387     /* XXX: is there a standard glibc define ? */
 388     unsigned long pc = regs[1];
 389 #else
 390 #ifdef __linux__
 391     struct sigcontext *sc = puc;
 392     unsigned long pc = sc->sigc_regs.tpc;
 393     void *sigmask = (void *)sc->sigc_mask;
 394 #elif defined(__OpenBSD__)
 395     struct sigcontext *uc = puc;
 396     unsigned long pc = uc->sc_pc;
 397     void *sigmask = (void *)(long)uc->sc_mask;
 398 #elif defined(__NetBSD__)
 399     ucontext_t *uc = puc;
 400     unsigned long pc = _UC_MACHINE_PC(uc);
 401     void *sigmask = (void *)&uc->uc_sigmask;
 402 #endif
 403 #endif
 404
 405     /* XXX: need kernel patch to get write flag faster */
 406     is_write = 0;
 407     insn = *(uint32_t *)pc;
 408     if ((insn >> 30) == 3) {
 409         switch ((insn >> 19) & 0x3f) {
 410         case 0x05: /* stb */
 411         case 0x15: /* stba */
 412         case 0x06: /* sth */
 413         case 0x16: /* stha */
 414         case 0x04: /* st */
 415         case 0x14: /* sta */
 416         case 0x07: /* std */
 417         case 0x17: /* stda */
 418         case 0x0e: /* stx */
 419         case 0x1e: /* stxa */
 420         case 0x24: /* stf */
 421         case 0x34: /* stfa */
 422         case 0x27: /* stdf */
 423         case 0x37: /* stdfa */
 424         case 0x26: /* stqf */
 425         case 0x36: /* stqfa */
 426         case 0x25: /* stfsr */
 427         case 0x3c: /* casa */
 428         case 0x3e: /* casxa */
 429             is_write = 1;
 430             break;
 431         }
 432     }
 433     return handle_cpu_signal(pc, info, is_write, sigmask);
 434 }
 435
 436 #elif defined(__arm__)
 437
 438 #if defined(__NetBSD__)
 439 #include <ucontext.h>
 440 #endif
 441
 442 int cpu_signal_handler(int host_signum, void *pinfo,
 443                        void *puc)
 444 {
 445     siginfo_t *info = pinfo;
 446 #if defined(__NetBSD__)
 447     ucontext_t *uc = puc;
 448 #else
 449     ucontext_t *uc = puc;
 450 #endif
 451     unsigned long pc;
 452     int is_write;
 453
 454 #if defined(__NetBSD__)
 455     pc = uc->uc_mcontext.__gregs[_REG_R15];
 456 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 457     pc = uc->uc_mcontext.gregs[R15];
 458 #else
 459     pc = uc->uc_mcontext.arm_pc;
 460 #endif
 461
 462     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 463      * later processor; on v5 we will always report this as a read).
 464      */
 465     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 466     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 467 }
 468
 469 #elif defined(__aarch64__)
 470
 471 #ifndef ESR_MAGIC
 472 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
 473 #define ESR_MAGIC 0x45535201
 474 struct esr_context {
 475     struct _aarch64_ctx head;
 476     uint64_t esr;
 477 };
 478 #endif
 479
 480 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
 481 {
 482     return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
 483 }
 484
 485 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
 486 {
 487     return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
 488 }
 489
 490 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 491 {
 492     siginfo_t *info = pinfo;
 493     ucontext_t *uc = puc;
 494     uintptr_t pc = uc->uc_mcontext.pc;
 495     bool is_write;
 496     struct _aarch64_ctx *hdr;
 497     struct esr_context const *esrctx = NULL;
 498
 499     /* Find the esr_context, which has the WnR bit in it */
 500     for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
 501         if (hdr->magic == ESR_MAGIC) {
 502             esrctx = (struct esr_context const *)hdr;
 503             break;
 504         }
 505     }
 506
 507     if (esrctx) {
 508         /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
 509         uint64_t esr = esrctx->esr;
 510         is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
 511     } else {
 512         /*
 513          * Fall back to parsing instructions; will only be needed
 514          * for really ancient (pre-3.16) kernels.
 515          */
 516         uint32_t insn = *(uint32_t *)pc;
 517
 518         is_write = ((insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */
 519                     || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */
 520                     || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */
 521                     || (insn & 0xbfc00000) == 0x0d800000   /* C3.3.4 */
 522                     || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */
 523                     || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */
 524                     || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */
 525                     /* Ignore bits 10, 11 & 21, controlling indexing.  */
 526                     || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */
 527                     || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */
 528                     /* Ignore bits 23 & 24, controlling indexing.  */
 529                     || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
 530     }
 531     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 532 }
 533
 534 #elif defined(__s390__)
 535
 536 int cpu_signal_handler(int host_signum, void *pinfo,
 537                        void *puc)
 538 {
 539     siginfo_t *info = pinfo;
 540     ucontext_t *uc = puc;
 541     unsigned long pc;
 542     uint16_t *pinsn;
 543     int is_write = 0;
 544
 545     pc = uc->uc_mcontext.psw.addr;
 546
 547     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 548        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 549        from the hardware which does in fact contain the is_write value.
 550        The rt signal handler, as far as I can tell, does not give this value
 551        at all.  Not that we could get to it from here even if it were.  */
 552     /* ??? This is not even close to complete, since it ignores all
 553        of the read-modify-write instructions.  */
 554     pinsn = (uint16_t *)pc;
 555     switch (pinsn[0] >> 8) {
 556     case 0x50: /* ST */
 557     case 0x42: /* STC */
 558     case 0x40: /* STH */
 559         is_write = 1;
 560         break;
 561     case 0xc4: /* RIL format insns */
 562         switch (pinsn[0] & 0xf) {
 563         case 0xf: /* STRL */
 564         case 0xb: /* STGRL */
 565         case 0x7: /* STHRL */
 566             is_write = 1;
 567         }
 568         break;
 569     case 0xe3: /* RXY format insns */
 570         switch (pinsn[2] & 0xff) {
 571         case 0x50: /* STY */
 572         case 0x24: /* STG */
 573         case 0x72: /* STCY */
 574         case 0x70: /* STHY */
 575         case 0x8e: /* STPQ */
 576         case 0x3f: /* STRVH */
 577         case 0x3e: /* STRV */
 578         case 0x2f: /* STRVG */
 579             is_write = 1;
 580         }
 581         break;
 582     }
 583     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 584 }
 585
 586 #elif defined(__mips__)
 587
 588 int cpu_signal_handler(int host_signum, void *pinfo,
 589                        void *puc)
 590 {
 591     siginfo_t *info = pinfo;
 592     ucontext_t *uc = puc;
 593     greg_t pc = uc->uc_mcontext.pc;
 594     int is_write;
 595
 596     /* XXX: compute is_write */
 597     is_write = 0;
 598     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 599 }
 600
 601 #elif defined(__riscv)
 602
 603 int cpu_signal_handler(int host_signum, void *pinfo,
 604                        void *puc)
 605 {
 606     siginfo_t *info = pinfo;
 607     ucontext_t *uc = puc;
 608     greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
 609     uint32_t insn = *(uint32_t *)pc;
 610     int is_write = 0;
 611
 612     /* Detect store by reading the instruction at the program
 613        counter. Note: we currently only generate 32-bit
 614        instructions so we thus only detect 32-bit stores */
 615     switch (((insn >> 0) & 0b11)) {
 616     case 3:
 617         switch (((insn >> 2) & 0b11111)) {
 618         case 8:
 619             switch (((insn >> 12) & 0b111)) {
 620             case 0: /* sb */
 621             case 1: /* sh */
 622             case 2: /* sw */
 623             case 3: /* sd */
 624             case 4: /* sq */
 625                 is_write = 1;
 626                 break;
 627             default:
 628                 break;
 629             }
 630             break;
 631         case 9:
 632             switch (((insn >> 12) & 0b111)) {
 633             case 2: /* fsw */
 634             case 3: /* fsd */
 635             case 4: /* fsq */
 636                 is_write = 1;
 637                 break;
 638             default:
 639                 break;
 640             }
 641             break;
 642         default:
 643             break;
 644         }
 645     }
 646
 647     /* Check for compressed instructions */
 648     switch (((insn >> 13) & 0b111)) {
 649     case 7:
 650         switch (insn & 0b11) {
 651         case 0: /*c.sd */
 652         case 2: /* c.sdsp */
 653             is_write = 1;
 654             break;
 655         default:
 656             break;
 657         }
 658         break;
 659     case 6:
 660         switch (insn & 0b11) {
 661         case 0: /* c.sw */
 662         case 3: /* c.swsp */
 663             is_write = 1;
 664             break;
 665         default:
 666             break;
 667         }
 668         break;
 669     default:
 670         break;
 671     }
 672
 673     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 674 }
 675
 676 #else
 677
 678 #error host CPU specific signal handler needed
 679
 680 #endif
 681
 682 /* The softmmu versions of these helpers are in cputlb.c.  */
 683
 684 /* Do not allow unaligned operations to proceed.  Return the host address.  */
 685 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
 686                                int size, uintptr_t retaddr)
 687 {
 688     /* Enforce qemu required alignment.  */
 689     if (unlikely(addr & (size - 1))) {
 690         cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr);
 691     }
 692     helper_retaddr = retaddr;
 693     return g2h(addr);
 694 }
 695
 696 /* Macro to call the above, with local variables from the use context.  */
 697 #define ATOMIC_MMU_DECLS do {} while (0)
 698 #define ATOMIC_MMU_LOOKUP  atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
 699 #define ATOMIC_MMU_CLEANUP do { helper_retaddr = 0; } while (0)
 700
 701 #define ATOMIC_NAME(X)   HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
 702 #define EXTRA_ARGS
 703
 704 #define DATA_SIZE 1
 705 #include "atomic_template.h"
 706
 707 #define DATA_SIZE 2
 708 #include "atomic_template.h"
 709
 710 #define DATA_SIZE 4
 711 #include "atomic_template.h"
 712
 713 #ifdef CONFIG_ATOMIC64
 714 #define DATA_SIZE 8
 715 #include "atomic_template.h"
 716 #endif
 717
 718 /* The following is only callable from other helpers, and matches up
 719    with the softmmu version.  */
 720
 721 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128
 722
 723 #undef EXTRA_ARGS
 724 #undef ATOMIC_NAME
 725 #undef ATOMIC_MMU_LOOKUP
 726
 727 #define EXTRA_ARGS     , TCGMemOpIdx oi, uintptr_t retaddr
 728 #define ATOMIC_NAME(X) \
 729     HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
 730 #define ATOMIC_MMU_LOOKUP  atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
 731
 732 #define DATA_SIZE 16
 733 #include "atomic_template.h"
 734 #endif