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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/alpha/kernel/core_apecs.c
2 * linux/arch/alpha/kernel/core_apecs.c
4 * Rewritten for Apecs from the lca.c from:
6 * Written by David Mosberger (davidm@cs.arizona.edu) with some code
7 * taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit
10 * Code common to all APECS core logic chips.
13 #define __EXTERN_INLINE inline
15 #include <asm/core_apecs.h>
16 #undef __EXTERN_INLINE
18 #include <linux/types.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
22 #include <asm/ptrace.h>
30 * NOTE: Herein lie back-to-back mb instructions. They are magic.
31 * One plausible explanation is that the i/o controller does not properly
32 * handle the system transaction. Another involves timing. Ho hum.
36 * BIOS32-style PCI interface:
39 #define DEBUG_CONFIG 0
42 # define DBGC(args) printk args
47 #define vuip volatile unsigned int *
50 * Given a bus, device, and function number, compute resulting
51 * configuration space address and setup the APECS_HAXR2 register
52 * accordingly. It is therefore not safe to have concurrent
53 * invocations to configuration space access routines, but there
54 * really shouldn't be any need for this.
58 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
59 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
60 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
61 * | | | | | | | | | | | | | | | | | | | | | | | |F|F|F|R|R|R|R|R|R|0|0|
62 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
64 * 31:11 Device select bit.
65 * 10:8 Function number
70 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
71 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
73 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
74 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
77 * 23:16 bus number (8 bits = 128 possible buses)
78 * 15:11 Device number (5 bits)
79 * 10:8 function number
83 * The function number selects which function of a multi-function device
84 * (e.g., SCSI and Ethernet).
86 * The register selects a DWORD (32 bit) register offset. Hence it
87 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
92 mk_conf_addr(struct pci_bus
*pbus
, unsigned int device_fn
, int where
,
93 unsigned long *pci_addr
, unsigned char *type1
)
96 u8 bus
= pbus
->number
;
98 DBGC(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
99 " pci_addr=0x%p, type1=0x%p)\n",
100 bus
, device_fn
, where
, pci_addr
, type1
));
103 int device
= device_fn
>> 3;
105 /* type 0 configuration cycle: */
108 DBGC(("mk_conf_addr: device (%d) > 20, returning -1\n",
114 addr
= (device_fn
<< 8) | (where
);
116 /* type 1 configuration cycle: */
118 addr
= (bus
<< 16) | (device_fn
<< 8) | (where
);
121 DBGC(("mk_conf_addr: returning pci_addr 0x%lx\n", addr
));
126 conf_read(unsigned long addr
, unsigned char type1
)
129 unsigned int stat0
, value
;
130 unsigned int haxr2
= 0;
132 local_irq_save(flags
); /* avoid getting hit by machine check */
134 DBGC(("conf_read(addr=0x%lx, type1=%d)\n", addr
, type1
));
136 /* Reset status register to avoid losing errors. */
137 stat0
= *(vuip
)APECS_IOC_DCSR
;
138 *(vuip
)APECS_IOC_DCSR
= stat0
;
140 DBGC(("conf_read: APECS DCSR was 0x%x\n", stat0
));
142 /* If Type1 access, must set HAE #2. */
144 haxr2
= *(vuip
)APECS_IOC_HAXR2
;
146 *(vuip
)APECS_IOC_HAXR2
= haxr2
| 1;
147 DBGC(("conf_read: TYPE1 access\n"));
151 mcheck_expected(0) = 1;
155 /* Access configuration space. */
157 /* Some SRMs step on these registers during a machine check. */
158 asm volatile("ldl %0,%1; mb; mb" : "=r"(value
) : "m"(*(vuip
)addr
)
159 : "$9", "$10", "$11", "$12", "$13", "$14", "memory");
161 if (mcheck_taken(0)) {
166 mcheck_expected(0) = 0;
171 * david.rusling@reo.mts.dec.com. This code is needed for the
172 * EB64+ as it does not generate a machine check (why I don't
173 * know). When we build kernels for one particular platform
174 * then we can make this conditional on the type.
178 /* Now look for any errors. */
179 stat0
= *(vuip
)APECS_IOC_DCSR
;
180 DBGC(("conf_read: APECS DCSR after read 0x%x\n", stat0
));
182 /* Is any error bit set? */
183 if (stat0
& 0xffe0U
) {
184 /* If not NDEV, print status. */
185 if (!(stat0
& 0x0800)) {
186 printk("apecs.c:conf_read: got stat0=%x\n", stat0
);
189 /* Reset error status. */
190 *(vuip
)APECS_IOC_DCSR
= stat0
;
192 wrmces(0x7); /* reset machine check */
197 /* If Type1 access, must reset HAE #2 so normal IO space ops work. */
199 *(vuip
)APECS_IOC_HAXR2
= haxr2
& ~1;
202 local_irq_restore(flags
);
208 conf_write(unsigned long addr
, unsigned int value
, unsigned char type1
)
212 unsigned int haxr2
= 0;
214 local_irq_save(flags
); /* avoid getting hit by machine check */
216 /* Reset status register to avoid losing errors. */
217 stat0
= *(vuip
)APECS_IOC_DCSR
;
218 *(vuip
)APECS_IOC_DCSR
= stat0
;
221 /* If Type1 access, must set HAE #2. */
223 haxr2
= *(vuip
)APECS_IOC_HAXR2
;
225 *(vuip
)APECS_IOC_HAXR2
= haxr2
| 1;
229 mcheck_expected(0) = 1;
232 /* Access configuration space. */
236 mcheck_expected(0) = 0;
241 * david.rusling@reo.mts.dec.com. This code is needed for the
242 * EB64+ as it does not generate a machine check (why I don't
243 * know). When we build kernels for one particular platform
244 * then we can make this conditional on the type.
248 /* Now look for any errors. */
249 stat0
= *(vuip
)APECS_IOC_DCSR
;
251 /* Is any error bit set? */
252 if (stat0
& 0xffe0U
) {
253 /* If not NDEV, print status. */
254 if (!(stat0
& 0x0800)) {
255 printk("apecs.c:conf_write: got stat0=%x\n", stat0
);
258 /* Reset error status. */
259 *(vuip
)APECS_IOC_DCSR
= stat0
;
261 wrmces(0x7); /* reset machine check */
265 /* If Type1 access, must reset HAE #2 so normal IO space ops work. */
267 *(vuip
)APECS_IOC_HAXR2
= haxr2
& ~1;
270 local_irq_restore(flags
);
274 apecs_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
275 int size
, u32
*value
)
277 unsigned long addr
, pci_addr
;
282 if (mk_conf_addr(bus
, devfn
, where
, &pci_addr
, &type1
))
283 return PCIBIOS_DEVICE_NOT_FOUND
;
285 mask
= (size
- 1) * 8;
286 shift
= (where
& 3) * 8;
287 addr
= (pci_addr
<< 5) + mask
+ APECS_CONF
;
288 *value
= conf_read(addr
, type1
) >> (shift
);
289 return PCIBIOS_SUCCESSFUL
;
293 apecs_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
296 unsigned long addr
, pci_addr
;
300 if (mk_conf_addr(bus
, devfn
, where
, &pci_addr
, &type1
))
301 return PCIBIOS_DEVICE_NOT_FOUND
;
303 mask
= (size
- 1) * 8;
304 addr
= (pci_addr
<< 5) + mask
+ APECS_CONF
;
305 conf_write(addr
, value
<< ((where
& 3) * 8), type1
);
306 return PCIBIOS_SUCCESSFUL
;
309 struct pci_ops apecs_pci_ops
=
311 .read
= apecs_read_config
,
312 .write
= apecs_write_config
,
316 apecs_pci_tbi(struct pci_controller
*hose
, dma_addr_t start
, dma_addr_t end
)
319 *(vip
)APECS_IOC_TBIA
= 0;
324 apecs_init_arch(void)
326 struct pci_controller
*hose
;
329 * Create our single hose.
332 pci_isa_hose
= hose
= alloc_pci_controller();
333 hose
->io_space
= &ioport_resource
;
334 hose
->mem_space
= &iomem_resource
;
337 hose
->sparse_mem_base
= APECS_SPARSE_MEM
- IDENT_ADDR
;
338 hose
->dense_mem_base
= APECS_DENSE_MEM
- IDENT_ADDR
;
339 hose
->sparse_io_base
= APECS_IO
- IDENT_ADDR
;
340 hose
->dense_io_base
= 0;
343 * Set up the PCI to main memory translation windows.
345 * Window 1 is direct access 1GB at 1GB
346 * Window 2 is scatter-gather 8MB at 8MB (for isa)
348 hose
->sg_isa
= iommu_arena_new(hose
, 0x00800000, 0x00800000, 0);
350 __direct_map_base
= 0x40000000;
351 __direct_map_size
= 0x40000000;
353 *(vuip
)APECS_IOC_PB1R
= __direct_map_base
| 0x00080000;
354 *(vuip
)APECS_IOC_PM1R
= (__direct_map_size
- 1) & 0xfff00000U
;
355 *(vuip
)APECS_IOC_TB1R
= 0;
357 *(vuip
)APECS_IOC_PB2R
= hose
->sg_isa
->dma_base
| 0x000c0000;
358 *(vuip
)APECS_IOC_PM2R
= (hose
->sg_isa
->size
- 1) & 0xfff00000;
359 *(vuip
)APECS_IOC_TB2R
= virt_to_phys(hose
->sg_isa
->ptes
) >> 1;
361 apecs_pci_tbi(hose
, 0, -1);
364 * Finally, clear the HAXR2 register, which gets used
365 * for PCI Config Space accesses. That is the way
366 * we want to use it, and we do not want to depend on
367 * what ARC or SRM might have left behind...
369 *(vuip
)APECS_IOC_HAXR2
= 0;
374 apecs_pci_clr_err(void)
378 jd
= *(vuip
)APECS_IOC_DCSR
;
380 *(vuip
)APECS_IOC_SEAR
;
381 *(vuip
)APECS_IOC_DCSR
= jd
| 0xffe1L
;
383 *(vuip
)APECS_IOC_DCSR
;
385 *(vuip
)APECS_IOC_TBIA
= (unsigned int)APECS_IOC_TBIA
;
387 *(vuip
)APECS_IOC_TBIA
;
391 apecs_machine_check(unsigned long vector
, unsigned long la_ptr
)
393 struct el_common
*mchk_header
;
394 struct el_apecs_procdata
*mchk_procdata
;
395 struct el_apecs_sysdata_mcheck
*mchk_sysdata
;
397 mchk_header
= (struct el_common
*)la_ptr
;
399 mchk_procdata
= (struct el_apecs_procdata
*)
400 (la_ptr
+ mchk_header
->proc_offset
401 - sizeof(mchk_procdata
->paltemp
));
403 mchk_sysdata
= (struct el_apecs_sysdata_mcheck
*)
404 (la_ptr
+ mchk_header
->sys_offset
);
407 /* Clear the error before any reporting. */
412 wrmces(0x7); /* reset machine check pending flag */
415 process_mcheck_info(vector
, la_ptr
, "APECS",
417 && (mchk_sysdata
->epic_dcsr
& 0x0c00UL
)));