2 * linux/arch/alpha/kernel/core_marvel.c
4 * Code common to all Marvel based systems.
7 #define __EXTERN_INLINE inline
9 #include <asm/core_marvel.h>
10 #undef __EXTERN_INLINE
12 #include <linux/types.h>
13 #include <linux/pci.h>
14 #include <linux/sched.h>
15 #include <linux/init.h>
16 #include <linux/vmalloc.h>
17 #include <linux/mc146818rtc.h>
18 #include <linux/rtc.h>
19 #include <linux/module.h>
20 #include <linux/bootmem.h>
22 #include <asm/ptrace.h>
25 #include <asm/pgalloc.h>
26 #include <asm/tlbflush.h>
36 #define DEBUG_CONFIG 0
39 # define DBG_CFG(args) printk args
41 # define DBG_CFG(args)
48 static struct io7
*io7_head
= NULL
;
54 static unsigned long __attribute__ ((unused
))
55 read_ev7_csr(int pe
, unsigned long offset
)
57 ev7_csr
*ev7csr
= EV7_CSR_KERN(pe
, offset
);
67 static void __attribute__ ((unused
))
68 write_ev7_csr(int pe
, unsigned long offset
, unsigned long q
)
70 ev7_csr
*ev7csr
= EV7_CSR_KERN(pe
, offset
);
78 mk_resource_name(int pe
, int port
, char *str
)
83 sprintf(tmp
, "PCI %s PE %d PORT %d", str
, pe
, port
);
84 name
= alloc_bootmem(strlen(tmp
) + 1);
91 marvel_next_io7(struct io7
*prev
)
93 return (prev
? prev
->next
: io7_head
);
97 marvel_find_io7(int pe
)
101 for (io7
= io7_head
; io7
&& io7
->pe
!= pe
; io7
= io7
->next
)
107 static struct io7
* __init
108 alloc_io7(unsigned int pe
)
114 if (marvel_find_io7(pe
)) {
115 printk(KERN_WARNING
"IO7 at PE %d already allocated!\n", pe
);
119 io7
= alloc_bootmem(sizeof(*io7
));
121 spin_lock_init(&io7
->irq_lock
);
123 for (h
= 0; h
< 4; h
++) {
124 io7
->ports
[h
].io7
= io7
;
125 io7
->ports
[h
].port
= h
;
126 io7
->ports
[h
].enabled
= 0; /* default to disabled */
130 * Insert in pe sorted order.
132 if (NULL
== io7_head
) /* empty list */
134 else if (io7_head
->pe
> io7
->pe
) { /* insert at head */
135 io7
->next
= io7_head
;
137 } else { /* insert at position */
138 for (insp
= io7_head
; insp
; insp
= insp
->next
) {
139 if (insp
->pe
== io7
->pe
) {
140 printk(KERN_ERR
"Too many IO7s at PE %d\n",
145 if (NULL
== insp
->next
||
146 insp
->next
->pe
> io7
->pe
) { /* insert here */
147 io7
->next
= insp
->next
;
153 if (NULL
== insp
) { /* couldn't insert ?!? */
154 printk(KERN_WARNING
"Failed to insert IO7 at PE %d "
155 " - adding at head of list\n", io7
->pe
);
156 io7
->next
= io7_head
;
165 io7_clear_errors(struct io7
*io7
)
167 io7_port7_csrs
*p7csrs
;
168 io7_ioport_csrs
*csrs
;
173 * First the IO ports.
175 for (port
= 0; port
< 4; port
++) {
176 csrs
= IO7_CSRS_KERN(io7
->pe
, port
);
178 csrs
->POx_ERR_SUM
.csr
= -1UL;
179 csrs
->POx_TLB_ERR
.csr
= -1UL;
180 csrs
->POx_SPL_COMPLT
.csr
= -1UL;
181 csrs
->POx_TRANS_SUM
.csr
= -1UL;
185 * Then the common ones.
187 p7csrs
= IO7_PORT7_CSRS_KERN(io7
->pe
);
189 p7csrs
->PO7_ERROR_SUM
.csr
= -1UL;
190 p7csrs
->PO7_UNCRR_SYM
.csr
= -1UL;
191 p7csrs
->PO7_CRRCT_SYM
.csr
= -1UL;
196 * IO7 PCI, PCI/X, AGP configuration.
199 io7_init_hose(struct io7
*io7
, int port
)
201 static int hose_index
= 0;
203 struct pci_controller
*hose
= alloc_pci_controller();
204 struct io7_port
*io7_port
= &io7
->ports
[port
];
205 io7_ioport_csrs
*csrs
= IO7_CSRS_KERN(io7
->pe
, port
);
208 hose
->index
= hose_index
++; /* arbitrary */
211 * We don't have an isa or legacy hose, but glibc expects to be
212 * able to use the bus == 0 / dev == 0 form of the iobase syscall
213 * to determine information about the i/o system. Since XFree86
214 * relies on glibc's determination to tell whether or not to use
215 * sparse access, we need to point the pci_isa_hose at a real hose
216 * so at least that determination is correct.
218 if (hose
->index
== 0)
221 io7_port
->csrs
= csrs
;
222 io7_port
->hose
= hose
;
223 hose
->sysdata
= io7_port
;
225 hose
->io_space
= alloc_resource();
226 hose
->mem_space
= alloc_resource();
229 * Base addresses for userland consumption. Since these are going
230 * to be mapped, they are pure physical addresses.
232 hose
->sparse_mem_base
= hose
->sparse_io_base
= 0;
233 hose
->dense_mem_base
= IO7_MEM_PHYS(io7
->pe
, port
);
234 hose
->dense_io_base
= IO7_IO_PHYS(io7
->pe
, port
);
237 * Base addresses and resource ranges for kernel consumption.
239 hose
->config_space_base
= (unsigned long)IO7_CONF_KERN(io7
->pe
, port
);
241 hose
->io_space
->start
= (unsigned long)IO7_IO_KERN(io7
->pe
, port
);
242 hose
->io_space
->end
= hose
->io_space
->start
+ IO7_IO_SPACE
- 1;
243 hose
->io_space
->name
= mk_resource_name(io7
->pe
, port
, "IO");
244 hose
->io_space
->flags
= IORESOURCE_IO
;
246 hose
->mem_space
->start
= (unsigned long)IO7_MEM_KERN(io7
->pe
, port
);
247 hose
->mem_space
->end
= hose
->mem_space
->start
+ IO7_MEM_SPACE
- 1;
248 hose
->mem_space
->name
= mk_resource_name(io7
->pe
, port
, "MEM");
249 hose
->mem_space
->flags
= IORESOURCE_MEM
;
251 if (request_resource(&ioport_resource
, hose
->io_space
) < 0)
252 printk(KERN_ERR
"Failed to request IO on hose %d\n",
254 if (request_resource(&iomem_resource
, hose
->mem_space
) < 0)
255 printk(KERN_ERR
"Failed to request MEM on hose %d\n",
259 * Save the existing DMA window settings for later restoration.
261 for (i
= 0; i
< 4; i
++) {
262 io7_port
->saved_wbase
[i
] = csrs
->POx_WBASE
[i
].csr
;
263 io7_port
->saved_wmask
[i
] = csrs
->POx_WMASK
[i
].csr
;
264 io7_port
->saved_tbase
[i
] = csrs
->POx_TBASE
[i
].csr
;
268 * Set up the PCI to main memory translation windows.
270 * Window 0 is scatter-gather 8MB at 8MB
271 * Window 1 is direct access 1GB at 2GB
272 * Window 2 is scatter-gather (up-to) 1GB at 3GB
273 * Window 3 is disabled
277 * TBIA before modifying windows.
279 marvel_pci_tbi(hose
, 0, -1);
282 * Set up window 0 for scatter-gather 8MB at 8MB.
284 hose
->sg_isa
= iommu_arena_new_node(marvel_cpuid_to_nid(io7
->pe
),
285 hose
, 0x00800000, 0x00800000, 0);
286 hose
->sg_isa
->align_entry
= 8; /* cache line boundary */
287 csrs
->POx_WBASE
[0].csr
=
288 hose
->sg_isa
->dma_base
| wbase_m_ena
| wbase_m_sg
;
289 csrs
->POx_WMASK
[0].csr
= (hose
->sg_isa
->size
- 1) & wbase_m_addr
;
290 csrs
->POx_TBASE
[0].csr
= virt_to_phys(hose
->sg_isa
->ptes
);
293 * Set up window 1 for direct-mapped 1GB at 2GB.
295 csrs
->POx_WBASE
[1].csr
= __direct_map_base
| wbase_m_ena
;
296 csrs
->POx_WMASK
[1].csr
= (__direct_map_size
- 1) & wbase_m_addr
;
297 csrs
->POx_TBASE
[1].csr
= 0;
300 * Set up window 2 for scatter-gather (up-to) 1GB at 3GB.
302 hose
->sg_pci
= iommu_arena_new_node(marvel_cpuid_to_nid(io7
->pe
),
303 hose
, 0xc0000000, 0x40000000, 0);
304 hose
->sg_pci
->align_entry
= 8; /* cache line boundary */
305 csrs
->POx_WBASE
[2].csr
=
306 hose
->sg_pci
->dma_base
| wbase_m_ena
| wbase_m_sg
;
307 csrs
->POx_WMASK
[2].csr
= (hose
->sg_pci
->size
- 1) & wbase_m_addr
;
308 csrs
->POx_TBASE
[2].csr
= virt_to_phys(hose
->sg_pci
->ptes
);
313 csrs
->POx_WBASE
[3].csr
= 0;
316 * Make sure that the AGP Monster Window is disabled.
318 csrs
->POx_CTRL
.csr
&= ~(1UL << 61);
321 printk("FIXME: disabling master aborts\n");
322 csrs
->POx_MSK_HEI
.csr
&= ~(3UL << 14);
325 * TBIA after modifying windows.
327 marvel_pci_tbi(hose
, 0, -1);
331 marvel_init_io7(struct io7
*io7
)
335 printk("Initializing IO7 at PID %d\n", io7
->pe
);
338 * Get the Port 7 CSR pointer.
340 io7
->csrs
= IO7_PORT7_CSRS_KERN(io7
->pe
);
343 * Init this IO7's hoses.
345 for (i
= 0; i
< IO7_NUM_PORTS
; i
++) {
346 io7_ioport_csrs
*csrs
= IO7_CSRS_KERN(io7
->pe
, i
);
347 if (csrs
->POx_CACHE_CTL
.csr
== 8) {
348 io7
->ports
[i
].enabled
= 1;
349 io7_init_hose(io7
, i
);
355 marvel_io7_present(gct6_node
*node
)
359 if (node
->type
!= GCT_TYPE_HOSE
||
360 node
->subtype
!= GCT_SUBTYPE_IO_PORT_MODULE
)
363 pe
= (node
->id
>> 8) & 0xff;
364 printk("Found an IO7 at PID %d\n", pe
);
370 marvel_find_console_vga_hose(void)
372 #ifdef CONFIG_VGA_HOSE
373 u64
*pu64
= (u64
*)((u64
)hwrpb
+ hwrpb
->ctbt_offset
);
375 if (pu64
[7] == 3) { /* TERM_TYPE == graphics */
376 struct pci_controller
*hose
= NULL
;
377 int h
= (pu64
[30] >> 24) & 0xff; /* TERM_OUT_LOC, hose # */
381 /* FIXME - encoding is going to have to change for Marvel
382 * since hose will be able to overflow a byte...
383 * need to fix this decode when the console
384 * changes its encoding
386 printk("console graphics is on hose %d (console)\n", h
);
389 * The console's hose numbering is:
394 * We need to find the hose at that pid and port
398 if ((io7
= marvel_find_io7(pid
)))
399 hose
= io7
->ports
[port
].hose
;
402 printk("Console graphics on hose %d\n", hose
->index
);
409 gct6_search_struct gct_wanted_node_list
[] __initdata
= {
410 { GCT_TYPE_HOSE
, GCT_SUBTYPE_IO_PORT_MODULE
, marvel_io7_present
},
415 * In case the GCT is not complete, let the user specify PIDs with IO7s
416 * at boot time. Syntax is 'io7=a,b,c,...,n' where a-n are the PIDs (decimal)
417 * where IO7s are connected
420 marvel_specify_io7(char *str
)
427 pid
= simple_strtoul(str
, &pchar
, 0);
429 printk("User-specified IO7 at PID %lu\n", pid
);
430 io7
= alloc_io7(pid
);
431 if (io7
) marvel_init_io7(io7
);
434 if (pchar
== str
) pchar
++;
440 __setup("io7=", marvel_specify_io7
);
443 marvel_init_arch(void)
447 /* With multiple PCI busses, we play with I/O as physical addrs. */
448 ioport_resource
.end
= ~0UL;
450 /* PCI DMA Direct Mapping is 1GB at 2GB. */
451 __direct_map_base
= 0x80000000;
452 __direct_map_size
= 0x40000000;
454 /* Parse the config tree. */
455 gct6_find_nodes(GCT_NODE_PTR(0), gct_wanted_node_list
);
458 for (io7
= NULL
; NULL
!= (io7
= marvel_next_io7(io7
)); )
459 marvel_init_io7(io7
);
461 /* Check for graphic console location (if any). */
462 marvel_find_console_vga_hose();
466 marvel_kill_arch(int mode
)
472 * PCI Configuration Space access functions
474 * Configuration space addresses have the following format:
476 * |2 2 2 2|1 1 1 1|1 1 1 1|1 1
477 * |3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
478 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
479 * |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|R|R|
480 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
482 * n:24 reserved for hose base
483 * 23:16 bus number (8 bits = 128 possible buses)
484 * 15:11 Device number (5 bits)
485 * 10:8 function number
486 * 7:2 register number
489 * IO7 determines whether to use a type 0 or type 1 config cycle
490 * based on the bus number. Therefore the bus number must be set
491 * to 0 for the root bus on any hose.
493 * The function number selects which function of a multi-function device
494 * (e.g., SCSI and Ethernet).
498 static inline unsigned long
499 build_conf_addr(struct pci_controller
*hose
, u8 bus
,
500 unsigned int devfn
, int where
)
502 return (hose
->config_space_base
| (bus
<< 16) | (devfn
<< 8) | where
);
506 mk_conf_addr(struct pci_bus
*pbus
, unsigned int devfn
, int where
)
508 struct pci_controller
*hose
= pbus
->sysdata
;
509 struct io7_port
*io7_port
;
510 unsigned long addr
= 0;
511 u8 bus
= pbus
->number
;
516 /* Check for enabled. */
517 io7_port
= hose
->sysdata
;
518 if (!io7_port
->enabled
)
521 if (!pbus
->parent
) { /* No parent means peer PCI bus. */
522 /* Don't support idsel > 20 on primary bus. */
523 if (devfn
>= PCI_DEVFN(21, 0))
528 addr
= build_conf_addr(hose
, bus
, devfn
, where
);
530 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr
));
535 marvel_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
536 int size
, u32
*value
)
540 if (0 == (addr
= mk_conf_addr(bus
, devfn
, where
)))
541 return PCIBIOS_DEVICE_NOT_FOUND
;
545 *value
= __kernel_ldbu(*(vucp
)addr
);
548 *value
= __kernel_ldwu(*(vusp
)addr
);
551 *value
= *(vuip
)addr
;
554 return PCIBIOS_FUNC_NOT_SUPPORTED
;
557 return PCIBIOS_SUCCESSFUL
;
561 marvel_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
566 if (0 == (addr
= mk_conf_addr(bus
, devfn
, where
)))
567 return PCIBIOS_DEVICE_NOT_FOUND
;
571 __kernel_stb(value
, *(vucp
)addr
);
573 __kernel_ldbu(*(vucp
)addr
);
576 __kernel_stw(value
, *(vusp
)addr
);
578 __kernel_ldwu(*(vusp
)addr
);
586 return PCIBIOS_FUNC_NOT_SUPPORTED
;
589 return PCIBIOS_SUCCESSFUL
;
592 struct pci_ops marvel_pci_ops
=
594 .read
= marvel_read_config
,
595 .write
= marvel_write_config
,
600 * Other PCI helper functions.
603 marvel_pci_tbi(struct pci_controller
*hose
, dma_addr_t start
, dma_addr_t end
)
605 io7_ioport_csrs
*csrs
= ((struct io7_port
*)hose
->sysdata
)->csrs
;
608 csrs
->POx_SG_TBIA
.csr
= 0;
610 csrs
->POx_SG_TBIA
.csr
;
618 struct marvel_rtc_access_info
{
619 unsigned long function
;
625 __marvel_access_rtc(void *info
)
627 struct marvel_rtc_access_info
*rtc_access
= info
;
629 register unsigned long __r0
__asm__("$0");
630 register unsigned long __r16
__asm__("$16") = rtc_access
->function
;
631 register unsigned long __r17
__asm__("$17") = rtc_access
->index
;
632 register unsigned long __r18
__asm__("$18") = rtc_access
->data
;
634 __asm__
__volatile__(
635 "call_pal %4 # cserve rtc"
636 : "=r"(__r16
), "=r"(__r17
), "=r"(__r18
), "=r"(__r0
)
637 : "i"(PAL_cserve
), "0"(__r16
), "1"(__r17
), "2"(__r18
)
638 : "$1", "$22", "$23", "$24", "$25");
640 rtc_access
->data
= __r0
;
644 __marvel_rtc_io(u8 b
, unsigned long addr
, int write
)
648 struct marvel_rtc_access_info rtc_access
;
652 case 0x70: /* RTC_PORT(0) */
653 if (write
) index
= b
;
657 case 0x71: /* RTC_PORT(1) */
658 rtc_access
.index
= index
;
659 rtc_access
.data
= bcd2bin(b
);
660 rtc_access
.function
= 0x48 + !write
; /* GET/PUT_TOY */
662 __marvel_access_rtc(&rtc_access
);
664 ret
= bin2bcd(rtc_access
.data
);
668 printk(KERN_WARNING
"Illegal RTC port %lx\n", addr
);
680 marvel_ioremap(unsigned long addr
, unsigned long size
)
682 struct pci_controller
*hose
;
683 unsigned long baddr
, last
;
684 struct vm_struct
*area
;
690 * Adjust the address.
692 FIXUP_MEMADDR_VGA(addr
);
697 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
698 if ((addr
>> 32) == (hose
->mem_space
->start
>> 32))
705 * We have the hose - calculate the bus limits.
707 baddr
= addr
- hose
->mem_space
->start
;
708 last
= baddr
+ size
- 1;
711 * Is it direct-mapped?
713 if ((baddr
>= __direct_map_base
) &&
714 ((baddr
+ size
- 1) < __direct_map_base
+ __direct_map_size
)) {
715 addr
= IDENT_ADDR
| (baddr
- __direct_map_base
);
716 return (void __iomem
*) addr
;
720 * Check the scatter-gather arena.
723 baddr
>= (unsigned long)hose
->sg_pci
->dma_base
&&
724 last
< (unsigned long)hose
->sg_pci
->dma_base
+ hose
->sg_pci
->size
) {
727 * Adjust the limits (mappings must be page aligned)
729 baddr
-= hose
->sg_pci
->dma_base
;
730 last
-= hose
->sg_pci
->dma_base
;
732 size
= PAGE_ALIGN(last
) - baddr
;
737 area
= get_vm_area(size
, VM_IOREMAP
);
741 ptes
= hose
->sg_pci
->ptes
;
742 for (vaddr
= (unsigned long)area
->addr
;
744 baddr
+= PAGE_SIZE
, vaddr
+= PAGE_SIZE
) {
745 pfn
= ptes
[baddr
>> PAGE_SHIFT
];
747 printk("ioremap failed... pte not valid...\n");
751 pfn
>>= 1; /* make it a true pfn */
753 if (__alpha_remap_area_pages(vaddr
,
756 printk("FAILED to map...\n");
764 vaddr
= (unsigned long)area
->addr
+ (addr
& ~PAGE_MASK
);
766 return (void __iomem
*) vaddr
;
769 /* Assume it was already a reasonable address */
770 vaddr
= baddr
+ hose
->mem_space
->start
;
771 return (void __iomem
*) vaddr
;
775 marvel_iounmap(volatile void __iomem
*xaddr
)
777 unsigned long addr
= (unsigned long) xaddr
;
778 if (addr
>= VMALLOC_START
)
779 vfree((void *)(PAGE_MASK
& addr
));
783 marvel_is_mmio(const volatile void __iomem
*xaddr
)
785 unsigned long addr
= (unsigned long) xaddr
;
787 if (addr
>= VMALLOC_START
)
790 return (addr
& 0xFF000000UL
) == 0;
793 #define __marvel_is_port_kbd(a) (((a) == 0x60) || ((a) == 0x64))
794 #define __marvel_is_port_rtc(a) (((a) == 0x70) || ((a) == 0x71))
796 void __iomem
*marvel_ioportmap (unsigned long addr
)
798 FIXUP_IOADDR_VGA(addr
);
799 return (void __iomem
*)addr
;
803 marvel_ioread8(void __iomem
*xaddr
)
805 unsigned long addr
= (unsigned long) xaddr
;
806 if (__marvel_is_port_kbd(addr
))
808 else if (__marvel_is_port_rtc(addr
))
809 return __marvel_rtc_io(0, addr
, 0);
810 else if (marvel_is_ioaddr(addr
))
811 return __kernel_ldbu(*(vucp
)addr
);
813 /* this should catch other legacy addresses
814 that would normally fail on MARVEL,
815 because there really is nothing there...
821 marvel_iowrite8(u8 b
, void __iomem
*xaddr
)
823 unsigned long addr
= (unsigned long) xaddr
;
824 if (__marvel_is_port_kbd(addr
))
826 else if (__marvel_is_port_rtc(addr
))
827 __marvel_rtc_io(b
, addr
, 1);
828 else if (marvel_is_ioaddr(addr
))
829 __kernel_stb(b
, *(vucp
)addr
);
832 #ifndef CONFIG_ALPHA_GENERIC
833 EXPORT_SYMBOL(marvel_ioremap
);
834 EXPORT_SYMBOL(marvel_iounmap
);
835 EXPORT_SYMBOL(marvel_is_mmio
);
836 EXPORT_SYMBOL(marvel_ioportmap
);
837 EXPORT_SYMBOL(marvel_ioread8
);
838 EXPORT_SYMBOL(marvel_iowrite8
);
845 * FIXME - for now each cpu is a node by itself
846 * -- no real support for striped mode
850 marvel_pa_to_nid(unsigned long pa
)
854 if ((pa
>> 43) & 1) /* I/O */
855 cpuid
= (~(pa
>> 35) & 0xff);
857 cpuid
= ((pa
>> 34) & 0x3) | ((pa
>> (37 - 2)) & (0x1f << 2));
859 return marvel_cpuid_to_nid(cpuid
);
863 marvel_cpuid_to_nid(int cpuid
)
869 marvel_node_mem_start(int nid
)
873 pa
= (nid
& 0x3) | ((nid
& (0x1f << 2)) << 1);
880 marvel_node_mem_size(int nid
)
882 return 16UL * 1024 * 1024 * 1024; /* 16GB */
889 #include <linux/agp_backend.h>
890 #include <asm/agp_backend.h>
891 #include <linux/slab.h>
892 #include <linux/delay.h>
894 struct marvel_agp_aperture
{
895 struct pci_iommu_arena
*arena
;
901 marvel_agp_setup(alpha_agp_info
*agp
)
903 struct marvel_agp_aperture
*aper
;
905 if (!alpha_agpgart_size
)
908 aper
= kmalloc(sizeof(*aper
), GFP_KERNEL
);
909 if (aper
== NULL
) return -ENOMEM
;
911 aper
->arena
= agp
->hose
->sg_pci
;
912 aper
->pg_count
= alpha_agpgart_size
/ PAGE_SIZE
;
913 aper
->pg_start
= iommu_reserve(aper
->arena
, aper
->pg_count
,
916 if (aper
->pg_start
< 0) {
917 printk(KERN_ERR
"Failed to reserve AGP memory\n");
922 agp
->aperture
.bus_base
=
923 aper
->arena
->dma_base
+ aper
->pg_start
* PAGE_SIZE
;
924 agp
->aperture
.size
= aper
->pg_count
* PAGE_SIZE
;
925 agp
->aperture
.sysdata
= aper
;
931 marvel_agp_cleanup(alpha_agp_info
*agp
)
933 struct marvel_agp_aperture
*aper
= agp
->aperture
.sysdata
;
936 status
= iommu_release(aper
->arena
, aper
->pg_start
, aper
->pg_count
);
937 if (status
== -EBUSY
) {
939 "Attempted to release bound AGP memory - unbinding\n");
940 iommu_unbind(aper
->arena
, aper
->pg_start
, aper
->pg_count
);
941 status
= iommu_release(aper
->arena
, aper
->pg_start
,
945 printk(KERN_ERR
"Failed to release AGP memory\n");
952 marvel_agp_configure(alpha_agp_info
*agp
)
954 io7_ioport_csrs
*csrs
= ((struct io7_port
*)agp
->hose
->sysdata
)->csrs
;
955 struct io7
*io7
= ((struct io7_port
*)agp
->hose
->sysdata
)->io7
;
956 unsigned int new_rate
= 0;
957 unsigned long agp_pll
;
960 * Check the requested mode against the PLL setting.
961 * The agpgart_be code has not programmed the card yet,
962 * so we can still tweak mode here.
964 agp_pll
= io7
->csrs
->POx_RST
[IO7_AGP_PORT
].csr
;
965 switch(IO7_PLL_RNGB(agp_pll
)) {
966 case 0x4: /* 2x only */
968 * The PLL is only programmed for 2x, so adjust the
969 * rate to 2x, if necessary.
971 if (agp
->mode
.bits
.rate
!= 2)
975 case 0x6: /* 1x / 4x */
977 * The PLL is programmed for 1x or 4x. Don't go faster
978 * than requested, so if the requested rate is 2x, use 1x.
980 if (agp
->mode
.bits
.rate
== 2)
984 default: /* ??????? */
986 * Don't know what this PLL setting is, take the requested
987 * rate, but warn the user.
989 printk("%s: unknown PLL setting RNGB=%lx (PLL6_CTL=%016lx)\n",
990 __func__
, IO7_PLL_RNGB(agp_pll
), agp_pll
);
995 * Set the new rate, if necessary.
998 printk("Requested AGP Rate %dX not compatible "
999 "with PLL setting - using %dX\n",
1000 agp
->mode
.bits
.rate
,
1003 agp
->mode
.bits
.rate
= new_rate
;
1006 printk("Enabling AGP on hose %d: %dX%s RQ %d\n",
1007 agp
->hose
->index
, agp
->mode
.bits
.rate
,
1008 agp
->mode
.bits
.sba
? " - SBA" : "", agp
->mode
.bits
.rq
);
1010 csrs
->AGP_CMD
.csr
= agp
->mode
.lw
;
1016 marvel_agp_bind_memory(alpha_agp_info
*agp
, off_t pg_start
, struct agp_memory
*mem
)
1018 struct marvel_agp_aperture
*aper
= agp
->aperture
.sysdata
;
1019 return iommu_bind(aper
->arena
, aper
->pg_start
+ pg_start
,
1020 mem
->page_count
, mem
->pages
);
1024 marvel_agp_unbind_memory(alpha_agp_info
*agp
, off_t pg_start
, struct agp_memory
*mem
)
1026 struct marvel_agp_aperture
*aper
= agp
->aperture
.sysdata
;
1027 return iommu_unbind(aper
->arena
, aper
->pg_start
+ pg_start
,
1031 static unsigned long
1032 marvel_agp_translate(alpha_agp_info
*agp
, dma_addr_t addr
)
1034 struct marvel_agp_aperture
*aper
= agp
->aperture
.sysdata
;
1035 unsigned long baddr
= addr
- aper
->arena
->dma_base
;
1038 if (addr
< agp
->aperture
.bus_base
||
1039 addr
>= agp
->aperture
.bus_base
+ agp
->aperture
.size
) {
1040 printk("%s: addr out of range\n", __func__
);
1044 pte
= aper
->arena
->ptes
[baddr
>> PAGE_SHIFT
];
1046 printk("%s: pte not valid\n", __func__
);
1049 return (pte
>> 1) << PAGE_SHIFT
;
1052 struct alpha_agp_ops marvel_agp_ops
=
1054 .setup
= marvel_agp_setup
,
1055 .cleanup
= marvel_agp_cleanup
,
1056 .configure
= marvel_agp_configure
,
1057 .bind
= marvel_agp_bind_memory
,
1058 .unbind
= marvel_agp_unbind_memory
,
1059 .translate
= marvel_agp_translate
1063 marvel_agp_info(void)
1065 struct pci_controller
*hose
;
1066 io7_ioport_csrs
*csrs
;
1067 alpha_agp_info
*agp
;
1071 * Find the first IO7 with an AGP card.
1073 * FIXME -- there should be a better way (we want to be able to
1074 * specify and what if the agp card is not video???)
1077 for (io7
= NULL
; (io7
= marvel_next_io7(io7
)) != NULL
; ) {
1078 struct pci_controller
*h
;
1081 if (!io7
->ports
[IO7_AGP_PORT
].enabled
)
1084 h
= io7
->ports
[IO7_AGP_PORT
].hose
;
1085 addr
= (vuip
)build_conf_addr(h
, 0, PCI_DEVFN(5, 0), 0);
1087 if (*addr
!= 0xffffffffu
) {
1093 if (!hose
|| !hose
->sg_pci
)
1096 printk("MARVEL - using hose %d as AGP\n", hose
->index
);
1099 * Get the csrs from the hose.
1101 csrs
= ((struct io7_port
*)hose
->sysdata
)->csrs
;
1104 * Allocate the info structure.
1106 agp
= kmalloc(sizeof(*agp
), GFP_KERNEL
);
1114 agp
->private = NULL
;
1115 agp
->ops
= &marvel_agp_ops
;
1118 * Aperture - not configured until ops.setup().
1120 agp
->aperture
.bus_base
= 0;
1121 agp
->aperture
.size
= 0;
1122 agp
->aperture
.sysdata
= NULL
;
1127 * NOTE: IO7 reports through AGP_STAT that it can support a read queue
1128 * depth of 17 (rq = 0x10). It actually only supports a depth of
1131 agp
->capability
.lw
= csrs
->AGP_STAT
.csr
;
1132 agp
->capability
.bits
.rq
= 0xf;
1137 agp
->mode
.lw
= csrs
->AGP_CMD
.csr
;