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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/alpha/kernel/core_t2.c
2 * linux/arch/alpha/kernel/core_t2.c
4 * Written by Jay A Estabrook (jestabro@amt.tay1.dec.com).
7 * based on CIA code by David A Rusling (david.rusling@reo.mts.dec.com)
9 * Code common to all T2 core logic chips.
12 #define __EXTERN_INLINE
14 #include <asm/core_t2.h>
15 #undef __EXTERN_INLINE
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/init.h>
22 #include <asm/ptrace.h>
23 #include <asm/delay.h>
29 /* For dumping initial DMA window settings. */
30 #define DEBUG_PRINT_INITIAL_SETTINGS 0
32 /* For dumping final DMA window settings. */
33 #define DEBUG_PRINT_FINAL_SETTINGS 0
36 * By default, we direct-map starting at 2GB, in order to allow the
37 * maximum size direct-map window (2GB) to match the maximum amount of
38 * memory (2GB) that can be present on SABLEs. But that limits the
39 * floppy to DMA only via the scatter/gather window set up for 8MB
40 * ISA DMA, since the maximum ISA DMA address is 2GB-1.
42 * For now, this seems a reasonable trade-off: even though most SABLEs
43 * have less than 1GB of memory, floppy usage/performance will not
44 * really be affected by forcing it to go via scatter/gather...
46 #define T2_DIRECTMAP_2G 1
49 # define T2_DIRECTMAP_START 0x80000000UL
50 # define T2_DIRECTMAP_LENGTH 0x80000000UL
52 # define T2_DIRECTMAP_START 0x40000000UL
53 # define T2_DIRECTMAP_LENGTH 0x40000000UL
56 /* The ISA scatter/gather window settings. */
57 #define T2_ISA_SG_START 0x00800000UL
58 #define T2_ISA_SG_LENGTH 0x00800000UL
61 * NOTE: Herein lie back-to-back mb instructions. They are magic.
62 * One plausible explanation is that the i/o controller does not properly
63 * handle the system transaction. Another involves timing. Ho hum.
67 * BIOS32-style PCI interface:
70 #define DEBUG_CONFIG 0
73 # define DBG(args) printk args
78 static volatile unsigned int t2_mcheck_any_expected
;
79 static volatile unsigned int t2_mcheck_last_taken
;
81 /* Place to save the DMA Window registers as set up by SRM
82 for restoration during shutdown. */
95 } t2_saved_config
__attribute((common
));
98 * Given a bus, device, and function number, compute resulting
99 * configuration space address and setup the T2_HAXR2 register
100 * accordingly. It is therefore not safe to have concurrent
101 * invocations to configuration space access routines, but there
102 * really shouldn't be any need for this.
106 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
107 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
108 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
109 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
110 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
112 * 31:11 Device select bit.
113 * 10:8 Function number
114 * 7:2 Register number
118 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
119 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
120 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
121 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
122 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
125 * 23:16 bus number (8 bits = 128 possible buses)
126 * 15:11 Device number (5 bits)
127 * 10:8 function number
128 * 7:2 register number
131 * The function number selects which function of a multi-function device
132 * (e.g., SCSI and Ethernet).
134 * The register selects a DWORD (32 bit) register offset. Hence it
135 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
140 mk_conf_addr(struct pci_bus
*pbus
, unsigned int device_fn
, int where
,
141 unsigned long *pci_addr
, unsigned char *type1
)
144 u8 bus
= pbus
->number
;
146 DBG(("mk_conf_addr(bus=%d, dfn=0x%x, where=0x%x,"
147 " addr=0x%lx, type1=0x%x)\n",
148 bus
, device_fn
, where
, pci_addr
, type1
));
151 int device
= device_fn
>> 3;
153 /* Type 0 configuration cycle. */
156 DBG(("mk_conf_addr: device (%d)>20, returning -1\n",
162 addr
= (0x0800L
<< device
) | ((device_fn
& 7) << 8) | (where
);
164 /* Type 1 configuration cycle. */
166 addr
= (bus
<< 16) | (device_fn
<< 8) | (where
);
169 DBG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr
));
174 * NOTE: both conf_read() and conf_write() may set HAE_3 when needing
175 * to do type1 access. This is protected by the use of spinlock IRQ
176 * primitives in the wrapper functions pci_{read,write}_config_*()
177 * defined in drivers/pci/pci.c.
180 conf_read(unsigned long addr
, unsigned char type1
)
182 unsigned int value
, cpu
, taken
;
183 unsigned long t2_cfg
= 0;
185 cpu
= smp_processor_id();
187 DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr
, type1
));
189 /* If Type1 access, must set T2 CFG. */
191 t2_cfg
= *(vulp
)T2_HAE_3
& ~0xc0000000UL
;
192 *(vulp
)T2_HAE_3
= 0x40000000UL
| t2_cfg
;
198 mcheck_expected(cpu
) = 1;
199 mcheck_taken(cpu
) = 0;
200 t2_mcheck_any_expected
|= (1 << cpu
);
203 /* Access configuration space. */
208 /* Wait for possible mcheck. Also, this lets other CPUs clear
209 their mchecks as well, as they can reliably tell when
210 another CPU is in the midst of handling a real mcheck via
211 the "taken" function. */
214 if ((taken
= mcheck_taken(cpu
))) {
215 mcheck_taken(cpu
) = 0;
216 t2_mcheck_last_taken
|= (1 << cpu
);
220 mcheck_expected(cpu
) = 0;
221 t2_mcheck_any_expected
= 0;
224 /* If Type1 access, must reset T2 CFG so normal IO space ops work. */
226 *(vulp
)T2_HAE_3
= t2_cfg
;
234 conf_write(unsigned long addr
, unsigned int value
, unsigned char type1
)
236 unsigned int cpu
, taken
;
237 unsigned long t2_cfg
= 0;
239 cpu
= smp_processor_id();
241 /* If Type1 access, must set T2 CFG. */
243 t2_cfg
= *(vulp
)T2_HAE_3
& ~0xc0000000UL
;
244 *(vulp
)T2_HAE_3
= t2_cfg
| 0x40000000UL
;
250 mcheck_expected(cpu
) = 1;
251 mcheck_taken(cpu
) = 0;
252 t2_mcheck_any_expected
|= (1 << cpu
);
255 /* Access configuration space. */
260 /* Wait for possible mcheck. Also, this lets other CPUs clear
261 their mchecks as well, as they can reliably tell when
262 this CPU is in the midst of handling a real mcheck via
263 the "taken" function. */
266 if ((taken
= mcheck_taken(cpu
))) {
267 mcheck_taken(cpu
) = 0;
268 t2_mcheck_last_taken
|= (1 << cpu
);
271 mcheck_expected(cpu
) = 0;
272 t2_mcheck_any_expected
= 0;
275 /* If Type1 access, must reset T2 CFG so normal IO space ops work. */
277 *(vulp
)T2_HAE_3
= t2_cfg
;
283 t2_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
284 int size
, u32
*value
)
286 unsigned long addr
, pci_addr
;
291 if (mk_conf_addr(bus
, devfn
, where
, &pci_addr
, &type1
))
292 return PCIBIOS_DEVICE_NOT_FOUND
;
294 mask
= (size
- 1) * 8;
295 shift
= (where
& 3) * 8;
296 addr
= (pci_addr
<< 5) + mask
+ T2_CONF
;
297 *value
= conf_read(addr
, type1
) >> (shift
);
298 return PCIBIOS_SUCCESSFUL
;
302 t2_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
,
305 unsigned long addr
, pci_addr
;
309 if (mk_conf_addr(bus
, devfn
, where
, &pci_addr
, &type1
))
310 return PCIBIOS_DEVICE_NOT_FOUND
;
312 mask
= (size
- 1) * 8;
313 addr
= (pci_addr
<< 5) + mask
+ T2_CONF
;
314 conf_write(addr
, value
<< ((where
& 3) * 8), type1
);
315 return PCIBIOS_SUCCESSFUL
;
318 struct pci_ops t2_pci_ops
=
320 .read
= t2_read_config
,
321 .write
= t2_write_config
,
325 t2_direct_map_window1(unsigned long base
, unsigned long length
)
329 __direct_map_base
= base
;
330 __direct_map_size
= length
;
332 temp
= (base
& 0xfff00000UL
) | ((base
+ length
- 1) >> 20);
333 *(vulp
)T2_WBASE1
= temp
| 0x80000UL
; /* OR in ENABLE bit */
334 temp
= (length
- 1) & 0xfff00000UL
;
335 *(vulp
)T2_WMASK1
= temp
;
336 *(vulp
)T2_TBASE1
= 0;
338 #if DEBUG_PRINT_FINAL_SETTINGS
339 printk("%s: setting WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n",
340 __func__
, *(vulp
)T2_WBASE1
, *(vulp
)T2_WMASK1
, *(vulp
)T2_TBASE1
);
345 t2_sg_map_window2(struct pci_controller
*hose
,
347 unsigned long length
)
351 /* Note we can only do 1 SG window, as the other is for direct, so
352 do an ISA SG area, especially for the floppy. */
353 hose
->sg_isa
= iommu_arena_new(hose
, base
, length
, 0);
356 temp
= (base
& 0xfff00000UL
) | ((base
+ length
- 1) >> 20);
357 *(vulp
)T2_WBASE2
= temp
| 0xc0000UL
; /* OR in ENABLE/SG bits */
358 temp
= (length
- 1) & 0xfff00000UL
;
359 *(vulp
)T2_WMASK2
= temp
;
360 *(vulp
)T2_TBASE2
= virt_to_phys(hose
->sg_isa
->ptes
) >> 1;
363 t2_pci_tbi(hose
, 0, -1); /* flush TLB all */
365 #if DEBUG_PRINT_FINAL_SETTINGS
366 printk("%s: setting WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n",
367 __func__
, *(vulp
)T2_WBASE2
, *(vulp
)T2_WMASK2
, *(vulp
)T2_TBASE2
);
372 t2_save_configuration(void)
374 #if DEBUG_PRINT_INITIAL_SETTINGS
375 printk("%s: HAE_1 was 0x%lx\n", __func__
, srm_hae
); /* HW is 0 */
376 printk("%s: HAE_2 was 0x%lx\n", __func__
, *(vulp
)T2_HAE_2
);
377 printk("%s: HAE_3 was 0x%lx\n", __func__
, *(vulp
)T2_HAE_3
);
378 printk("%s: HAE_4 was 0x%lx\n", __func__
, *(vulp
)T2_HAE_4
);
379 printk("%s: HBASE was 0x%lx\n", __func__
, *(vulp
)T2_HBASE
);
381 printk("%s: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n", __func__
,
382 *(vulp
)T2_WBASE1
, *(vulp
)T2_WMASK1
, *(vulp
)T2_TBASE1
);
383 printk("%s: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n", __func__
,
384 *(vulp
)T2_WBASE2
, *(vulp
)T2_WMASK2
, *(vulp
)T2_TBASE2
);
388 * Save the DMA Window registers.
390 t2_saved_config
.window
[0].wbase
= *(vulp
)T2_WBASE1
;
391 t2_saved_config
.window
[0].wmask
= *(vulp
)T2_WMASK1
;
392 t2_saved_config
.window
[0].tbase
= *(vulp
)T2_TBASE1
;
393 t2_saved_config
.window
[1].wbase
= *(vulp
)T2_WBASE2
;
394 t2_saved_config
.window
[1].wmask
= *(vulp
)T2_WMASK2
;
395 t2_saved_config
.window
[1].tbase
= *(vulp
)T2_TBASE2
;
397 t2_saved_config
.hae_1
= srm_hae
; /* HW is already set to 0 */
398 t2_saved_config
.hae_2
= *(vulp
)T2_HAE_2
;
399 t2_saved_config
.hae_3
= *(vulp
)T2_HAE_3
;
400 t2_saved_config
.hae_4
= *(vulp
)T2_HAE_4
;
401 t2_saved_config
.hbase
= *(vulp
)T2_HBASE
;
407 struct pci_controller
*hose
;
408 struct resource
*hae_mem
;
412 for (i
= 0; i
< NR_CPUS
; i
++) {
413 mcheck_expected(i
) = 0;
416 t2_mcheck_any_expected
= 0;
417 t2_mcheck_last_taken
= 0;
419 /* Enable scatter/gather TLB use. */
420 temp
= *(vulp
)T2_IOCSR
;
421 if (!(temp
& (0x1UL
<< 26))) {
422 printk("t2_init_arch: enabling SG TLB, IOCSR was 0x%lx\n",
424 *(vulp
)T2_IOCSR
= temp
| (0x1UL
<< 26);
426 *(vulp
)T2_IOCSR
; /* read it back to make sure */
429 t2_save_configuration();
432 * Create our single hose.
434 pci_isa_hose
= hose
= alloc_pci_controller();
435 hose
->io_space
= &ioport_resource
;
436 hae_mem
= alloc_resource();
438 hae_mem
->end
= T2_MEM_R1_MASK
;
439 hae_mem
->name
= pci_hae0_name
;
440 if (request_resource(&iomem_resource
, hae_mem
) < 0)
441 printk(KERN_ERR
"Failed to request HAE_MEM\n");
442 hose
->mem_space
= hae_mem
;
445 hose
->sparse_mem_base
= T2_SPARSE_MEM
- IDENT_ADDR
;
446 hose
->dense_mem_base
= T2_DENSE_MEM
- IDENT_ADDR
;
447 hose
->sparse_io_base
= T2_IO
- IDENT_ADDR
;
448 hose
->dense_io_base
= 0;
451 * Set up the PCI->physical memory translation windows.
453 * Window 1 is direct mapped.
454 * Window 2 is scatter/gather (for ISA).
457 t2_direct_map_window1(T2_DIRECTMAP_START
, T2_DIRECTMAP_LENGTH
);
459 /* Always make an ISA DMA window. */
460 t2_sg_map_window2(hose
, T2_ISA_SG_START
, T2_ISA_SG_LENGTH
);
462 *(vulp
)T2_HBASE
= 0x0; /* Disable HOLES. */
465 *(vulp
)T2_HAE_1
= 0; mb(); /* Sparse MEM HAE */
466 *(vulp
)T2_HAE_2
= 0; mb(); /* Sparse I/O HAE */
467 *(vulp
)T2_HAE_3
= 0; mb(); /* Config Space HAE */
470 * We also now zero out HAE_4, the dense memory HAE, so that
471 * we need not account for its "offset" when accessing dense
472 * memory resources which we allocated in our normal way. This
473 * HAE would need to stay untouched were we to keep the SRM
476 * Thus we can now run standard X servers on SABLE/LYNX. :-)
478 *(vulp
)T2_HAE_4
= 0; mb();
482 t2_kill_arch(int mode
)
485 * Restore the DMA Window registers.
487 *(vulp
)T2_WBASE1
= t2_saved_config
.window
[0].wbase
;
488 *(vulp
)T2_WMASK1
= t2_saved_config
.window
[0].wmask
;
489 *(vulp
)T2_TBASE1
= t2_saved_config
.window
[0].tbase
;
490 *(vulp
)T2_WBASE2
= t2_saved_config
.window
[1].wbase
;
491 *(vulp
)T2_WMASK2
= t2_saved_config
.window
[1].wmask
;
492 *(vulp
)T2_TBASE2
= t2_saved_config
.window
[1].tbase
;
495 *(vulp
)T2_HAE_1
= srm_hae
;
496 *(vulp
)T2_HAE_2
= t2_saved_config
.hae_2
;
497 *(vulp
)T2_HAE_3
= t2_saved_config
.hae_3
;
498 *(vulp
)T2_HAE_4
= t2_saved_config
.hae_4
;
499 *(vulp
)T2_HBASE
= t2_saved_config
.hbase
;
501 *(vulp
)T2_HBASE
; /* READ it back to ensure WRITE occurred. */
505 t2_pci_tbi(struct pci_controller
*hose
, dma_addr_t start
, dma_addr_t end
)
507 unsigned long t2_iocsr
;
509 t2_iocsr
= *(vulp
)T2_IOCSR
;
511 /* set the TLB Clear bit */
512 *(vulp
)T2_IOCSR
= t2_iocsr
| (0x1UL
<< 28);
514 *(vulp
)T2_IOCSR
; /* read it back to make sure */
516 /* clear the TLB Clear bit */
517 *(vulp
)T2_IOCSR
= t2_iocsr
& ~(0x1UL
<< 28);
519 *(vulp
)T2_IOCSR
; /* read it back to make sure */
522 #define SIC_SEIC (1UL << 33) /* System Event Clear */
525 t2_clear_errors(int cpu
)
527 struct sable_cpu_csr
*cpu_regs
;
529 cpu_regs
= (struct sable_cpu_csr
*)T2_CPUn_BASE(cpu
);
531 cpu_regs
->sic
&= ~SIC_SEIC
;
533 /* Clear CPU errors. */
534 cpu_regs
->bcce
|= cpu_regs
->bcce
;
535 cpu_regs
->cbe
|= cpu_regs
->cbe
;
536 cpu_regs
->bcue
|= cpu_regs
->bcue
;
537 cpu_regs
->dter
|= cpu_regs
->dter
;
539 *(vulp
)T2_CERR1
|= *(vulp
)T2_CERR1
;
540 *(vulp
)T2_PERR1
|= *(vulp
)T2_PERR1
;
547 * SABLE seems to have a "broadcast" style machine check, in that all
548 * CPUs receive it. And, the issuing CPU, in the case of PCI Config
549 * space read/write faults, will also receive a second mcheck, upon
550 * lowering IPL during completion processing in pci_read_config_byte()
553 * Hence all the taken/expected/any_expected/last_taken stuff...
556 t2_machine_check(unsigned long vector
, unsigned long la_ptr
)
558 int cpu
= smp_processor_id();
559 #ifdef CONFIG_VERBOSE_MCHECK
560 struct el_common
*mchk_header
= (struct el_common
*)la_ptr
;
563 /* Clear the error before any reporting. */
567 t2_clear_errors(cpu
);
569 /* This should not actually be done until the logout frame is
570 examined, but, since we don't do that, go on and do this... */
574 /* Now, do testing for the anomalous conditions. */
575 if (!mcheck_expected(cpu
) && t2_mcheck_any_expected
) {
577 * FUNKY: Received mcheck on a CPU and not
578 * expecting it, but another CPU is expecting one.
580 * Just dismiss it for now on this CPU...
582 #ifdef CONFIG_VERBOSE_MCHECK
583 if (alpha_verbose_mcheck
> 1) {
584 printk("t2_machine_check(cpu%d): any_expected 0x%x -"
585 " (assumed) spurious -"
586 " code 0x%x\n", cpu
, t2_mcheck_any_expected
,
587 (unsigned int)mchk_header
->code
);
593 if (!mcheck_expected(cpu
) && !t2_mcheck_any_expected
) {
594 if (t2_mcheck_last_taken
& (1 << cpu
)) {
595 #ifdef CONFIG_VERBOSE_MCHECK
596 if (alpha_verbose_mcheck
> 1) {
597 printk("t2_machine_check(cpu%d): last_taken 0x%x - "
598 "unexpected mcheck - code 0x%x\n",
599 cpu
, t2_mcheck_last_taken
,
600 (unsigned int)mchk_header
->code
);
603 t2_mcheck_last_taken
= 0;
607 t2_mcheck_last_taken
= 0;
612 #ifdef CONFIG_VERBOSE_MCHECK
613 if (alpha_verbose_mcheck
> 1) {
614 printk("%s t2_mcheck(cpu%d): last_taken 0x%x - "
615 "any_expected 0x%x - code 0x%x\n",
616 (mcheck_expected(cpu
) ? "EX" : "UN"), cpu
,
617 t2_mcheck_last_taken
, t2_mcheck_any_expected
,
618 (unsigned int)mchk_header
->code
);
622 process_mcheck_info(vector
, la_ptr
, "T2", mcheck_expected(cpu
));