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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/alpha/kernel/irq_i8259.c
2 * linux/arch/alpha/kernel/irq_i8259.c
4 * This is the 'legacy' 8259A Programmable Interrupt Controller,
5 * present in the majority of PC/AT boxes.
7 * Started hacking from linux-2.3.30pre6/arch/i386/kernel/i8259.c.
10 #include <linux/init.h>
11 #include <linux/cache.h>
12 #include <linux/sched.h>
13 #include <linux/irq.h>
14 #include <linux/interrupt.h>
22 /* Note mask bit is true for DISABLED irqs. */
23 static unsigned int cached_irq_mask
= 0xffff;
24 static DEFINE_SPINLOCK(i8259_irq_lock
);
27 i8259_update_irq_hw(unsigned int irq
, unsigned long mask
)
30 if (irq
& 8) mask
>>= 8;
31 if (irq
& 8) port
= 0xA1;
36 i8259a_enable_irq(struct irq_data
*d
)
38 spin_lock(&i8259_irq_lock
);
39 i8259_update_irq_hw(d
->irq
, cached_irq_mask
&= ~(1 << d
->irq
));
40 spin_unlock(&i8259_irq_lock
);
44 __i8259a_disable_irq(unsigned int irq
)
46 i8259_update_irq_hw(irq
, cached_irq_mask
|= 1 << irq
);
50 i8259a_disable_irq(struct irq_data
*d
)
52 spin_lock(&i8259_irq_lock
);
53 __i8259a_disable_irq(d
->irq
);
54 spin_unlock(&i8259_irq_lock
);
58 i8259a_mask_and_ack_irq(struct irq_data
*d
)
60 unsigned int irq
= d
->irq
;
62 spin_lock(&i8259_irq_lock
);
63 __i8259a_disable_irq(irq
);
65 /* Ack the interrupt making it the lowest priority. */
67 outb(0xE0 | (irq
- 8), 0xa0); /* ack the slave */
70 outb(0xE0 | irq
, 0x20); /* ack the master */
71 spin_unlock(&i8259_irq_lock
);
74 struct irq_chip i8259a_irq_type
= {
76 .irq_unmask
= i8259a_enable_irq
,
77 .irq_mask
= i8259a_disable_irq
,
78 .irq_mask_ack
= i8259a_mask_and_ack_irq
,
82 init_i8259a_irqs(void)
84 static struct irqaction cascade
= {
91 outb(0xff, 0x21); /* mask all of 8259A-1 */
92 outb(0xff, 0xA1); /* mask all of 8259A-2 */
94 for (i
= 0; i
< 16; i
++) {
95 set_irq_chip_and_handler(i
, &i8259a_irq_type
, handle_level_irq
);
98 setup_irq(2, &cascade
);
102 #if defined(CONFIG_ALPHA_GENERIC)
103 # define IACK_SC alpha_mv.iack_sc
104 #elif defined(CONFIG_ALPHA_APECS)
105 # define IACK_SC APECS_IACK_SC
106 #elif defined(CONFIG_ALPHA_LCA)
107 # define IACK_SC LCA_IACK_SC
108 #elif defined(CONFIG_ALPHA_CIA)
109 # define IACK_SC CIA_IACK_SC
110 #elif defined(CONFIG_ALPHA_PYXIS)
111 # define IACK_SC PYXIS_IACK_SC
112 #elif defined(CONFIG_ALPHA_TITAN)
113 # define IACK_SC TITAN_IACK_SC
114 #elif defined(CONFIG_ALPHA_TSUNAMI)
115 # define IACK_SC TSUNAMI_IACK_SC
116 #elif defined(CONFIG_ALPHA_IRONGATE)
117 # define IACK_SC IRONGATE_IACK_SC
119 /* Note that CONFIG_ALPHA_POLARIS is intentionally left out here, since
120 sys_rx164 wants to use isa_no_iack_sc_device_interrupt for some reason. */
124 isa_device_interrupt(unsigned long vector
)
127 * Generate a PCI interrupt acknowledge cycle. The PIC will
128 * respond with the interrupt vector of the highest priority
129 * interrupt that is pending. The PALcode sets up the
130 * interrupts vectors such that irq level L generates vector L.
132 int j
= *(vuip
) IACK_SC
;
138 #if defined(CONFIG_ALPHA_GENERIC) || !defined(IACK_SC)
140 isa_no_iack_sc_device_interrupt(unsigned long vector
)
145 * It seems to me that the probability of two or more *device*
146 * interrupts occurring at almost exactly the same time is
147 * pretty low. So why pay the price of checking for
148 * additional interrupts here if the common case can be
149 * handled so much easier?
152 * The first read of gives you *all* interrupting lines.
153 * Therefore, read the mask register and and out those lines
154 * not enabled. Note that some documentation has 21 and a1
155 * write only. This is not true.
157 pic
= inb(0x20) | (inb(0xA0) << 8); /* read isr */
158 pic
&= 0xFFFB; /* mask out cascade & hibits */