arch/alpha/kernel/sys_mikasa.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_mikasa.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code supporting the MIKASA (AlphaServer 1000).
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/sched.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/system.h>
  22 #include <asm/dma.h>
  23 #include <asm/irq.h>
  24 #include <asm/mmu_context.h>
  25 #include <asm/io.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/core_apecs.h>
  28 #include <asm/core_cia.h>
  29 #include <asm/tlbflush.h>
  30
  31 #include "proto.h"
  32 #include "irq_impl.h"
  33 #include "pci_impl.h"
  34 #include "machvec_impl.h"
  35
  36
  37 /* Note mask bit is true for ENABLED irqs.  */
  38 static int cached_irq_mask;
  39
  40 static inline void
  41 mikasa_update_irq_hw(int mask)
  42 {
  43         outw(mask, 0x536);
  44 }
  45
  46 static inline void
  47 mikasa_enable_irq(unsigned int irq)
  48 {
  49         mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
  50 }
  51
  52 static void
  53 mikasa_disable_irq(unsigned int irq)
  54 {
  55         mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
  56 }
  57
  58 static unsigned int
  59 mikasa_startup_irq(unsigned int irq)
  60 {
  61         mikasa_enable_irq(irq);
  62         return 0;
  63 }
  64
  65 static void
  66 mikasa_end_irq(unsigned int irq)
  67 {
  68         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  69                 mikasa_enable_irq(irq);
  70 }
  71
  72 static struct hw_interrupt_type mikasa_irq_type = {
  73         .typename       = "MIKASA",
  74         .startup        = mikasa_startup_irq,
  75         .shutdown       = mikasa_disable_irq,
  76         .enable         = mikasa_enable_irq,
  77         .disable        = mikasa_disable_irq,
  78         .ack            = mikasa_disable_irq,
  79         .end            = mikasa_end_irq,
  80 };
  81
  82 static void
  83 mikasa_device_interrupt(unsigned long vector, struct pt_regs *regs)
  84 {
  85         unsigned long pld;
  86         unsigned int i;
  87
  88         /* Read the interrupt summary registers */
  89         pld = (((~inw(0x534) & 0x0000ffffUL) << 16)
  90                | (((unsigned long) inb(0xa0)) << 8)
  91                | inb(0x20));
  92
  93         /*
  94          * Now for every possible bit set, work through them and call
  95          * the appropriate interrupt handler.
  96          */
  97         while (pld) {
  98                 i = ffz(~pld);
  99                 pld &= pld - 1; /* clear least bit set */
 100                 if (i < 16) {
 101                         isa_device_interrupt(vector, regs);
 102                 } else {
 103                         handle_irq(i, regs);
 104                 }
 105         }
 106 }
 107
 108 static void __init
 109 mikasa_init_irq(void)
 110 {
 111         long i;
 112
 113         if (alpha_using_srm)
 114                 alpha_mv.device_interrupt = srm_device_interrupt;
 115
 116         mikasa_update_irq_hw(0);
 117
 118         for (i = 16; i < 32; ++i) {
 119                 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
 120                 irq_desc[i].handler = &mikasa_irq_type;
 121         }
 122
 123         init_i8259a_irqs();
 124         common_init_isa_dma();
 125 }
 126
 127
 128 /*
 129  * PCI Fixup configuration.
 130  *
 131  * Summary @ 0x536:
 132  * Bit      Meaning
 133  * 0        Interrupt Line A from slot 0
 134  * 1        Interrupt Line B from slot 0
 135  * 2        Interrupt Line C from slot 0
 136  * 3        Interrupt Line D from slot 0
 137  * 4        Interrupt Line A from slot 1
 138  * 5        Interrupt line B from slot 1
 139  * 6        Interrupt Line C from slot 1
 140  * 7        Interrupt Line D from slot 1
 141  * 8        Interrupt Line A from slot 2
 142  * 9        Interrupt Line B from slot 2
 143  *10        Interrupt Line C from slot 2
 144  *11        Interrupt Line D from slot 2
 145  *12        NCR 810 SCSI
 146  *13        Power Supply Fail
 147  *14        Temperature Warn
 148  *15        Reserved
 149  *
 150  * The device to slot mapping looks like:
 151  *
 152  * Slot     Device
 153  *  6       NCR SCSI controller
 154  *  7       Intel PCI-EISA bridge chip
 155  * 11       PCI on board slot 0
 156  * 12       PCI on board slot 1
 157  * 13       PCI on board slot 2
 158  *
 159  *
 160  * This two layered interrupt approach means that we allocate IRQ 16 and
 161  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 162  * comes in on.  This makes interrupt processing much easier.
 163  */
 164
 165 static int __init
 166 mikasa_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 167 {
 168         static char irq_tab[8][5] __initdata = {
 169                 /*INT    INTA   INTB   INTC   INTD */
 170                 {16+12, 16+12, 16+12, 16+12, 16+12},    /* IdSel 17,  SCSI */
 171                 {   -1,    -1,    -1,    -1,    -1},    /* IdSel 18,  PCEB */
 172                 {   -1,    -1,    -1,    -1,    -1},    /* IdSel 19,  ???? */
 173                 {   -1,    -1,    -1,    -1,    -1},    /* IdSel 20,  ???? */
 174                 {   -1,    -1,    -1,    -1,    -1},    /* IdSel 21,  ???? */
 175                 { 16+0,  16+0,  16+1,  16+2,  16+3},    /* IdSel 22,  slot 0 */
 176                 { 16+4,  16+4,  16+5,  16+6,  16+7},    /* IdSel 23,  slot 1 */
 177                 { 16+8,  16+8,  16+9, 16+10, 16+11},    /* IdSel 24,  slot 2 */
 178         };
 179         const long min_idsel = 6, max_idsel = 13, irqs_per_slot = 5;
 180         return COMMON_TABLE_LOOKUP;
 181 }
 182
 183
 184 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
 185 static void
 186 mikasa_apecs_machine_check(unsigned long vector, unsigned long la_ptr,
 187                            struct pt_regs * regs)
 188 {
 189 #define MCHK_NO_DEVSEL 0x205U
 190 #define MCHK_NO_TABT 0x204U
 191
 192         struct el_common *mchk_header;
 193         unsigned int code;
 194
 195         mchk_header = (struct el_common *)la_ptr;
 196
 197         /* Clear the error before any reporting.  */
 198         mb();
 199         mb(); /* magic */
 200         draina();
 201         apecs_pci_clr_err();
 202         wrmces(0x7);
 203         mb();
 204
 205         code = mchk_header->code;
 206         process_mcheck_info(vector, la_ptr, regs, "MIKASA APECS",
 207                             (mcheck_expected(0)
 208                              && (code == MCHK_NO_DEVSEL
 209                                  || code == MCHK_NO_TABT)));
 210 }
 211 #endif
 212
 213
 214 /*
 215  * The System Vector
 216  */
 217
 218 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
 219 struct alpha_machine_vector mikasa_mv __initmv = {
 220         .vector_name            = "Mikasa",
 221         DO_EV4_MMU,
 222         DO_DEFAULT_RTC,
 223         DO_APECS_IO,
 224         .machine_check          = mikasa_apecs_machine_check,
 225         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 226         .min_io_address         = DEFAULT_IO_BASE,
 227         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 228
 229         .nr_irqs                = 32,
 230         .device_interrupt       = mikasa_device_interrupt,
 231
 232         .init_arch              = apecs_init_arch,
 233         .init_irq               = mikasa_init_irq,
 234         .init_rtc               = common_init_rtc,
 235         .init_pci               = common_init_pci,
 236         .pci_map_irq            = mikasa_map_irq,
 237         .pci_swizzle            = common_swizzle,
 238 };
 239 ALIAS_MV(mikasa)
 240 #endif
 241
 242 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
 243 struct alpha_machine_vector mikasa_primo_mv __initmv = {
 244         .vector_name            = "Mikasa-Primo",
 245         DO_EV5_MMU,
 246         DO_DEFAULT_RTC,
 247         DO_CIA_IO,
 248         .machine_check          = cia_machine_check,
 249         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 250         .min_io_address         = DEFAULT_IO_BASE,
 251         .min_mem_address        = CIA_DEFAULT_MEM_BASE,
 252
 253         .nr_irqs                = 32,
 254         .device_interrupt       = mikasa_device_interrupt,
 255
 256         .init_arch              = cia_init_arch,
 257         .init_irq               = mikasa_init_irq,
 258         .init_rtc               = common_init_rtc,
 259         .init_pci               = cia_init_pci,
 260         .kill_arch              = cia_kill_arch,
 261         .pci_map_irq            = mikasa_map_irq,
 262         .pci_swizzle            = common_swizzle,
 263 };
 264 ALIAS_MV(mikasa_primo)
 265 #endif