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1 // SPDX-License-Identifier: GPL-2.0
3 * arch/alpha/kernel/traps.c
5 * (C) Copyright 1994 Linus Torvalds
9 * This file initializes the trap entry points
12 #include <linux/jiffies.h>
14 #include <linux/sched/signal.h>
15 #include <linux/sched/debug.h>
16 #include <linux/tty.h>
17 #include <linux/delay.h>
18 #include <linux/extable.h>
19 #include <linux/kallsyms.h>
20 #include <linux/ratelimit.h>
22 #include <asm/gentrap.h>
23 #include <linux/uaccess.h>
24 #include <asm/unaligned.h>
25 #include <asm/sysinfo.h>
26 #include <asm/hwrpb.h>
27 #include <asm/mmu_context.h>
28 #include <asm/special_insns.h>
32 /* Work-around for some SRMs which mishandle opDEC faults. */
39 __asm__
__volatile__ (
40 /* Load the address of... */
42 /* A stub instruction fault handler. Just add 4 to the
48 /* Install the instruction fault handler. */
50 " call_pal %[wrent]\n"
51 /* With that in place, the fault from the round-to-minf fp
52 insn will arrive either at the "lda 4" insn (bad) or one
53 past that (good). This places the correct fixup in %0. */
55 " cvttq/svm $f31,$f31\n"
57 : [fix
] "=r" (opDEC_fix
)
58 : [rti
] "n" (PAL_rti
), [wrent
] "n" (PAL_wrent
)
59 : "$0", "$1", "$16", "$17", "$22", "$23", "$24", "$25");
62 printk("opDEC fixup enabled.\n");
66 dik_show_regs(struct pt_regs
*regs
, unsigned long *r9_15
)
68 printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx %s\n",
69 regs
->pc
, regs
->r26
, regs
->ps
, print_tainted());
70 printk("pc is at %pSR\n", (void *)regs
->pc
);
71 printk("ra is at %pSR\n", (void *)regs
->r26
);
72 printk("v0 = %016lx t0 = %016lx t1 = %016lx\n",
73 regs
->r0
, regs
->r1
, regs
->r2
);
74 printk("t2 = %016lx t3 = %016lx t4 = %016lx\n",
75 regs
->r3
, regs
->r4
, regs
->r5
);
76 printk("t5 = %016lx t6 = %016lx t7 = %016lx\n",
77 regs
->r6
, regs
->r7
, regs
->r8
);
80 printk("s0 = %016lx s1 = %016lx s2 = %016lx\n",
81 r9_15
[9], r9_15
[10], r9_15
[11]);
82 printk("s3 = %016lx s4 = %016lx s5 = %016lx\n",
83 r9_15
[12], r9_15
[13], r9_15
[14]);
84 printk("s6 = %016lx\n", r9_15
[15]);
87 printk("a0 = %016lx a1 = %016lx a2 = %016lx\n",
88 regs
->r16
, regs
->r17
, regs
->r18
);
89 printk("a3 = %016lx a4 = %016lx a5 = %016lx\n",
90 regs
->r19
, regs
->r20
, regs
->r21
);
91 printk("t8 = %016lx t9 = %016lx t10= %016lx\n",
92 regs
->r22
, regs
->r23
, regs
->r24
);
93 printk("t11= %016lx pv = %016lx at = %016lx\n",
94 regs
->r25
, regs
->r27
, regs
->r28
);
95 printk("gp = %016lx sp = %p\n", regs
->gp
, regs
+1);
102 static char * ireg_name
[] = {"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
103 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6",
104 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
105 "t10", "t11", "ra", "pv", "at", "gp", "sp", "zero"};
109 dik_show_code(unsigned int *pc
)
114 for (i
= -6; i
< 2; i
++) {
116 if (__get_user(insn
, (unsigned int __user
*)pc
+ i
))
118 printk("%c%08x%c", i
? ' ' : '<', insn
, i
? ' ' : '>');
124 dik_show_trace(unsigned long *sp
)
128 while (0x1ff8 & (unsigned long) sp
) {
129 extern char _stext
[], _etext
[];
130 unsigned long tmp
= *sp
;
132 if (tmp
< (unsigned long) &_stext
)
134 if (tmp
>= (unsigned long) &_etext
)
136 printk("[<%lx>] %pSR\n", tmp
, (void *)tmp
);
145 static int kstack_depth_to_print
= 24;
147 void show_stack(struct task_struct
*task
, unsigned long *sp
)
149 unsigned long *stack
;
153 * debugging aid: "show_stack(NULL);" prints the
154 * back trace for this cpu.
157 sp
=(unsigned long*)&sp
;
160 for(i
=0; i
< kstack_depth_to_print
; i
++) {
161 if (((long) stack
& (THREAD_SIZE
-1)) == 0)
163 if (i
&& ((i
% 4) == 0))
165 printk("%016lx ", *stack
++);
172 die_if_kernel(char * str
, struct pt_regs
*regs
, long err
, unsigned long *r9_15
)
177 printk("CPU %d ", hard_smp_processor_id());
179 printk("%s(%d): %s %ld\n", current
->comm
, task_pid_nr(current
), str
, err
);
180 dik_show_regs(regs
, r9_15
);
181 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
182 dik_show_trace((unsigned long *)(regs
+1));
183 dik_show_code((unsigned int *)regs
->pc
);
185 if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL
)) {
186 printk("die_if_kernel recursion detected.\n");
193 #ifndef CONFIG_MATHEMU
194 static long dummy_emul(void) { return 0; }
195 long (*alpha_fp_emul_imprecise
)(struct pt_regs
*regs
, unsigned long writemask
)
196 = (void *)dummy_emul
;
197 EXPORT_SYMBOL_GPL(alpha_fp_emul_imprecise
);
198 long (*alpha_fp_emul
) (unsigned long pc
)
199 = (void *)dummy_emul
;
200 EXPORT_SYMBOL_GPL(alpha_fp_emul
);
202 long alpha_fp_emul_imprecise(struct pt_regs
*regs
, unsigned long writemask
);
203 long alpha_fp_emul (unsigned long pc
);
207 do_entArith(unsigned long summary
, unsigned long write_mask
,
208 struct pt_regs
*regs
)
210 long si_code
= FPE_FLTINV
;
214 /* Software-completion summary bit is set, so try to
215 emulate the instruction. If the processor supports
216 precise exceptions, we don't have to search. */
217 if (!amask(AMASK_PRECISE_TRAP
))
218 si_code
= alpha_fp_emul(regs
->pc
- 4);
220 si_code
= alpha_fp_emul_imprecise(regs
, write_mask
);
224 die_if_kernel("Arithmetic fault", regs
, 0, NULL
);
226 info
.si_signo
= SIGFPE
;
228 info
.si_code
= si_code
;
229 info
.si_addr
= (void __user
*) regs
->pc
;
230 send_sig_info(SIGFPE
, &info
, current
);
234 do_entIF(unsigned long type
, struct pt_regs
*regs
)
239 if ((regs
->ps
& ~IPL_MAX
) == 0) {
241 const unsigned int *data
242 = (const unsigned int *) regs
->pc
;
243 printk("Kernel bug at %s:%d\n",
244 (const char *)(data
[1] | (long)data
[2] << 32),
247 #ifdef CONFIG_ALPHA_WTINT
249 /* If CALL_PAL WTINT is totally unsupported by the
250 PALcode, e.g. MILO, "emulate" it by overwriting
253 = (unsigned int *) regs
->pc
- 1;
254 if (*pinsn
== PAL_wtint
) {
255 *pinsn
= 0x47e01400; /* mov 0,$0 */
261 #endif /* ALPHA_WTINT */
262 die_if_kernel((type
== 1 ? "Kernel Bug" : "Instruction fault"),
267 case 0: /* breakpoint */
268 info
.si_signo
= SIGTRAP
;
270 info
.si_code
= TRAP_BRKPT
;
272 info
.si_addr
= (void __user
*) regs
->pc
;
274 if (ptrace_cancel_bpt(current
)) {
275 regs
->pc
-= 4; /* make pc point to former bpt */
278 send_sig_info(SIGTRAP
, &info
, current
);
281 case 1: /* bugcheck */
282 info
.si_signo
= SIGTRAP
;
284 info
.si_code
= TRAP_FIXME
;
285 info
.si_addr
= (void __user
*) regs
->pc
;
287 send_sig_info(SIGTRAP
, &info
, current
);
290 case 2: /* gentrap */
291 info
.si_addr
= (void __user
*) regs
->pc
;
292 info
.si_trapno
= regs
->r16
;
293 switch ((long) regs
->r16
) {
350 info
.si_signo
= signo
;
353 info
.si_addr
= (void __user
*) regs
->pc
;
354 send_sig_info(signo
, &info
, current
);
358 if (implver() == IMPLVER_EV4
) {
361 /* The some versions of SRM do not handle
362 the opDEC properly - they return the PC of the
363 opDEC fault, not the instruction after as the
364 Alpha architecture requires. Here we fix it up.
365 We do this by intentionally causing an opDEC
366 fault during the boot sequence and testing if
367 we get the correct PC. If not, we set a flag
368 to correct it every time through. */
369 regs
->pc
+= opDEC_fix
;
371 /* EV4 does not implement anything except normal
372 rounding. Everything else will come here as
373 an illegal instruction. Emulate them. */
374 si_code
= alpha_fp_emul(regs
->pc
- 4);
378 info
.si_signo
= SIGFPE
;
380 info
.si_code
= si_code
;
381 info
.si_addr
= (void __user
*) regs
->pc
;
382 send_sig_info(SIGFPE
, &info
, current
);
388 case 3: /* FEN fault */
389 /* Irritating users can call PAL_clrfen to disable the
390 FPU for the process. The kernel will then trap in
391 do_switch_stack and undo_switch_stack when we try
392 to save and restore the FP registers.
394 Given that GCC by default generates code that uses the
395 FP registers, PAL_clrfen is not useful except for DoS
396 attacks. So turn the bleeding FPU back on and be done
398 current_thread_info()->pcb
.flags
|= 1;
399 __reload_thread(¤t_thread_info()->pcb
);
403 default: /* unexpected instruction-fault type */
407 info
.si_signo
= SIGILL
;
409 info
.si_code
= ILL_ILLOPC
;
410 info
.si_addr
= (void __user
*) regs
->pc
;
411 send_sig_info(SIGILL
, &info
, current
);
414 /* There is an ifdef in the PALcode in MILO that enables a
415 "kernel debugging entry point" as an unprivileged call_pal.
417 We don't want to have anything to do with it, but unfortunately
418 several versions of MILO included in distributions have it enabled,
419 and if we don't put something on the entry point we'll oops. */
422 do_entDbg(struct pt_regs
*regs
)
426 die_if_kernel("Instruction fault", regs
, 0, NULL
);
428 info
.si_signo
= SIGILL
;
430 info
.si_code
= ILL_ILLOPC
;
431 info
.si_addr
= (void __user
*) regs
->pc
;
432 force_sig_info(SIGILL
, &info
, current
);
437 * entUna has a different register layout to be reasonably simple. It
438 * needs access to all the integer registers (the kernel doesn't use
439 * fp-regs), and it needs to have them in order for simpler access.
441 * Due to the non-standard register layout (and because we don't want
442 * to handle floating-point regs), user-mode unaligned accesses are
443 * handled separately by do_entUnaUser below.
445 * Oh, btw, we don't handle the "gp" register correctly, but if we fault
446 * on a gp-register unaligned load/store, something is _very_ wrong
447 * in the kernel anyway..
450 unsigned long regs
[32];
451 unsigned long ps
, pc
, gp
, a0
, a1
, a2
;
454 struct unaligned_stat
{
455 unsigned long count
, va
, pc
;
459 /* Macro for exception fixup code to access integer registers. */
460 #define una_reg(r) (_regs[(r) >= 16 && (r) <= 18 ? (r)+19 : (r)])
464 do_entUna(void * va
, unsigned long opcode
, unsigned long reg
,
465 struct allregs
*regs
)
467 long error
, tmp1
, tmp2
, tmp3
, tmp4
;
468 unsigned long pc
= regs
->pc
- 4;
469 unsigned long *_regs
= regs
->regs
;
470 const struct exception_table_entry
*fixup
;
472 unaligned
[0].count
++;
473 unaligned
[0].va
= (unsigned long) va
;
474 unaligned
[0].pc
= pc
;
476 /* We don't want to use the generic get/put unaligned macros as
477 we want to trap exceptions. Only if we actually get an
478 exception will we decide whether we should have caught it. */
481 case 0x0c: /* ldwu */
482 __asm__
__volatile__(
483 "1: ldq_u %1,0(%3)\n"
484 "2: ldq_u %2,1(%3)\n"
490 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
)
494 una_reg(reg
) = tmp1
|tmp2
;
498 __asm__
__volatile__(
499 "1: ldq_u %1,0(%3)\n"
500 "2: ldq_u %2,3(%3)\n"
506 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
)
510 una_reg(reg
) = (int)(tmp1
|tmp2
);
514 __asm__
__volatile__(
515 "1: ldq_u %1,0(%3)\n"
516 "2: ldq_u %2,7(%3)\n"
522 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
)
526 una_reg(reg
) = tmp1
|tmp2
;
529 /* Note that the store sequences do not indicate that they change
530 memory because it _should_ be affecting nothing in this context.
531 (Otherwise we have other, much larger, problems.) */
533 __asm__
__volatile__(
534 "1: ldq_u %2,1(%5)\n"
535 "2: ldq_u %1,0(%5)\n"
542 "3: stq_u %2,1(%5)\n"
543 "4: stq_u %1,0(%5)\n"
549 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
),
550 "=&r"(tmp3
), "=&r"(tmp4
)
551 : "r"(va
), "r"(una_reg(reg
)), "0"(0));
557 __asm__
__volatile__(
558 "1: ldq_u %2,3(%5)\n"
559 "2: ldq_u %1,0(%5)\n"
566 "3: stq_u %2,3(%5)\n"
567 "4: stq_u %1,0(%5)\n"
573 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
),
574 "=&r"(tmp3
), "=&r"(tmp4
)
575 : "r"(va
), "r"(una_reg(reg
)), "0"(0));
581 __asm__
__volatile__(
582 "1: ldq_u %2,7(%5)\n"
583 "2: ldq_u %1,0(%5)\n"
590 "3: stq_u %2,7(%5)\n"
591 "4: stq_u %1,0(%5)\n"
597 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
),
598 "=&r"(tmp3
), "=&r"(tmp4
)
599 : "r"(va
), "r"(una_reg(reg
)), "0"(0));
605 printk("Bad unaligned kernel access at %016lx: %p %lx %lu\n",
606 pc
, va
, opcode
, reg
);
610 /* Ok, we caught the exception, but we don't want it. Is there
611 someone to pass it along to? */
612 if ((fixup
= search_exception_tables(pc
)) != 0) {
614 newpc
= fixup_exception(una_reg
, fixup
, pc
);
616 printk("Forwarding unaligned exception at %lx (%lx)\n",
624 * Yikes! No one to forward the exception to.
625 * Since the registers are in a weird format, dump them ourselves.
628 printk("%s(%d): unhandled unaligned exception\n",
629 current
->comm
, task_pid_nr(current
));
631 printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx\n",
632 pc
, una_reg(26), regs
->ps
);
633 printk("r0 = %016lx r1 = %016lx r2 = %016lx\n",
634 una_reg(0), una_reg(1), una_reg(2));
635 printk("r3 = %016lx r4 = %016lx r5 = %016lx\n",
636 una_reg(3), una_reg(4), una_reg(5));
637 printk("r6 = %016lx r7 = %016lx r8 = %016lx\n",
638 una_reg(6), una_reg(7), una_reg(8));
639 printk("r9 = %016lx r10= %016lx r11= %016lx\n",
640 una_reg(9), una_reg(10), una_reg(11));
641 printk("r12= %016lx r13= %016lx r14= %016lx\n",
642 una_reg(12), una_reg(13), una_reg(14));
643 printk("r15= %016lx\n", una_reg(15));
644 printk("r16= %016lx r17= %016lx r18= %016lx\n",
645 una_reg(16), una_reg(17), una_reg(18));
646 printk("r19= %016lx r20= %016lx r21= %016lx\n",
647 una_reg(19), una_reg(20), una_reg(21));
648 printk("r22= %016lx r23= %016lx r24= %016lx\n",
649 una_reg(22), una_reg(23), una_reg(24));
650 printk("r25= %016lx r27= %016lx r28= %016lx\n",
651 una_reg(25), una_reg(27), una_reg(28));
652 printk("gp = %016lx sp = %p\n", regs
->gp
, regs
+1);
654 dik_show_code((unsigned int *)pc
);
655 dik_show_trace((unsigned long *)(regs
+1));
657 if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL
)) {
658 printk("die_if_kernel recursion detected.\n");
666 * Convert an s-floating point value in memory format to the
667 * corresponding value in register format. The exponent
668 * needs to be remapped to preserve non-finite values
669 * (infinities, not-a-numbers, denormals).
671 static inline unsigned long
672 s_mem_to_reg (unsigned long s_mem
)
674 unsigned long frac
= (s_mem
>> 0) & 0x7fffff;
675 unsigned long sign
= (s_mem
>> 31) & 0x1;
676 unsigned long exp_msb
= (s_mem
>> 30) & 0x1;
677 unsigned long exp_low
= (s_mem
>> 23) & 0x7f;
680 exp
= (exp_msb
<< 10) | exp_low
; /* common case */
682 if (exp_low
== 0x7f) {
686 if (exp_low
== 0x00) {
692 return (sign
<< 63) | (exp
<< 52) | (frac
<< 29);
696 * Convert an s-floating point value in register format to the
697 * corresponding value in memory format.
699 static inline unsigned long
700 s_reg_to_mem (unsigned long s_reg
)
702 return ((s_reg
>> 62) << 30) | ((s_reg
<< 5) >> 34);
706 * Handle user-level unaligned fault. Handling user-level unaligned
707 * faults is *extremely* slow and produces nasty messages. A user
708 * program *should* fix unaligned faults ASAP.
710 * Notice that we have (almost) the regular kernel stack layout here,
711 * so finding the appropriate registers is a little more difficult
712 * than in the kernel case.
714 * Finally, we handle regular integer load/stores only. In
715 * particular, load-linked/store-conditionally and floating point
716 * load/stores are not supported. The former make no sense with
717 * unaligned faults (they are guaranteed to fail) and I don't think
718 * the latter will occur in any decent program.
720 * Sigh. We *do* have to handle some FP operations, because GCC will
721 * uses them as temporary storage for integer memory to memory copies.
722 * However, we need to deal with stt/ldt and sts/lds only.
725 #define OP_INT_MASK ( 1L << 0x28 | 1L << 0x2c /* ldl stl */ \
726 | 1L << 0x29 | 1L << 0x2d /* ldq stq */ \
727 | 1L << 0x0c | 1L << 0x0d /* ldwu stw */ \
728 | 1L << 0x0a | 1L << 0x0e ) /* ldbu stb */
730 #define OP_WRITE_MASK ( 1L << 0x26 | 1L << 0x27 /* sts stt */ \
731 | 1L << 0x2c | 1L << 0x2d /* stl stq */ \
732 | 1L << 0x0d | 1L << 0x0e ) /* stw stb */
734 #define R(x) ((size_t) &((struct pt_regs *)0)->x)
736 static int unauser_reg_offsets
[32] = {
737 R(r0
), R(r1
), R(r2
), R(r3
), R(r4
), R(r5
), R(r6
), R(r7
), R(r8
),
738 /* r9 ... r15 are stored in front of regs. */
739 -56, -48, -40, -32, -24, -16, -8,
740 R(r16
), R(r17
), R(r18
),
741 R(r19
), R(r20
), R(r21
), R(r22
), R(r23
), R(r24
), R(r25
), R(r26
),
742 R(r27
), R(r28
), R(gp
),
749 do_entUnaUser(void __user
* va
, unsigned long opcode
,
750 unsigned long reg
, struct pt_regs
*regs
)
752 static DEFINE_RATELIMIT_STATE(ratelimit
, 5 * HZ
, 5);
754 unsigned long tmp1
, tmp2
, tmp3
, tmp4
;
755 unsigned long fake_reg
, *reg_addr
= &fake_reg
;
759 /* Check the UAC bits to decide what the user wants us to do
760 with the unaliged access. */
762 if (!(current_thread_info()->status
& TS_UAC_NOPRINT
)) {
763 if (__ratelimit(&ratelimit
)) {
764 printk("%s(%d): unaligned trap at %016lx: %p %lx %ld\n",
765 current
->comm
, task_pid_nr(current
),
766 regs
->pc
- 4, va
, opcode
, reg
);
769 if ((current_thread_info()->status
& TS_UAC_SIGBUS
))
771 /* Not sure why you'd want to use this, but... */
772 if ((current_thread_info()->status
& TS_UAC_NOFIX
))
775 /* Don't bother reading ds in the access check since we already
776 know that this came from the user. Also rely on the fact that
777 the page at TASK_SIZE is unmapped and so can't be touched anyway. */
778 if ((unsigned long)va
>= TASK_SIZE
)
781 ++unaligned
[1].count
;
782 unaligned
[1].va
= (unsigned long)va
;
783 unaligned
[1].pc
= regs
->pc
- 4;
785 if ((1L << opcode
) & OP_INT_MASK
) {
786 /* it's an integer load/store */
788 reg_addr
= (unsigned long *)
789 ((char *)regs
+ unauser_reg_offsets
[reg
]);
790 } else if (reg
== 30) {
791 /* usp in PAL regs */
794 /* zero "register" */
799 /* We don't want to use the generic get/put unaligned macros as
800 we want to trap exceptions. Only if we actually get an
801 exception will we decide whether we should have caught it. */
804 case 0x0c: /* ldwu */
805 __asm__
__volatile__(
806 "1: ldq_u %1,0(%3)\n"
807 "2: ldq_u %2,1(%3)\n"
813 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
)
817 *reg_addr
= tmp1
|tmp2
;
821 __asm__
__volatile__(
822 "1: ldq_u %1,0(%3)\n"
823 "2: ldq_u %2,3(%3)\n"
829 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
)
833 alpha_write_fp_reg(reg
, s_mem_to_reg((int)(tmp1
|tmp2
)));
837 __asm__
__volatile__(
838 "1: ldq_u %1,0(%3)\n"
839 "2: ldq_u %2,7(%3)\n"
845 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
)
849 alpha_write_fp_reg(reg
, tmp1
|tmp2
);
853 __asm__
__volatile__(
854 "1: ldq_u %1,0(%3)\n"
855 "2: ldq_u %2,3(%3)\n"
861 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
)
865 *reg_addr
= (int)(tmp1
|tmp2
);
869 __asm__
__volatile__(
870 "1: ldq_u %1,0(%3)\n"
871 "2: ldq_u %2,7(%3)\n"
877 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
)
881 *reg_addr
= tmp1
|tmp2
;
884 /* Note that the store sequences do not indicate that they change
885 memory because it _should_ be affecting nothing in this context.
886 (Otherwise we have other, much larger, problems.) */
888 __asm__
__volatile__(
889 "1: ldq_u %2,1(%5)\n"
890 "2: ldq_u %1,0(%5)\n"
897 "3: stq_u %2,1(%5)\n"
898 "4: stq_u %1,0(%5)\n"
904 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
),
905 "=&r"(tmp3
), "=&r"(tmp4
)
906 : "r"(va
), "r"(*reg_addr
), "0"(0));
912 fake_reg
= s_reg_to_mem(alpha_read_fp_reg(reg
));
916 __asm__
__volatile__(
917 "1: ldq_u %2,3(%5)\n"
918 "2: ldq_u %1,0(%5)\n"
925 "3: stq_u %2,3(%5)\n"
926 "4: stq_u %1,0(%5)\n"
932 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
),
933 "=&r"(tmp3
), "=&r"(tmp4
)
934 : "r"(va
), "r"(*reg_addr
), "0"(0));
940 fake_reg
= alpha_read_fp_reg(reg
);
944 __asm__
__volatile__(
945 "1: ldq_u %2,7(%5)\n"
946 "2: ldq_u %1,0(%5)\n"
953 "3: stq_u %2,7(%5)\n"
954 "4: stq_u %1,0(%5)\n"
960 : "=r"(error
), "=&r"(tmp1
), "=&r"(tmp2
),
961 "=&r"(tmp3
), "=&r"(tmp4
)
962 : "r"(va
), "r"(*reg_addr
), "0"(0));
968 /* What instruction were you trying to use, exactly? */
972 /* Only integer loads should get here; everyone else returns early. */
978 regs
->pc
-= 4; /* make pc point to faulting insn */
979 info
.si_signo
= SIGSEGV
;
982 /* We need to replicate some of the logic in mm/fault.c,
983 since we don't have access to the fault code in the
984 exception handling return path. */
985 if ((unsigned long)va
>= TASK_SIZE
)
986 info
.si_code
= SEGV_ACCERR
;
988 struct mm_struct
*mm
= current
->mm
;
989 down_read(&mm
->mmap_sem
);
990 if (find_vma(mm
, (unsigned long)va
))
991 info
.si_code
= SEGV_ACCERR
;
993 info
.si_code
= SEGV_MAPERR
;
994 up_read(&mm
->mmap_sem
);
997 send_sig_info(SIGSEGV
, &info
, current
);
1002 info
.si_signo
= SIGBUS
;
1004 info
.si_code
= BUS_ADRALN
;
1006 send_sig_info(SIGBUS
, &info
, current
);
1013 /* Tell PAL-code what global pointer we want in the kernel. */
1014 register unsigned long gptr
__asm__("$29");
1017 /* Hack for Multia (UDB) and JENSEN: some of their SRMs have
1018 a bug in the handling of the opDEC fault. Fix it up if so. */
1019 if (implver() == IMPLVER_EV4
)