arch/alpha/lib/ev6-csum_ipv6_magic.S

   1 /*
   2  * arch/alpha/lib/ev6-csum_ipv6_magic.S
   3  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
   4  *
   5  * unsigned short csum_ipv6_magic(struct in6_addr *saddr,
   6  *                                struct in6_addr *daddr,
   7  *                                __u32 len,
   8  *                                unsigned short proto,
   9  *                                unsigned int csum);
  10  *
  11  * Much of the information about 21264 scheduling/coding comes from:
  12  *      Compiler Writer's Guide for the Alpha 21264
  13  *      abbreviated as 'CWG' in other comments here
  14  *      ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
  15  * Scheduling notation:
  16  *      E       - either cluster
  17  *      U       - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
  18  *      L       - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
  19  * Try not to change the actual algorithm if possible for consistency.
  20  * Determining actual stalls (other than slotting) doesn't appear to be easy to do.
  21  *
  22  * unsigned short csum_ipv6_magic(struct in6_addr *saddr,
  23  *                                struct in6_addr *daddr,
  24  *                                __u32 len,
  25  *                                unsigned short proto,
  26  *                                unsigned int csum);
  27  *
  28  * Swap <proto> (takes form 0xaabb)
  29  * Then shift it left by 48, so result is:
  30  *      0xbbaa0000 00000000
  31  * Then turn it back into a sign extended 32-bit item
  32  *      0xbbaa0000
  33  *
  34  * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
  35  * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
  36  * Assume input takes form 0xAABBCCDD
  37  *
  38  * Finally, original 'folding' approach is to split the long into 4 unsigned shorts
  39  * add 4 ushorts, resulting in ushort/carry
  40  * add carry bits + ushort --> ushort
  41  * add carry bits + ushort --> ushort (in case the carry results in an overflow)
  42  * Truncate to a ushort.  (took 13 instructions)
  43  * From doing some testing, using the approach in checksum.c:from64to16()
  44  * results in the same outcome:
  45  * split into 2 uints, add those, generating a ulong
  46  * add the 3 low ushorts together, generating a uint
  47  * a final add of the 2 lower ushorts
  48  * truncating the result.
  49  */
  50
  51         .globl csum_ipv6_magic
  52         .align 4
  53         .ent csum_ipv6_magic
  54         .frame $30,0,$26,0
  55 csum_ipv6_magic:
  56         .prologue 0
  57
  58         ldq     $0,0($16)       # L : Latency: 3
  59         inslh   $18,7,$4        # U : 0000000000AABBCC
  60         ldq     $1,8($16)       # L : Latency: 3
  61         sll     $19,8,$7        # U : U L U L : 0x00000000 00aabb00
  62
  63         zapnot  $20,15,$20      # U : zero extend incoming csum
  64         ldq     $2,0($17)       # L : Latency: 3
  65         sll     $19,24,$19      # U : U L L U : 0x000000aa bb000000
  66         inswl   $18,3,$18       # U : 000000CCDD000000
  67
  68         ldq     $3,8($17)       # L : Latency: 3
  69         bis     $18,$4,$18      # E : 000000CCDDAABBCC
  70         addl    $19,$7,$19      # E : <sign bits>bbaabb00
  71         nop                     # E : U L U L
  72
  73         addq    $20,$0,$20      # E : begin summing the words
  74         srl     $18,16,$4       # U : 0000000000CCDDAA
  75         zap     $19,0x3,$19     # U : <sign bits>bbaa0000
  76         nop                     # E : L U U L
  77
  78         cmpult  $20,$0,$0       # E :
  79         addq    $20,$1,$20      # E :
  80         zapnot  $18,0xa,$18     # U : 00000000DD00BB00
  81         zap     $4,0xa,$4       # U : U U L L : 0000000000CC00AA
  82
  83         or      $18,$4,$18      # E : 00000000DDCCBBAA
  84         nop                     # E :
  85         cmpult  $20,$1,$1       # E :
  86         addq    $20,$2,$20      # E : U L U L
  87
  88         cmpult  $20,$2,$2       # E :
  89         addq    $20,$3,$20      # E :
  90         cmpult  $20,$3,$3       # E : (1 cycle stall on $20)
  91         addq    $20,$18,$20     # E : U L U L (1 cycle stall on $20)
  92
  93         cmpult  $20,$18,$18     # E :
  94         addq    $20,$19,$20     # E : (1 cycle stall on $20)
  95         addq    $0,$1,$0        # E : merge the carries back into the csum
  96         addq    $2,$3,$2        # E :
  97
  98         cmpult  $20,$19,$19     # E :
  99         addq    $18,$19,$18     # E : (1 cycle stall on $19)
 100         addq    $0,$2,$0        # E :
 101         addq    $20,$18,$20     # E : U L U L :
 102                 /* (1 cycle stall on $18, 2 cycles on $20) */
 103
 104         addq    $0,$20,$0       # E :
 105         zapnot  $0,15,$1        # U : Start folding output (1 cycle stall on $0)
 106         nop                     # E :
 107         srl     $0,32,$0        # U : U L U L : (1 cycle stall on $0)
 108
 109         addq    $1,$0,$1        # E : Finished generating ulong
 110         extwl   $1,2,$2         # U : ushort[1] (1 cycle stall on $1)
 111         zapnot  $1,3,$0         # U : ushort[0] (1 cycle stall on $1)
 112         extwl   $1,4,$1         # U : ushort[2] (1 cycle stall on $1)
 113
 114         addq    $0,$2,$0        # E
 115         addq    $0,$1,$3        # E : Finished generating uint
 116                 /* (1 cycle stall on $0) */
 117         extwl   $3,2,$1         # U : ushort[1] (1 cycle stall on $3)
 118         nop                     # E : L U L U
 119
 120         addq    $1,$3,$0        # E : Final carry
 121         not     $0,$4           # E : complement (1 cycle stall on $0)
 122         zapnot  $4,3,$0         # U : clear upper garbage bits
 123                 /* (1 cycle stall on $4) */
 124         ret                     # L0 : L U L U
 125
 126         .end csum_ipv6_magic