arch/arc/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 #
   3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4 #
   5
   6 config ARC
   7         def_bool y
   8         select ARC_TIMERS
   9         select ARCH_HAS_CACHE_LINE_SIZE
  10         select ARCH_HAS_DEBUG_VM_PGTABLE
  11         select ARCH_HAS_DMA_PREP_COHERENT
  12         select ARCH_HAS_PTE_SPECIAL
  13         select ARCH_HAS_SETUP_DMA_OPS
  14         select ARCH_HAS_SYNC_DMA_FOR_CPU
  15         select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  16         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
  17         select ARCH_32BIT_OFF_T
  18         select BUILDTIME_TABLE_SORT
  19         select CLONE_BACKWARDS
  20         select COMMON_CLK
  21         select DMA_DIRECT_REMAP
  22         select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
  23         select GENERIC_FIND_FIRST_BIT
  24         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
  25         select GENERIC_IRQ_SHOW
  26         select GENERIC_PCI_IOMAP
  27         select GENERIC_PENDING_IRQ if SMP
  28         select GENERIC_SCHED_CLOCK
  29         select GENERIC_SMP_IDLE_THREAD
  30         select HAVE_ARCH_KGDB
  31         select HAVE_ARCH_TRACEHOOK
  32         select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
  33         select HAVE_DEBUG_STACKOVERFLOW
  34         select HAVE_DEBUG_KMEMLEAK
  35         select HAVE_FUTEX_CMPXCHG if FUTEX
  36         select HAVE_IOREMAP_PROT
  37         select HAVE_KERNEL_GZIP
  38         select HAVE_KERNEL_LZMA
  39         select HAVE_KPROBES
  40         select HAVE_KRETPROBES
  41         select HAVE_MOD_ARCH_SPECIFIC
  42         select HAVE_PERF_EVENTS
  43         select HANDLE_DOMAIN_IRQ
  44         select IRQ_DOMAIN
  45         select MODULES_USE_ELF_RELA
  46         select OF
  47         select OF_EARLY_FLATTREE
  48         select PCI_SYSCALL if PCI
  49         select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
  50         select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
  51         select SET_FS
  52         select TRACE_IRQFLAGS_SUPPORT
  53
  54 config LOCKDEP_SUPPORT
  55         def_bool y
  56
  57 config SCHED_OMIT_FRAME_POINTER
  58         def_bool y
  59
  60 config GENERIC_CSUM
  61         def_bool y
  62
  63 config ARCH_FLATMEM_ENABLE
  64         def_bool y
  65
  66 config MMU
  67         def_bool y
  68
  69 config NO_IOPORT_MAP
  70         def_bool y
  71
  72 config GENERIC_CALIBRATE_DELAY
  73         def_bool y
  74
  75 config GENERIC_HWEIGHT
  76         def_bool y
  77
  78 config STACKTRACE_SUPPORT
  79         def_bool y
  80         select STACKTRACE
  81
  82 menu "ARC Architecture Configuration"
  83
  84 menu "ARC Platform/SoC/Board"
  85
  86 source "arch/arc/plat-tb10x/Kconfig"
  87 source "arch/arc/plat-axs10x/Kconfig"
  88 source "arch/arc/plat-hsdk/Kconfig"
  89
  90 endmenu
  91
  92 choice
  93         prompt "ARC Instruction Set"
  94         default ISA_ARCV2
  95
  96 config ISA_ARCOMPACT
  97         bool "ARCompact ISA"
  98         select CPU_NO_EFFICIENT_FFS
  99         help
 100           The original ARC ISA of ARC600/700 cores
 101
 102 config ISA_ARCV2
 103         bool "ARC ISA v2"
 104         select ARC_TIMERS_64BIT
 105         help
 106           ISA for the Next Generation ARC-HS cores
 107
 108 endchoice
 109
 110 menu "ARC CPU Configuration"
 111
 112 choice
 113         prompt "ARC Core"
 114         default ARC_CPU_770 if ISA_ARCOMPACT
 115         default ARC_CPU_HS if ISA_ARCV2
 116
 117 config ARC_CPU_770
 118         bool "ARC770"
 119         depends on ISA_ARCOMPACT
 120         select ARC_HAS_SWAPE
 121         help
 122           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
 123           This core has a bunch of cool new features:
 124           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
 125                    Shared Address Spaces (for sharing TLB entries in MMU)
 126           -Caches: New Prog Model, Region Flush
 127           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
 128
 129 config ARC_CPU_HS
 130         bool "ARC-HS"
 131         depends on ISA_ARCV2
 132         help
 133           Support for ARC HS38x Cores based on ARCv2 ISA
 134           The notable features are:
 135             - SMP configurations of up to 4 cores with coherency
 136             - Optional L2 Cache and IO-Coherency
 137             - Revised Interrupt Architecture (multiple priorites, reg banks,
 138                 auto stack switch, auto regfile save/restore)
 139             - MMUv4 (PIPT dcache, Huge Pages)
 140             - Instructions for
 141                 * 64bit load/store: LDD, STD
 142                 * Hardware assisted divide/remainder: DIV, REM
 143                 * Function prologue/epilogue: ENTER_S, LEAVE_S
 144                 * IRQ enable/disable: CLRI, SETI
 145                 * pop count: FFS, FLS
 146                 * SETcc, BMSKN, XBFU...
 147
 148 endchoice
 149
 150 config ARC_TUNE_MCPU
 151         string "Override default -mcpu compiler flag"
 152         default ""
 153         help
 154           Override default -mcpu=xxx compiler flag (which is set depending on
 155           the ISA version) with the specified value.
 156           NOTE: If specified flag isn't supported by current compiler the
 157           ISA default value will be used as a fallback.
 158
 159 config CPU_BIG_ENDIAN
 160         bool "Enable Big Endian Mode"
 161         help
 162           Build kernel for Big Endian Mode of ARC CPU
 163
 164 config SMP
 165         bool "Symmetric Multi-Processing"
 166         select ARC_MCIP if ISA_ARCV2
 167         help
 168           This enables support for systems with more than one CPU.
 169
 170 if SMP
 171
 172 config NR_CPUS
 173         int "Maximum number of CPUs (2-4096)"
 174         range 2 4096
 175         default "4"
 176
 177 config ARC_SMP_HALT_ON_RESET
 178         bool "Enable Halt-on-reset boot mode"
 179         help
 180           In SMP configuration cores can be configured as Halt-on-reset
 181           or they could all start at same time. For Halt-on-reset, non
 182           masters are parked until Master kicks them so they can start off
 183           at designated entry point. For other case, all jump to common
 184           entry point and spin wait for Master's signal.
 185
 186 endif #SMP
 187
 188 config ARC_MCIP
 189         bool "ARConnect Multicore IP (MCIP) Support "
 190         depends on ISA_ARCV2
 191         default y if SMP
 192         help
 193           This IP block enables SMP in ARC-HS38 cores.
 194           It provides for cross-core interrupts, multi-core debug
 195           hardware semaphores, shared memory,....
 196
 197 menuconfig ARC_CACHE
 198         bool "Enable Cache Support"
 199         default y
 200
 201 if ARC_CACHE
 202
 203 config ARC_CACHE_LINE_SHIFT
 204         int "Cache Line Length (as power of 2)"
 205         range 5 7
 206         default "6"
 207         help
 208           Starting with ARC700 4.9, Cache line length is configurable,
 209           This option specifies "N", with Line-len = 2 power N
 210           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
 211           Linux only supports same line lengths for I and D caches.
 212
 213 config ARC_HAS_ICACHE
 214         bool "Use Instruction Cache"
 215         default y
 216
 217 config ARC_HAS_DCACHE
 218         bool "Use Data Cache"
 219         default y
 220
 221 config ARC_CACHE_PAGES
 222         bool "Per Page Cache Control"
 223         default y
 224         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
 225         help
 226           This can be used to over-ride the global I/D Cache Enable on a
 227           per-page basis (but only for pages accessed via MMU such as
 228           Kernel Virtual address or User Virtual Address)
 229           TLB entries have a per-page Cache Enable Bit.
 230           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
 231           Global DISABLE + Per Page ENABLE won't work
 232
 233 config ARC_CACHE_VIPT_ALIASING
 234         bool "Support VIPT Aliasing D$"
 235         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
 236
 237 endif #ARC_CACHE
 238
 239 config ARC_HAS_ICCM
 240         bool "Use ICCM"
 241         help
 242           Single Cycle RAMS to store Fast Path Code
 243
 244 config ARC_ICCM_SZ
 245         int "ICCM Size in KB"
 246         default "64"
 247         depends on ARC_HAS_ICCM
 248
 249 config ARC_HAS_DCCM
 250         bool "Use DCCM"
 251         help
 252           Single Cycle RAMS to store Fast Path Data
 253
 254 config ARC_DCCM_SZ
 255         int "DCCM Size in KB"
 256         default "64"
 257         depends on ARC_HAS_DCCM
 258
 259 config ARC_DCCM_BASE
 260         hex "DCCM map address"
 261         default "0xA0000000"
 262         depends on ARC_HAS_DCCM
 263
 264 choice
 265         prompt "MMU Version"
 266         default ARC_MMU_V3 if ISA_ARCOMPACT
 267         default ARC_MMU_V4 if ISA_ARCV2
 268
 269 config ARC_MMU_V3
 270         bool "MMU v3"
 271         depends on ISA_ARCOMPACT
 272         help
 273           Introduced with ARC700 4.10: New Features
 274           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 275           Shared Address Spaces (SASID)
 276
 277 config ARC_MMU_V4
 278         bool "MMU v4"
 279         depends on ISA_ARCV2
 280
 281 endchoice
 282
 283
 284 choice
 285         prompt "MMU Page Size"
 286         default ARC_PAGE_SIZE_8K
 287
 288 config ARC_PAGE_SIZE_8K
 289         bool "8KB"
 290         help
 291           Choose between 8k vs 16k
 292
 293 config ARC_PAGE_SIZE_16K
 294         bool "16KB"
 295
 296 config ARC_PAGE_SIZE_4K
 297         bool "4KB"
 298         depends on ARC_MMU_V3 || ARC_MMU_V4
 299
 300 endchoice
 301
 302 choice
 303         prompt "MMU Super Page Size"
 304         depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
 305         default ARC_HUGEPAGE_2M
 306
 307 config ARC_HUGEPAGE_2M
 308         bool "2MB"
 309
 310 config ARC_HUGEPAGE_16M
 311         bool "16MB"
 312
 313 endchoice
 314
 315 config PGTABLE_LEVELS
 316         int "Number of Page table levels"
 317         default 2
 318
 319 config ARC_COMPACT_IRQ_LEVELS
 320         depends on ISA_ARCOMPACT
 321         bool "Setup Timer IRQ as high Priority"
 322         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
 323         depends on !SMP
 324
 325 config ARC_FPU_SAVE_RESTORE
 326         bool "Enable FPU state persistence across context switch"
 327         help
 328           ARCompact FPU has internal registers to assist with Double precision
 329           Floating Point operations. There are control and stauts registers
 330           for floating point exceptions and rounding modes. These are
 331           preserved across task context switch when enabled.
 332
 333 config ARC_CANT_LLSC
 334         def_bool n
 335
 336 config ARC_HAS_LLSC
 337         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
 338         default y
 339         depends on !ARC_CANT_LLSC
 340
 341 config ARC_HAS_SWAPE
 342         bool "Insn: SWAPE (endian-swap)"
 343         default y
 344
 345 if ISA_ARCV2
 346
 347 config ARC_USE_UNALIGNED_MEM_ACCESS
 348         bool "Enable unaligned access in HW"
 349         default y
 350         select HAVE_EFFICIENT_UNALIGNED_ACCESS
 351         help
 352           The ARC HS architecture supports unaligned memory access
 353           which is disabled by default. Enable unaligned access in
 354           hardware and use software to use it
 355
 356 config ARC_HAS_LL64
 357         bool "Insn: 64bit LDD/STD"
 358         help
 359           Enable gcc to generate 64-bit load/store instructions
 360           ISA mandates even/odd registers to allow encoding of two
 361           dest operands with 2 possible source operands.
 362         default y
 363
 364 config ARC_HAS_DIV_REM
 365         bool "Insn: div, divu, rem, remu"
 366         default y
 367
 368 config ARC_HAS_ACCL_REGS
 369         bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
 370         default y
 371         help
 372           Depending on the configuration, CPU can contain accumulator reg-pair
 373           (also referred to as r58:r59). These can also be used by gcc as GPR so
 374           kernel needs to save/restore per process
 375
 376 config ARC_DSP_HANDLED
 377         def_bool n
 378
 379 config ARC_DSP_SAVE_RESTORE_REGS
 380         def_bool n
 381
 382 choice
 383         prompt "DSP support"
 384         default ARC_DSP_NONE
 385         help
 386           Depending on the configuration, CPU can contain DSP registers
 387           (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
 388           Below are options describing how to handle these registers in
 389           interrupt entry / exit and in context switch.
 390
 391 config ARC_DSP_NONE
 392         bool "No DSP extension presence in HW"
 393         help
 394           No DSP extension presence in HW
 395
 396 config ARC_DSP_KERNEL
 397         bool "DSP extension in HW, no support for userspace"
 398         select ARC_HAS_ACCL_REGS
 399         select ARC_DSP_HANDLED
 400         help
 401           DSP extension presence in HW, no support for DSP-enabled userspace
 402           applications. We don't save / restore DSP registers and only do
 403           some minimal preparations so userspace won't be able to break kernel
 404
 405 config ARC_DSP_USERSPACE
 406         bool "Support DSP for userspace apps"
 407         select ARC_HAS_ACCL_REGS
 408         select ARC_DSP_HANDLED
 409         select ARC_DSP_SAVE_RESTORE_REGS
 410         help
 411           DSP extension presence in HW, support save / restore DSP registers to
 412           run DSP-enabled userspace applications
 413
 414 config ARC_DSP_AGU_USERSPACE
 415         bool "Support DSP with AGU for userspace apps"
 416         select ARC_HAS_ACCL_REGS
 417         select ARC_DSP_HANDLED
 418         select ARC_DSP_SAVE_RESTORE_REGS
 419         help
 420           DSP and AGU extensions presence in HW, support save / restore DSP
 421           and AGU registers to run DSP-enabled userspace applications
 422 endchoice
 423
 424 config ARC_IRQ_NO_AUTOSAVE
 425         bool "Disable hardware autosave regfile on interrupts"
 426         default n
 427         help
 428           On HS cores, taken interrupt auto saves the regfile on stack.
 429           This is programmable and can be optionally disabled in which case
 430           software INTERRUPT_PROLOGUE/EPILGUE do the needed work
 431
 432 config ARC_LPB_DISABLE
 433         bool "Disable loop buffer (LPB)"
 434         help
 435           On HS cores, loop buffer (LPB) is programmable in runtime and can
 436           be optionally disabled.
 437
 438 endif # ISA_ARCV2
 439
 440 endmenu   # "ARC CPU Configuration"
 441
 442 config LINUX_LINK_BASE
 443         hex "Kernel link address"
 444         default "0x80000000"
 445         help
 446           ARC700 divides the 32 bit phy address space into two equal halves
 447           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
 448           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
 449           Typically Linux kernel is linked at the start of untransalted addr,
 450           hence the default value of 0x8zs.
 451           However some customers have peripherals mapped at this addr, so
 452           Linux needs to be scooted a bit.
 453           If you don't know what the above means, leave this setting alone.
 454           This needs to match memory start address specified in Device Tree
 455
 456 config LINUX_RAM_BASE
 457         hex "RAM base address"
 458         default LINUX_LINK_BASE
 459         help
 460           By default Linux is linked at base of RAM. However in some special
 461           cases (such as HSDK), Linux can't be linked at start of DDR, hence
 462           this option.
 463
 464 config HIGHMEM
 465         bool "High Memory Support"
 466         select HAVE_ARCH_PFN_VALID
 467         select KMAP_LOCAL
 468         help
 469           With ARC 2G:2G address split, only upper 2G is directly addressable by
 470           kernel. Enable this to potentially allow access to rest of 2G and PAE
 471           in future
 472
 473 config ARC_HAS_PAE40
 474         bool "Support for the 40-bit Physical Address Extension"
 475         depends on ISA_ARCV2
 476         select HIGHMEM
 477         select PHYS_ADDR_T_64BIT
 478         help
 479           Enable access to physical memory beyond 4G, only supported on
 480           ARC cores with 40 bit Physical Addressing support
 481
 482 config ARC_KVADDR_SIZE
 483         int "Kernel Virtual Address Space size (MB)"
 484         range 0 512
 485         default "256"
 486         help
 487           The kernel address space is carved out of 256MB of translated address
 488           space for catering to vmalloc, modules, pkmap, fixmap. This however may
 489           not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
 490           this to be stretched to 512 MB (by extending into the reserved
 491           kernel-user gutter)
 492
 493 config ARC_CURR_IN_REG
 494         bool "Dedicate Register r25 for current_task pointer"
 495         default y
 496         help
 497           This reserved Register R25 to point to Current Task in
 498           kernel mode. This saves memory access for each such access
 499
 500
 501 config ARC_EMUL_UNALIGNED
 502         bool "Emulate unaligned memory access (userspace only)"
 503         select SYSCTL_ARCH_UNALIGN_NO_WARN
 504         select SYSCTL_ARCH_UNALIGN_ALLOW
 505         depends on ISA_ARCOMPACT
 506         help
 507           This enables misaligned 16 & 32 bit memory access from user space.
 508           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
 509           potential bugs in code
 510
 511 config HZ
 512         int "Timer Frequency"
 513         default 100
 514
 515 config ARC_METAWARE_HLINK
 516         bool "Support for Metaware debugger assisted Host access"
 517         help
 518           This options allows a Linux userland apps to directly access
 519           host file system (open/creat/read/write etc) with help from
 520           Metaware Debugger. This can come in handy for Linux-host communication
 521           when there is no real usable peripheral such as EMAC.
 522
 523 menuconfig ARC_DBG
 524         bool "ARC debugging"
 525         default y
 526
 527 if ARC_DBG
 528
 529 config ARC_DW2_UNWIND
 530         bool "Enable DWARF specific kernel stack unwind"
 531         default y
 532         select KALLSYMS
 533         help
 534           Compiles the kernel with DWARF unwind information and can be used
 535           to get stack backtraces.
 536
 537           If you say Y here the resulting kernel image will be slightly larger
 538           but not slower, and it will give very useful debugging information.
 539           If you don't debug the kernel, you can say N, but we may not be able
 540           to solve problems without frame unwind information
 541
 542 config ARC_DBG_JUMP_LABEL
 543         bool "Paranoid checks in Static Keys (jump labels) code"
 544         depends on JUMP_LABEL
 545         default y if STATIC_KEYS_SELFTEST
 546         help
 547           Enable paranoid checks and self-test of both ARC-specific and generic
 548           part of static keys (jump labels) related code.
 549 endif
 550
 551 config ARC_BUILTIN_DTB_NAME
 552         string "Built in DTB"
 553         help
 554           Set the name of the DTB to embed in the vmlinux binary
 555           Leaving it blank selects the minimal "skeleton" dtb
 556
 557 endmenu  # "ARC Architecture Configuration"
 558
 559 config FORCE_MAX_ZONEORDER
 560         int "Maximum zone order"
 561         default "12" if ARC_HUGEPAGE_16M
 562         default "11"
 563
 564 source "kernel/power/Kconfig"