arch/arc/Kconfig

   1 #
   2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3 #
   4 # This program is free software; you can redistribute it and/or modify
   5 # it under the terms of the GNU General Public License version 2 as
   6 # published by the Free Software Foundation.
   7 #
   8
   9 config ARC
  10         def_bool y
  11         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
  12         select BUILDTIME_EXTABLE_SORT
  13         select COMMON_CLK
  14         select CLONE_BACKWARDS
  15         # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
  16         select DEVTMPFS if !INITRAMFS_SOURCE=""
  17         select GENERIC_ATOMIC64
  18         select GENERIC_CLOCKEVENTS
  19         select GENERIC_FIND_FIRST_BIT
  20         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
  21         select GENERIC_IRQ_SHOW
  22         select GENERIC_PENDING_IRQ if SMP
  23         select GENERIC_SMP_IDLE_THREAD
  24         select HAVE_ARCH_KGDB
  25         select HAVE_ARCH_TRACEHOOK
  26         select HAVE_FUTEX_CMPXCHG
  27         select HAVE_IOREMAP_PROT
  28         select HAVE_KPROBES
  29         select HAVE_KRETPROBES
  30         select HAVE_MEMBLOCK
  31         select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
  32         select HAVE_OPROFILE
  33         select HAVE_PERF_EVENTS
  34         select IRQ_DOMAIN
  35         select MODULES_USE_ELF_RELA
  36         select NO_BOOTMEM
  37         select OF
  38         select OF_EARLY_FLATTREE
  39         select PERF_USE_VMALLOC
  40         select HAVE_DEBUG_STACKOVERFLOW
  41
  42 config TRACE_IRQFLAGS_SUPPORT
  43         def_bool y
  44
  45 config LOCKDEP_SUPPORT
  46         def_bool y
  47
  48 config SCHED_OMIT_FRAME_POINTER
  49         def_bool y
  50
  51 config GENERIC_CSUM
  52         def_bool y
  53
  54 config RWSEM_GENERIC_SPINLOCK
  55         def_bool y
  56
  57 config ARCH_FLATMEM_ENABLE
  58         def_bool y
  59
  60 config MMU
  61         def_bool y
  62
  63 config NO_IOPORT_MAP
  64         def_bool y
  65
  66 config GENERIC_CALIBRATE_DELAY
  67         def_bool y
  68
  69 config GENERIC_HWEIGHT
  70         def_bool y
  71
  72 config STACKTRACE_SUPPORT
  73         def_bool y
  74         select STACKTRACE
  75
  76 config HAVE_LATENCYTOP_SUPPORT
  77         def_bool y
  78
  79 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
  80         def_bool y
  81         depends on ARC_MMU_V4
  82
  83 source "init/Kconfig"
  84 source "kernel/Kconfig.freezer"
  85
  86 menu "ARC Architecture Configuration"
  87
  88 menu "ARC Platform/SoC/Board"
  89
  90 source "arch/arc/plat-sim/Kconfig"
  91 source "arch/arc/plat-tb10x/Kconfig"
  92 source "arch/arc/plat-axs10x/Kconfig"
  93 #New platform adds here
  94
  95 endmenu
  96
  97 choice
  98         prompt "ARC Instruction Set"
  99         default ISA_ARCOMPACT
 100
 101 config ISA_ARCOMPACT
 102         bool "ARCompact ISA"
 103         help
 104           The original ARC ISA of ARC600/700 cores
 105
 106 config ISA_ARCV2
 107         bool "ARC ISA v2"
 108         help
 109           ISA for the Next Generation ARC-HS cores
 110
 111 endchoice
 112
 113 menu "ARC CPU Configuration"
 114
 115 choice
 116         prompt "ARC Core"
 117         default ARC_CPU_770 if ISA_ARCOMPACT
 118         default ARC_CPU_HS if ISA_ARCV2
 119
 120 if ISA_ARCOMPACT
 121
 122 config ARC_CPU_750D
 123         bool "ARC750D"
 124         select ARC_CANT_LLSC
 125         help
 126           Support for ARC750 core
 127
 128 config ARC_CPU_770
 129         bool "ARC770"
 130         select ARC_HAS_SWAPE
 131         help
 132           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
 133           This core has a bunch of cool new features:
 134           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
 135                    Shared Address Spaces (for sharing TLB entires in MMU)
 136           -Caches: New Prog Model, Region Flush
 137           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
 138
 139 endif   #ISA_ARCOMPACT
 140
 141 config ARC_CPU_HS
 142         bool "ARC-HS"
 143         depends on ISA_ARCV2
 144         help
 145           Support for ARC HS38x Cores based on ARCv2 ISA
 146           The notable features are:
 147             - SMP configurations of upto 4 core with coherency
 148             - Optional L2 Cache and IO-Coherency
 149             - Revised Interrupt Architecture (multiple priorites, reg banks,
 150                 auto stack switch, auto regfile save/restore)
 151             - MMUv4 (PIPT dcache, Huge Pages)
 152             - Instructions for
 153                 * 64bit load/store: LDD, STD
 154                 * Hardware assisted divide/remainder: DIV, REM
 155                 * Function prologue/epilogue: ENTER_S, LEAVE_S
 156                 * IRQ enable/disable: CLRI, SETI
 157                 * pop count: FFS, FLS
 158                 * SETcc, BMSKN, XBFU...
 159
 160 endchoice
 161
 162 config CPU_BIG_ENDIAN
 163         bool "Enable Big Endian Mode"
 164         default n
 165         help
 166           Build kernel for Big Endian Mode of ARC CPU
 167
 168 config SMP
 169         bool "Symmetric Multi-Processing"
 170         default n
 171         select ARC_HAS_COH_CACHES if ISA_ARCV2
 172         select ARC_MCIP if ISA_ARCV2
 173         help
 174           This enables support for systems with more than one CPU.
 175
 176 if SMP
 177
 178 config ARC_HAS_COH_CACHES
 179         def_bool n
 180
 181 config ARC_HAS_REENTRANT_IRQ_LV2
 182         def_bool n
 183
 184 config ARC_MCIP
 185         bool "ARConnect Multicore IP (MCIP) Support "
 186         depends on ISA_ARCV2
 187         help
 188           This IP block enables SMP in ARC-HS38 cores.
 189           It provides for cross-core interrupts, multi-core debug
 190           hardware semaphores, shared memory,....
 191
 192 config NR_CPUS
 193         int "Maximum number of CPUs (2-4096)"
 194         range 2 4096
 195         default "4"
 196
 197 endif   #SMP
 198
 199 menuconfig ARC_CACHE
 200         bool "Enable Cache Support"
 201         default y
 202         # if SMP, cache enabled ONLY if ARC implementation has cache coherency
 203         depends on !SMP || ARC_HAS_COH_CACHES
 204
 205 if ARC_CACHE
 206
 207 config ARC_CACHE_LINE_SHIFT
 208         int "Cache Line Length (as power of 2)"
 209         range 5 7
 210         default "6"
 211         help
 212           Starting with ARC700 4.9, Cache line length is configurable,
 213           This option specifies "N", with Line-len = 2 power N
 214           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
 215           Linux only supports same line lengths for I and D caches.
 216
 217 config ARC_HAS_ICACHE
 218         bool "Use Instruction Cache"
 219         default y
 220
 221 config ARC_HAS_DCACHE
 222         bool "Use Data Cache"
 223         default y
 224
 225 config ARC_CACHE_PAGES
 226         bool "Per Page Cache Control"
 227         default y
 228         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
 229         help
 230           This can be used to over-ride the global I/D Cache Enable on a
 231           per-page basis (but only for pages accessed via MMU such as
 232           Kernel Virtual address or User Virtual Address)
 233           TLB entries have a per-page Cache Enable Bit.
 234           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
 235           Global DISABLE + Per Page ENABLE won't work
 236
 237 config ARC_CACHE_VIPT_ALIASING
 238         bool "Support VIPT Aliasing D$"
 239         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
 240         default n
 241
 242 endif   #ARC_CACHE
 243
 244 config ARC_HAS_ICCM
 245         bool "Use ICCM"
 246         help
 247           Single Cycle RAMS to store Fast Path Code
 248         default n
 249
 250 config ARC_ICCM_SZ
 251         int "ICCM Size in KB"
 252         default "64"
 253         depends on ARC_HAS_ICCM
 254
 255 config ARC_HAS_DCCM
 256         bool "Use DCCM"
 257         help
 258           Single Cycle RAMS to store Fast Path Data
 259         default n
 260
 261 config ARC_DCCM_SZ
 262         int "DCCM Size in KB"
 263         default "64"
 264         depends on ARC_HAS_DCCM
 265
 266 config ARC_DCCM_BASE
 267         hex "DCCM map address"
 268         default "0xA0000000"
 269         depends on ARC_HAS_DCCM
 270
 271 config ARC_HAS_HW_MPY
 272         bool "Use Hardware Multiplier (Normal or Faster XMAC)"
 273         default y
 274         help
 275           Influences how gcc generates code for MPY operations.
 276           If enabled, MPYxx insns are generated, provided by Standard/XMAC
 277           Multipler. Otherwise software multipy lib is used
 278
 279 choice
 280         prompt "MMU Version"
 281         default ARC_MMU_V3 if ARC_CPU_770
 282         default ARC_MMU_V2 if ARC_CPU_750D
 283         default ARC_MMU_V4 if ARC_CPU_HS
 284
 285 config ARC_MMU_V1
 286         bool "MMU v1"
 287         help
 288           Orig ARC700 MMU
 289
 290 config ARC_MMU_V2
 291         bool "MMU v2"
 292         help
 293           Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
 294           when 2 D-TLB and 1 I-TLB entries index into same 2way set.
 295
 296 config ARC_MMU_V3
 297         bool "MMU v3"
 298         depends on ARC_CPU_770
 299         help
 300           Introduced with ARC700 4.10: New Features
 301           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 302           Shared Address Spaces (SASID)
 303
 304 config ARC_MMU_V4
 305         bool "MMU v4"
 306         depends on ISA_ARCV2
 307
 308 endchoice
 309
 310
 311 choice
 312         prompt "MMU Page Size"
 313         default ARC_PAGE_SIZE_8K
 314
 315 config ARC_PAGE_SIZE_8K
 316         bool "8KB"
 317         help
 318           Choose between 8k vs 16k
 319
 320 config ARC_PAGE_SIZE_16K
 321         bool "16KB"
 322         depends on ARC_MMU_V3 || ARC_MMU_V4
 323
 324 config ARC_PAGE_SIZE_4K
 325         bool "4KB"
 326         depends on ARC_MMU_V3 || ARC_MMU_V4
 327
 328 endchoice
 329
 330 if ISA_ARCOMPACT
 331
 332 config ARC_COMPACT_IRQ_LEVELS
 333         bool "ARCompact IRQ Priorities: High(2)/Low(1)"
 334         default n
 335         # Timer HAS to be high priority, for any other high priority config
 336         select ARC_IRQ3_LV2
 337         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
 338         depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
 339
 340 if ARC_COMPACT_IRQ_LEVELS
 341
 342 config ARC_IRQ3_LV2
 343         bool
 344
 345 config ARC_IRQ5_LV2
 346         bool
 347
 348 config ARC_IRQ6_LV2
 349         bool
 350
 351 endif   #ARC_COMPACT_IRQ_LEVELS
 352
 353 config ARC_FPU_SAVE_RESTORE
 354         bool "Enable FPU state persistence across context switch"
 355         default n
 356         help
 357           Double Precision Floating Point unit had dedictaed regs which
 358           need to be saved/restored across context-switch.
 359           Note that ARC FPU is overly simplistic, unlike say x86, which has
 360           hardware pieces to allow software to conditionally save/restore,
 361           based on actual usage of FPU by a task. Thus our implemn does
 362           this for all tasks in system.
 363
 364 endif   #ISA_ARCOMPACT
 365
 366 config ARC_CANT_LLSC
 367         def_bool n
 368
 369 config ARC_HAS_LLSC
 370         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
 371         default y
 372         depends on !ARC_CANT_LLSC
 373
 374 config ARC_STAR_9000923308
 375         bool "Workaround for llock/scond livelock"
 376         default y
 377         depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
 378
 379 config ARC_HAS_SWAPE
 380         bool "Insn: SWAPE (endian-swap)"
 381         default y
 382
 383 if ISA_ARCV2
 384
 385 config ARC_HAS_LL64
 386         bool "Insn: 64bit LDD/STD"
 387         help
 388           Enable gcc to generate 64-bit load/store instructions
 389           ISA mandates even/odd registers to allow encoding of two
 390           dest operands with 2 possible source operands.
 391         default y
 392
 393 config ARC_HAS_DIV_REM
 394         bool "Insn: div, divu, rem, remu"
 395         default y
 396
 397 config ARC_HAS_RTC
 398         bool "Local 64-bit r/o cycle counter"
 399         default n
 400         depends on !SMP
 401
 402 config ARC_HAS_GRTC
 403         bool "SMP synchronized 64-bit cycle counter"
 404         default y
 405         depends on SMP
 406
 407 config ARC_NUMBER_OF_INTERRUPTS
 408         int "Number of interrupts"
 409         range 8 240
 410         default 32
 411         help
 412           This defines the number of interrupts on the ARCv2HS core.
 413           It affects the size of vector table.
 414           The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
 415           in hardware, it keep things simple for Linux to assume they are always
 416           present.
 417
 418 endif   # ISA_ARCV2
 419
 420 endmenu   # "ARC CPU Configuration"
 421
 422 config LINUX_LINK_BASE
 423         hex "Linux Link Address"
 424         default "0x80000000"
 425         help
 426           ARC700 divides the 32 bit phy address space into two equal halves
 427           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
 428           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
 429           Typically Linux kernel is linked at the start of untransalted addr,
 430           hence the default value of 0x8zs.
 431           However some customers have peripherals mapped at this addr, so
 432           Linux needs to be scooted a bit.
 433           If you don't know what the above means, leave this setting alone.
 434
 435 config ARC_CURR_IN_REG
 436         bool "Dedicate Register r25 for current_task pointer"
 437         default y
 438         help
 439           This reserved Register R25 to point to Current Task in
 440           kernel mode. This saves memory access for each such access
 441
 442
 443 config ARC_EMUL_UNALIGNED
 444         bool "Emulate unaligned memory access (userspace only)"
 445         default N
 446         select SYSCTL_ARCH_UNALIGN_NO_WARN
 447         select SYSCTL_ARCH_UNALIGN_ALLOW
 448         depends on ISA_ARCOMPACT
 449         help
 450           This enables misaligned 16 & 32 bit memory access from user space.
 451           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
 452           potential bugs in code
 453
 454 config HZ
 455         int "Timer Frequency"
 456         default 100
 457
 458 config ARC_METAWARE_HLINK
 459         bool "Support for Metaware debugger assisted Host access"
 460         default n
 461         help
 462           This options allows a Linux userland apps to directly access
 463           host file system (open/creat/read/write etc) with help from
 464           Metaware Debugger. This can come in handy for Linux-host communication
 465           when there is no real usable peripheral such as EMAC.
 466
 467 menuconfig ARC_DBG
 468         bool "ARC debugging"
 469         default y
 470
 471 if ARC_DBG
 472
 473 config ARC_DW2_UNWIND
 474         bool "Enable DWARF specific kernel stack unwind"
 475         default y
 476         select KALLSYMS
 477         help
 478           Compiles the kernel with DWARF unwind information and can be used
 479           to get stack backtraces.
 480
 481           If you say Y here the resulting kernel image will be slightly larger
 482           but not slower, and it will give very useful debugging information.
 483           If you don't debug the kernel, you can say N, but we may not be able
 484           to solve problems without frame unwind information
 485
 486 config ARC_DBG_TLB_PARANOIA
 487         bool "Paranoia Checks in Low Level TLB Handlers"
 488         default n
 489
 490 config ARC_DBG_TLB_MISS_COUNT
 491         bool "Profile TLB Misses"
 492         default n
 493         select DEBUG_FS
 494         help
 495           Counts number of I and D TLB Misses and exports them via Debugfs
 496           The counters can be cleared via Debugfs as well
 497
 498 if SMP
 499
 500 config ARC_IPI_DBG
 501         bool "Debug Inter Core interrupts"
 502         default n
 503
 504 endif
 505
 506 endif
 507
 508 config ARC_UBOOT_SUPPORT
 509         bool "Support uboot arg Handling"
 510         default n
 511         help
 512           ARC Linux by default checks for uboot provided args as pointers to
 513           external cmdline or DTB. This however breaks in absence of uboot,
 514           when booting from Metaware debugger directly, as the registers are
 515           not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
 516           registers look like uboot args to kernel which then chokes.
 517           So only enable the uboot arg checking/processing if users are sure
 518           of uboot being in play.
 519
 520 config ARC_BUILTIN_DTB_NAME
 521         string "Built in DTB"
 522         help
 523           Set the name of the DTB to embed in the vmlinux binary
 524           Leaving it blank selects the minimal "skeleton" dtb
 525
 526 source "kernel/Kconfig.preempt"
 527
 528 menu "Executable file formats"
 529 source "fs/Kconfig.binfmt"
 530 endmenu
 531
 532 endmenu  # "ARC Architecture Configuration"
 533
 534 source "mm/Kconfig"
 535 source "net/Kconfig"
 536 source "drivers/Kconfig"
 537 source "fs/Kconfig"
 538 source "arch/arc/Kconfig.debug"
 539 source "security/Kconfig"
 540 source "crypto/Kconfig"
 541 source "lib/Kconfig"
 542 source "kernel/power/Kconfig"