arch/arc/Kconfig

   1 #
   2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3 #
   4 # This program is free software; you can redistribute it and/or modify
   5 # it under the terms of the GNU General Public License version 2 as
   6 # published by the Free Software Foundation.
   7 #
   8
   9 config ARC
  10         def_bool y
  11         select ARC_TIMERS
  12         select ARCH_HAS_SG_CHAIN
  13         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
  14         select BUILDTIME_EXTABLE_SORT
  15         select CLONE_BACKWARDS
  16         select COMMON_CLK
  17         select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
  18         select GENERIC_CLOCKEVENTS
  19         select GENERIC_FIND_FIRST_BIT
  20         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
  21         select GENERIC_IRQ_SHOW
  22         select GENERIC_PCI_IOMAP
  23         select GENERIC_PENDING_IRQ if SMP
  24         select GENERIC_SMP_IDLE_THREAD
  25         select HAVE_ARCH_KGDB
  26         select HAVE_ARCH_TRACEHOOK
  27         select HAVE_FUTEX_CMPXCHG
  28         select HAVE_IOREMAP_PROT
  29         select HAVE_KPROBES
  30         select HAVE_KRETPROBES
  31         select HAVE_MEMBLOCK
  32         select HAVE_MOD_ARCH_SPECIFIC
  33         select HAVE_OPROFILE
  34         select HAVE_PERF_EVENTS
  35         select HANDLE_DOMAIN_IRQ
  36         select IRQ_DOMAIN
  37         select MODULES_USE_ELF_RELA
  38         select NO_BOOTMEM
  39         select OF
  40         select OF_EARLY_FLATTREE
  41         select OF_RESERVED_MEM
  42         select PERF_USE_VMALLOC
  43         select HAVE_DEBUG_STACKOVERFLOW
  44         select HAVE_GENERIC_DMA_COHERENT
  45         select HAVE_KERNEL_GZIP
  46         select HAVE_KERNEL_LZMA
  47
  48 config MIGHT_HAVE_PCI
  49         bool
  50
  51 config TRACE_IRQFLAGS_SUPPORT
  52         def_bool y
  53
  54 config LOCKDEP_SUPPORT
  55         def_bool y
  56
  57 config SCHED_OMIT_FRAME_POINTER
  58         def_bool y
  59
  60 config GENERIC_CSUM
  61         def_bool y
  62
  63 config RWSEM_GENERIC_SPINLOCK
  64         def_bool y
  65
  66 config ARCH_DISCONTIGMEM_ENABLE
  67         def_bool n
  68
  69 config ARCH_FLATMEM_ENABLE
  70         def_bool y
  71
  72 config MMU
  73         def_bool y
  74
  75 config NO_IOPORT_MAP
  76         def_bool y
  77
  78 config GENERIC_CALIBRATE_DELAY
  79         def_bool y
  80
  81 config GENERIC_HWEIGHT
  82         def_bool y
  83
  84 config STACKTRACE_SUPPORT
  85         def_bool y
  86         select STACKTRACE
  87
  88 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
  89         def_bool y
  90         depends on ARC_MMU_V4
  91
  92 source "init/Kconfig"
  93 source "kernel/Kconfig.freezer"
  94
  95 menu "ARC Architecture Configuration"
  96
  97 menu "ARC Platform/SoC/Board"
  98
  99 source "arch/arc/plat-tb10x/Kconfig"
 100 source "arch/arc/plat-axs10x/Kconfig"
 101 #New platform adds here
 102 source "arch/arc/plat-eznps/Kconfig"
 103
 104 endmenu
 105
 106 choice
 107         prompt "ARC Instruction Set"
 108         default ISA_ARCOMPACT
 109
 110 config ISA_ARCOMPACT
 111         bool "ARCompact ISA"
 112         select CPU_NO_EFFICIENT_FFS
 113         help
 114           The original ARC ISA of ARC600/700 cores
 115
 116 config ISA_ARCV2
 117         bool "ARC ISA v2"
 118         select ARC_TIMERS_64BIT
 119         help
 120           ISA for the Next Generation ARC-HS cores
 121
 122 endchoice
 123
 124 menu "ARC CPU Configuration"
 125
 126 choice
 127         prompt "ARC Core"
 128         default ARC_CPU_770 if ISA_ARCOMPACT
 129         default ARC_CPU_HS if ISA_ARCV2
 130
 131 if ISA_ARCOMPACT
 132
 133 config ARC_CPU_750D
 134         bool "ARC750D"
 135         select ARC_CANT_LLSC
 136         help
 137           Support for ARC750 core
 138
 139 config ARC_CPU_770
 140         bool "ARC770"
 141         select ARC_HAS_SWAPE
 142         help
 143           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
 144           This core has a bunch of cool new features:
 145           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
 146                    Shared Address Spaces (for sharing TLB entires in MMU)
 147           -Caches: New Prog Model, Region Flush
 148           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
 149
 150 endif   #ISA_ARCOMPACT
 151
 152 config ARC_CPU_HS
 153         bool "ARC-HS"
 154         depends on ISA_ARCV2
 155         help
 156           Support for ARC HS38x Cores based on ARCv2 ISA
 157           The notable features are:
 158             - SMP configurations of upto 4 core with coherency
 159             - Optional L2 Cache and IO-Coherency
 160             - Revised Interrupt Architecture (multiple priorites, reg banks,
 161                 auto stack switch, auto regfile save/restore)
 162             - MMUv4 (PIPT dcache, Huge Pages)
 163             - Instructions for
 164                 * 64bit load/store: LDD, STD
 165                 * Hardware assisted divide/remainder: DIV, REM
 166                 * Function prologue/epilogue: ENTER_S, LEAVE_S
 167                 * IRQ enable/disable: CLRI, SETI
 168                 * pop count: FFS, FLS
 169                 * SETcc, BMSKN, XBFU...
 170
 171 endchoice
 172
 173 config CPU_BIG_ENDIAN
 174         bool "Enable Big Endian Mode"
 175         default n
 176         help
 177           Build kernel for Big Endian Mode of ARC CPU
 178
 179 config SMP
 180         bool "Symmetric Multi-Processing"
 181         default n
 182         select ARC_MCIP if ISA_ARCV2
 183         help
 184           This enables support for systems with more than one CPU.
 185
 186 if SMP
 187
 188 config NR_CPUS
 189         int "Maximum number of CPUs (2-4096)"
 190         range 2 4096
 191         default "4"
 192
 193 config ARC_SMP_HALT_ON_RESET
 194         bool "Enable Halt-on-reset boot mode"
 195         default y if ARC_UBOOT_SUPPORT
 196         help
 197           In SMP configuration cores can be configured as Halt-on-reset
 198           or they could all start at same time. For Halt-on-reset, non
 199           masters are parked until Master kicks them so they can start of
 200           at designated entry point. For other case, all jump to common
 201           entry point and spin wait for Master's signal.
 202
 203 endif   #SMP
 204
 205 config ARC_MCIP
 206         bool "ARConnect Multicore IP (MCIP) Support "
 207         depends on ISA_ARCV2
 208         default y if SMP
 209         help
 210           This IP block enables SMP in ARC-HS38 cores.
 211           It provides for cross-core interrupts, multi-core debug
 212           hardware semaphores, shared memory,....
 213
 214 menuconfig ARC_CACHE
 215         bool "Enable Cache Support"
 216         default y
 217
 218 if ARC_CACHE
 219
 220 config ARC_CACHE_LINE_SHIFT
 221         int "Cache Line Length (as power of 2)"
 222         range 5 7
 223         default "6"
 224         help
 225           Starting with ARC700 4.9, Cache line length is configurable,
 226           This option specifies "N", with Line-len = 2 power N
 227           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
 228           Linux only supports same line lengths for I and D caches.
 229
 230 config ARC_HAS_ICACHE
 231         bool "Use Instruction Cache"
 232         default y
 233
 234 config ARC_HAS_DCACHE
 235         bool "Use Data Cache"
 236         default y
 237
 238 config ARC_CACHE_PAGES
 239         bool "Per Page Cache Control"
 240         default y
 241         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
 242         help
 243           This can be used to over-ride the global I/D Cache Enable on a
 244           per-page basis (but only for pages accessed via MMU such as
 245           Kernel Virtual address or User Virtual Address)
 246           TLB entries have a per-page Cache Enable Bit.
 247           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
 248           Global DISABLE + Per Page ENABLE won't work
 249
 250 config ARC_CACHE_VIPT_ALIASING
 251         bool "Support VIPT Aliasing D$"
 252         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
 253         default n
 254
 255 endif   #ARC_CACHE
 256
 257 config ARC_HAS_ICCM
 258         bool "Use ICCM"
 259         help
 260           Single Cycle RAMS to store Fast Path Code
 261         default n
 262
 263 config ARC_ICCM_SZ
 264         int "ICCM Size in KB"
 265         default "64"
 266         depends on ARC_HAS_ICCM
 267
 268 config ARC_HAS_DCCM
 269         bool "Use DCCM"
 270         help
 271           Single Cycle RAMS to store Fast Path Data
 272         default n
 273
 274 config ARC_DCCM_SZ
 275         int "DCCM Size in KB"
 276         default "64"
 277         depends on ARC_HAS_DCCM
 278
 279 config ARC_DCCM_BASE
 280         hex "DCCM map address"
 281         default "0xA0000000"
 282         depends on ARC_HAS_DCCM
 283
 284 choice
 285         prompt "MMU Version"
 286         default ARC_MMU_V3 if ARC_CPU_770
 287         default ARC_MMU_V2 if ARC_CPU_750D
 288         default ARC_MMU_V4 if ARC_CPU_HS
 289
 290 if ISA_ARCOMPACT
 291
 292 config ARC_MMU_V1
 293         bool "MMU v1"
 294         help
 295           Orig ARC700 MMU
 296
 297 config ARC_MMU_V2
 298         bool "MMU v2"
 299         help
 300           Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
 301           when 2 D-TLB and 1 I-TLB entries index into same 2way set.
 302
 303 config ARC_MMU_V3
 304         bool "MMU v3"
 305         depends on ARC_CPU_770
 306         help
 307           Introduced with ARC700 4.10: New Features
 308           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 309           Shared Address Spaces (SASID)
 310
 311 endif
 312
 313 config ARC_MMU_V4
 314         bool "MMU v4"
 315         depends on ISA_ARCV2
 316
 317 endchoice
 318
 319
 320 choice
 321         prompt "MMU Page Size"
 322         default ARC_PAGE_SIZE_8K
 323
 324 config ARC_PAGE_SIZE_8K
 325         bool "8KB"
 326         help
 327           Choose between 8k vs 16k
 328
 329 config ARC_PAGE_SIZE_16K
 330         bool "16KB"
 331         depends on ARC_MMU_V3 || ARC_MMU_V4
 332
 333 config ARC_PAGE_SIZE_4K
 334         bool "4KB"
 335         depends on ARC_MMU_V3 || ARC_MMU_V4
 336
 337 endchoice
 338
 339 choice
 340         prompt "MMU Super Page Size"
 341         depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
 342         default ARC_HUGEPAGE_2M
 343
 344 config ARC_HUGEPAGE_2M
 345         bool "2MB"
 346
 347 config ARC_HUGEPAGE_16M
 348         bool "16MB"
 349
 350 endchoice
 351
 352 config NODES_SHIFT
 353         int "Maximum NUMA Nodes (as a power of 2)"
 354         default "0" if !DISCONTIGMEM
 355         default "1" if DISCONTIGMEM
 356         depends on NEED_MULTIPLE_NODES
 357         ---help---
 358           Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
 359           zones.
 360
 361 if ISA_ARCOMPACT
 362
 363 config ARC_COMPACT_IRQ_LEVELS
 364         bool "Setup Timer IRQ as high Priority"
 365         default n
 366         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
 367         depends on !SMP
 368
 369 config ARC_FPU_SAVE_RESTORE
 370         bool "Enable FPU state persistence across context switch"
 371         default n
 372         help
 373           Double Precision Floating Point unit had dedictaed regs which
 374           need to be saved/restored across context-switch.
 375           Note that ARC FPU is overly simplistic, unlike say x86, which has
 376           hardware pieces to allow software to conditionally save/restore,
 377           based on actual usage of FPU by a task. Thus our implemn does
 378           this for all tasks in system.
 379
 380 endif   #ISA_ARCOMPACT
 381
 382 config ARC_CANT_LLSC
 383         def_bool n
 384
 385 config ARC_HAS_LLSC
 386         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
 387         default y
 388         depends on !ARC_CANT_LLSC
 389
 390 config ARC_HAS_SWAPE
 391         bool "Insn: SWAPE (endian-swap)"
 392         default y
 393
 394 if ISA_ARCV2
 395
 396 config ARC_HAS_LL64
 397         bool "Insn: 64bit LDD/STD"
 398         help
 399           Enable gcc to generate 64-bit load/store instructions
 400           ISA mandates even/odd registers to allow encoding of two
 401           dest operands with 2 possible source operands.
 402         default y
 403
 404 config ARC_HAS_DIV_REM
 405         bool "Insn: div, divu, rem, remu"
 406         default y
 407
 408 config ARC_HAS_ACCL_REGS
 409         bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
 410         default n
 411         help
 412           Depending on the configuration, CPU can contain accumulator reg-pair
 413           (also referred to as r58:r59). These can also be used by gcc as GPR so
 414           kernel needs to save/restore per process
 415
 416 endif   # ISA_ARCV2
 417
 418 endmenu   # "ARC CPU Configuration"
 419
 420 config LINUX_LINK_BASE
 421         hex "Linux Link Address"
 422         default "0x80000000"
 423         help
 424           ARC700 divides the 32 bit phy address space into two equal halves
 425           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
 426           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
 427           Typically Linux kernel is linked at the start of untransalted addr,
 428           hence the default value of 0x8zs.
 429           However some customers have peripherals mapped at this addr, so
 430           Linux needs to be scooted a bit.
 431           If you don't know what the above means, leave this setting alone.
 432           This needs to match memory start address specified in Device Tree
 433
 434 config HIGHMEM
 435         bool "High Memory Support"
 436         select ARCH_DISCONTIGMEM_ENABLE
 437         help
 438           With ARC 2G:2G address split, only upper 2G is directly addressable by
 439           kernel. Enable this to potentially allow access to rest of 2G and PAE
 440           in future
 441
 442 config ARC_HAS_PAE40
 443         bool "Support for the 40-bit Physical Address Extension"
 444         default n
 445         depends on ISA_ARCV2
 446         select HIGHMEM
 447         help
 448           Enable access to physical memory beyond 4G, only supported on
 449           ARC cores with 40 bit Physical Addressing support
 450
 451 config ARCH_PHYS_ADDR_T_64BIT
 452         def_bool ARC_HAS_PAE40
 453
 454 config ARCH_DMA_ADDR_T_64BIT
 455         bool
 456
 457 config ARC_PLAT_NEEDS_PHYS_TO_DMA
 458         bool
 459
 460 config ARC_KVADDR_SIZE
 461         int "Kernel Virtaul Address Space size (MB)"
 462         range 0 512
 463         default "256"
 464         help
 465           The kernel address space is carved out of 256MB of translated address
 466           space for catering to vmalloc, modules, pkmap, fixmap. This however may
 467           not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
 468           this to be stretched to 512 MB (by extending into the reserved
 469           kernel-user gutter)
 470
 471 config ARC_CURR_IN_REG
 472         bool "Dedicate Register r25 for current_task pointer"
 473         default y
 474         help
 475           This reserved Register R25 to point to Current Task in
 476           kernel mode. This saves memory access for each such access
 477
 478
 479 config ARC_EMUL_UNALIGNED
 480         bool "Emulate unaligned memory access (userspace only)"
 481         default N
 482         select SYSCTL_ARCH_UNALIGN_NO_WARN
 483         select SYSCTL_ARCH_UNALIGN_ALLOW
 484         depends on ISA_ARCOMPACT
 485         help
 486           This enables misaligned 16 & 32 bit memory access from user space.
 487           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
 488           potential bugs in code
 489
 490 config HZ
 491         int "Timer Frequency"
 492         default 100
 493
 494 config ARC_METAWARE_HLINK
 495         bool "Support for Metaware debugger assisted Host access"
 496         default n
 497         help
 498           This options allows a Linux userland apps to directly access
 499           host file system (open/creat/read/write etc) with help from
 500           Metaware Debugger. This can come in handy for Linux-host communication
 501           when there is no real usable peripheral such as EMAC.
 502
 503 menuconfig ARC_DBG
 504         bool "ARC debugging"
 505         default y
 506
 507 if ARC_DBG
 508
 509 config ARC_DW2_UNWIND
 510         bool "Enable DWARF specific kernel stack unwind"
 511         default y
 512         select KALLSYMS
 513         help
 514           Compiles the kernel with DWARF unwind information and can be used
 515           to get stack backtraces.
 516
 517           If you say Y here the resulting kernel image will be slightly larger
 518           but not slower, and it will give very useful debugging information.
 519           If you don't debug the kernel, you can say N, but we may not be able
 520           to solve problems without frame unwind information
 521
 522 config ARC_DBG_TLB_PARANOIA
 523         bool "Paranoia Checks in Low Level TLB Handlers"
 524         default n
 525
 526 endif
 527
 528 config ARC_UBOOT_SUPPORT
 529         bool "Support uboot arg Handling"
 530         default n
 531         help
 532           ARC Linux by default checks for uboot provided args as pointers to
 533           external cmdline or DTB. This however breaks in absence of uboot,
 534           when booting from Metaware debugger directly, as the registers are
 535           not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
 536           registers look like uboot args to kernel which then chokes.
 537           So only enable the uboot arg checking/processing if users are sure
 538           of uboot being in play.
 539
 540 config ARC_BUILTIN_DTB_NAME
 541         string "Built in DTB"
 542         help
 543           Set the name of the DTB to embed in the vmlinux binary
 544           Leaving it blank selects the minimal "skeleton" dtb
 545
 546 source "kernel/Kconfig.preempt"
 547
 548 menu "Executable file formats"
 549 source "fs/Kconfig.binfmt"
 550 endmenu
 551
 552 endmenu  # "ARC Architecture Configuration"
 553
 554 source "mm/Kconfig"
 555
 556 config FORCE_MAX_ZONEORDER
 557         int "Maximum zone order"
 558         default "12" if ARC_HUGEPAGE_16M
 559         default "11"
 560
 561 source "net/Kconfig"
 562 source "drivers/Kconfig"
 563
 564 menu "Bus Support"
 565
 566 config PCI
 567         bool "PCI support" if MIGHT_HAVE_PCI
 568         help
 569           PCI is the name of a bus system, i.e., the way the CPU talks to
 570           the other stuff inside your box.  Find out if your board/platform
 571           has PCI.
 572
 573           Note: PCIe support for Synopsys Device will be available only
 574           when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
 575           say Y, otherwise N.
 576
 577 config PCI_SYSCALL
 578         def_bool PCI
 579
 580 source "drivers/pci/Kconfig"
 581
 582 endmenu
 583
 584 source "fs/Kconfig"
 585 source "arch/arc/Kconfig.debug"
 586 source "security/Kconfig"
 587 source "crypto/Kconfig"
 588 source "lib/Kconfig"
 589 source "kernel/power/Kconfig"