arch/arc/Kconfig

   1 #
   2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3 #
   4 # This program is free software; you can redistribute it and/or modify
   5 # it under the terms of the GNU General Public License version 2 as
   6 # published by the Free Software Foundation.
   7 #
   8
   9 config ARC
  10         def_bool y
  11         select ARC_TIMERS
  12         select ARCH_HAS_SG_CHAIN
  13         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
  14         select BUILDTIME_EXTABLE_SORT
  15         select CLONE_BACKWARDS
  16         select COMMON_CLK
  17         select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
  18         select GENERIC_CLOCKEVENTS
  19         select GENERIC_FIND_FIRST_BIT
  20         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
  21         select GENERIC_IRQ_SHOW
  22         select GENERIC_PCI_IOMAP
  23         select GENERIC_PENDING_IRQ if SMP
  24         select GENERIC_SMP_IDLE_THREAD
  25         select HAVE_ARCH_KGDB
  26         select HAVE_ARCH_TRACEHOOK
  27         select HAVE_FUTEX_CMPXCHG
  28         select HAVE_IOREMAP_PROT
  29         select HAVE_KPROBES
  30         select HAVE_KRETPROBES
  31         select HAVE_MEMBLOCK
  32         select HAVE_MOD_ARCH_SPECIFIC
  33         select HAVE_OPROFILE
  34         select HAVE_PERF_EVENTS
  35         select HANDLE_DOMAIN_IRQ
  36         select IRQ_DOMAIN
  37         select MODULES_USE_ELF_RELA
  38         select NO_BOOTMEM
  39         select OF
  40         select OF_EARLY_FLATTREE
  41         select OF_RESERVED_MEM
  42         select PERF_USE_VMALLOC
  43         select HAVE_DEBUG_STACKOVERFLOW
  44         select HAVE_GENERIC_DMA_COHERENT
  45         select HAVE_KERNEL_GZIP
  46         select HAVE_KERNEL_LZMA
  47
  48 config MIGHT_HAVE_PCI
  49         bool
  50
  51 config TRACE_IRQFLAGS_SUPPORT
  52         def_bool y
  53
  54 config LOCKDEP_SUPPORT
  55         def_bool y
  56
  57 config SCHED_OMIT_FRAME_POINTER
  58         def_bool y
  59
  60 config GENERIC_CSUM
  61         def_bool y
  62
  63 config RWSEM_GENERIC_SPINLOCK
  64         def_bool y
  65
  66 config ARCH_DISCONTIGMEM_ENABLE
  67         def_bool n
  68
  69 config ARCH_FLATMEM_ENABLE
  70         def_bool y
  71
  72 config MMU
  73         def_bool y
  74
  75 config NO_IOPORT_MAP
  76         def_bool y
  77
  78 config GENERIC_CALIBRATE_DELAY
  79         def_bool y
  80
  81 config GENERIC_HWEIGHT
  82         def_bool y
  83
  84 config STACKTRACE_SUPPORT
  85         def_bool y
  86         select STACKTRACE
  87
  88 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
  89         def_bool y
  90         depends on ARC_MMU_V4
  91
  92 source "init/Kconfig"
  93 source "kernel/Kconfig.freezer"
  94
  95 menu "ARC Architecture Configuration"
  96
  97 menu "ARC Platform/SoC/Board"
  98
  99 source "arch/arc/plat-sim/Kconfig"
 100 source "arch/arc/plat-tb10x/Kconfig"
 101 source "arch/arc/plat-axs10x/Kconfig"
 102 #New platform adds here
 103 source "arch/arc/plat-eznps/Kconfig"
 104
 105 endmenu
 106
 107 choice
 108         prompt "ARC Instruction Set"
 109         default ISA_ARCOMPACT
 110
 111 config ISA_ARCOMPACT
 112         bool "ARCompact ISA"
 113         select CPU_NO_EFFICIENT_FFS
 114         help
 115           The original ARC ISA of ARC600/700 cores
 116
 117 config ISA_ARCV2
 118         bool "ARC ISA v2"
 119         select ARC_TIMERS_64BIT
 120         help
 121           ISA for the Next Generation ARC-HS cores
 122
 123 endchoice
 124
 125 menu "ARC CPU Configuration"
 126
 127 choice
 128         prompt "ARC Core"
 129         default ARC_CPU_770 if ISA_ARCOMPACT
 130         default ARC_CPU_HS if ISA_ARCV2
 131
 132 if ISA_ARCOMPACT
 133
 134 config ARC_CPU_750D
 135         bool "ARC750D"
 136         select ARC_CANT_LLSC
 137         help
 138           Support for ARC750 core
 139
 140 config ARC_CPU_770
 141         bool "ARC770"
 142         select ARC_HAS_SWAPE
 143         help
 144           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
 145           This core has a bunch of cool new features:
 146           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
 147                    Shared Address Spaces (for sharing TLB entires in MMU)
 148           -Caches: New Prog Model, Region Flush
 149           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
 150
 151 endif   #ISA_ARCOMPACT
 152
 153 config ARC_CPU_HS
 154         bool "ARC-HS"
 155         depends on ISA_ARCV2
 156         help
 157           Support for ARC HS38x Cores based on ARCv2 ISA
 158           The notable features are:
 159             - SMP configurations of upto 4 core with coherency
 160             - Optional L2 Cache and IO-Coherency
 161             - Revised Interrupt Architecture (multiple priorites, reg banks,
 162                 auto stack switch, auto regfile save/restore)
 163             - MMUv4 (PIPT dcache, Huge Pages)
 164             - Instructions for
 165                 * 64bit load/store: LDD, STD
 166                 * Hardware assisted divide/remainder: DIV, REM
 167                 * Function prologue/epilogue: ENTER_S, LEAVE_S
 168                 * IRQ enable/disable: CLRI, SETI
 169                 * pop count: FFS, FLS
 170                 * SETcc, BMSKN, XBFU...
 171
 172 endchoice
 173
 174 config CPU_BIG_ENDIAN
 175         bool "Enable Big Endian Mode"
 176         default n
 177         help
 178           Build kernel for Big Endian Mode of ARC CPU
 179
 180 config SMP
 181         bool "Symmetric Multi-Processing"
 182         default n
 183         select ARC_MCIP if ISA_ARCV2
 184         help
 185           This enables support for systems with more than one CPU.
 186
 187 if SMP
 188
 189 config NR_CPUS
 190         int "Maximum number of CPUs (2-4096)"
 191         range 2 4096
 192         default "4"
 193
 194 config ARC_SMP_HALT_ON_RESET
 195         bool "Enable Halt-on-reset boot mode"
 196         default y if ARC_UBOOT_SUPPORT
 197         help
 198           In SMP configuration cores can be configured as Halt-on-reset
 199           or they could all start at same time. For Halt-on-reset, non
 200           masters are parked until Master kicks them so they can start of
 201           at designated entry point. For other case, all jump to common
 202           entry point and spin wait for Master's signal.
 203
 204 endif   #SMP
 205
 206 config ARC_MCIP
 207         bool "ARConnect Multicore IP (MCIP) Support "
 208         depends on ISA_ARCV2
 209         default y if SMP
 210         help
 211           This IP block enables SMP in ARC-HS38 cores.
 212           It provides for cross-core interrupts, multi-core debug
 213           hardware semaphores, shared memory,....
 214
 215 menuconfig ARC_CACHE
 216         bool "Enable Cache Support"
 217         default y
 218
 219 if ARC_CACHE
 220
 221 config ARC_CACHE_LINE_SHIFT
 222         int "Cache Line Length (as power of 2)"
 223         range 5 7
 224         default "6"
 225         help
 226           Starting with ARC700 4.9, Cache line length is configurable,
 227           This option specifies "N", with Line-len = 2 power N
 228           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
 229           Linux only supports same line lengths for I and D caches.
 230
 231 config ARC_HAS_ICACHE
 232         bool "Use Instruction Cache"
 233         default y
 234
 235 config ARC_HAS_DCACHE
 236         bool "Use Data Cache"
 237         default y
 238
 239 config ARC_CACHE_PAGES
 240         bool "Per Page Cache Control"
 241         default y
 242         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
 243         help
 244           This can be used to over-ride the global I/D Cache Enable on a
 245           per-page basis (but only for pages accessed via MMU such as
 246           Kernel Virtual address or User Virtual Address)
 247           TLB entries have a per-page Cache Enable Bit.
 248           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
 249           Global DISABLE + Per Page ENABLE won't work
 250
 251 config ARC_CACHE_VIPT_ALIASING
 252         bool "Support VIPT Aliasing D$"
 253         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
 254         default n
 255
 256 endif   #ARC_CACHE
 257
 258 config ARC_HAS_ICCM
 259         bool "Use ICCM"
 260         help
 261           Single Cycle RAMS to store Fast Path Code
 262         default n
 263
 264 config ARC_ICCM_SZ
 265         int "ICCM Size in KB"
 266         default "64"
 267         depends on ARC_HAS_ICCM
 268
 269 config ARC_HAS_DCCM
 270         bool "Use DCCM"
 271         help
 272           Single Cycle RAMS to store Fast Path Data
 273         default n
 274
 275 config ARC_DCCM_SZ
 276         int "DCCM Size in KB"
 277         default "64"
 278         depends on ARC_HAS_DCCM
 279
 280 config ARC_DCCM_BASE
 281         hex "DCCM map address"
 282         default "0xA0000000"
 283         depends on ARC_HAS_DCCM
 284
 285 choice
 286         prompt "MMU Version"
 287         default ARC_MMU_V3 if ARC_CPU_770
 288         default ARC_MMU_V2 if ARC_CPU_750D
 289         default ARC_MMU_V4 if ARC_CPU_HS
 290
 291 if ISA_ARCOMPACT
 292
 293 config ARC_MMU_V1
 294         bool "MMU v1"
 295         help
 296           Orig ARC700 MMU
 297
 298 config ARC_MMU_V2
 299         bool "MMU v2"
 300         help
 301           Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
 302           when 2 D-TLB and 1 I-TLB entries index into same 2way set.
 303
 304 config ARC_MMU_V3
 305         bool "MMU v3"
 306         depends on ARC_CPU_770
 307         help
 308           Introduced with ARC700 4.10: New Features
 309           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 310           Shared Address Spaces (SASID)
 311
 312 endif
 313
 314 config ARC_MMU_V4
 315         bool "MMU v4"
 316         depends on ISA_ARCV2
 317
 318 endchoice
 319
 320
 321 choice
 322         prompt "MMU Page Size"
 323         default ARC_PAGE_SIZE_8K
 324
 325 config ARC_PAGE_SIZE_8K
 326         bool "8KB"
 327         help
 328           Choose between 8k vs 16k
 329
 330 config ARC_PAGE_SIZE_16K
 331         bool "16KB"
 332         depends on ARC_MMU_V3 || ARC_MMU_V4
 333
 334 config ARC_PAGE_SIZE_4K
 335         bool "4KB"
 336         depends on ARC_MMU_V3 || ARC_MMU_V4
 337
 338 endchoice
 339
 340 choice
 341         prompt "MMU Super Page Size"
 342         depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
 343         default ARC_HUGEPAGE_2M
 344
 345 config ARC_HUGEPAGE_2M
 346         bool "2MB"
 347
 348 config ARC_HUGEPAGE_16M
 349         bool "16MB"
 350
 351 endchoice
 352
 353 config NODES_SHIFT
 354         int "Maximum NUMA Nodes (as a power of 2)"
 355         default "0" if !DISCONTIGMEM
 356         default "1" if DISCONTIGMEM
 357         depends on NEED_MULTIPLE_NODES
 358         ---help---
 359           Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
 360           zones.
 361
 362 if ISA_ARCOMPACT
 363
 364 config ARC_COMPACT_IRQ_LEVELS
 365         bool "Setup Timer IRQ as high Priority"
 366         default n
 367         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
 368         depends on !SMP
 369
 370 config ARC_FPU_SAVE_RESTORE
 371         bool "Enable FPU state persistence across context switch"
 372         default n
 373         help
 374           Double Precision Floating Point unit had dedictaed regs which
 375           need to be saved/restored across context-switch.
 376           Note that ARC FPU is overly simplistic, unlike say x86, which has
 377           hardware pieces to allow software to conditionally save/restore,
 378           based on actual usage of FPU by a task. Thus our implemn does
 379           this for all tasks in system.
 380
 381 endif   #ISA_ARCOMPACT
 382
 383 config ARC_CANT_LLSC
 384         def_bool n
 385
 386 config ARC_HAS_LLSC
 387         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
 388         default y
 389         depends on !ARC_CANT_LLSC
 390
 391 config ARC_HAS_SWAPE
 392         bool "Insn: SWAPE (endian-swap)"
 393         default y
 394
 395 if ISA_ARCV2
 396
 397 config ARC_HAS_LL64
 398         bool "Insn: 64bit LDD/STD"
 399         help
 400           Enable gcc to generate 64-bit load/store instructions
 401           ISA mandates even/odd registers to allow encoding of two
 402           dest operands with 2 possible source operands.
 403         default y
 404
 405 config ARC_HAS_DIV_REM
 406         bool "Insn: div, divu, rem, remu"
 407         default y
 408
 409 config ARC_HAS_ACCL_REGS
 410         bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
 411         default n
 412         help
 413           Depending on the configuration, CPU can contain accumulator reg-pair
 414           (also referred to as r58:r59). These can also be used by gcc as GPR so
 415           kernel needs to save/restore per process
 416
 417 endif   # ISA_ARCV2
 418
 419 endmenu   # "ARC CPU Configuration"
 420
 421 config LINUX_LINK_BASE
 422         hex "Linux Link Address"
 423         default "0x80000000"
 424         help
 425           ARC700 divides the 32 bit phy address space into two equal halves
 426           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
 427           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
 428           Typically Linux kernel is linked at the start of untransalted addr,
 429           hence the default value of 0x8zs.
 430           However some customers have peripherals mapped at this addr, so
 431           Linux needs to be scooted a bit.
 432           If you don't know what the above means, leave this setting alone.
 433           This needs to match memory start address specified in Device Tree
 434
 435 config HIGHMEM
 436         bool "High Memory Support"
 437         select ARCH_DISCONTIGMEM_ENABLE
 438         help
 439           With ARC 2G:2G address split, only upper 2G is directly addressable by
 440           kernel. Enable this to potentially allow access to rest of 2G and PAE
 441           in future
 442
 443 config ARC_HAS_PAE40
 444         bool "Support for the 40-bit Physical Address Extension"
 445         default n
 446         depends on ISA_ARCV2
 447         select HIGHMEM
 448         help
 449           Enable access to physical memory beyond 4G, only supported on
 450           ARC cores with 40 bit Physical Addressing support
 451
 452 config ARCH_PHYS_ADDR_T_64BIT
 453         def_bool ARC_HAS_PAE40
 454
 455 config ARCH_DMA_ADDR_T_64BIT
 456         bool
 457
 458 config ARC_PLAT_NEEDS_PHYS_TO_DMA
 459         bool
 460
 461 config ARC_KVADDR_SIZE
 462         int "Kernel Virtaul Address Space size (MB)"
 463         range 0 512
 464         default "256"
 465         help
 466           The kernel address space is carved out of 256MB of translated address
 467           space for catering to vmalloc, modules, pkmap, fixmap. This however may
 468           not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
 469           this to be stretched to 512 MB (by extending into the reserved
 470           kernel-user gutter)
 471
 472 config ARC_CURR_IN_REG
 473         bool "Dedicate Register r25 for current_task pointer"
 474         default y
 475         help
 476           This reserved Register R25 to point to Current Task in
 477           kernel mode. This saves memory access for each such access
 478
 479
 480 config ARC_EMUL_UNALIGNED
 481         bool "Emulate unaligned memory access (userspace only)"
 482         default N
 483         select SYSCTL_ARCH_UNALIGN_NO_WARN
 484         select SYSCTL_ARCH_UNALIGN_ALLOW
 485         depends on ISA_ARCOMPACT
 486         help
 487           This enables misaligned 16 & 32 bit memory access from user space.
 488           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
 489           potential bugs in code
 490
 491 config HZ
 492         int "Timer Frequency"
 493         default 100
 494
 495 config ARC_METAWARE_HLINK
 496         bool "Support for Metaware debugger assisted Host access"
 497         default n
 498         help
 499           This options allows a Linux userland apps to directly access
 500           host file system (open/creat/read/write etc) with help from
 501           Metaware Debugger. This can come in handy for Linux-host communication
 502           when there is no real usable peripheral such as EMAC.
 503
 504 menuconfig ARC_DBG
 505         bool "ARC debugging"
 506         default y
 507
 508 if ARC_DBG
 509
 510 config ARC_DW2_UNWIND
 511         bool "Enable DWARF specific kernel stack unwind"
 512         default y
 513         select KALLSYMS
 514         help
 515           Compiles the kernel with DWARF unwind information and can be used
 516           to get stack backtraces.
 517
 518           If you say Y here the resulting kernel image will be slightly larger
 519           but not slower, and it will give very useful debugging information.
 520           If you don't debug the kernel, you can say N, but we may not be able
 521           to solve problems without frame unwind information
 522
 523 config ARC_DBG_TLB_PARANOIA
 524         bool "Paranoia Checks in Low Level TLB Handlers"
 525         default n
 526
 527 endif
 528
 529 config ARC_UBOOT_SUPPORT
 530         bool "Support uboot arg Handling"
 531         default n
 532         help
 533           ARC Linux by default checks for uboot provided args as pointers to
 534           external cmdline or DTB. This however breaks in absence of uboot,
 535           when booting from Metaware debugger directly, as the registers are
 536           not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
 537           registers look like uboot args to kernel which then chokes.
 538           So only enable the uboot arg checking/processing if users are sure
 539           of uboot being in play.
 540
 541 config ARC_BUILTIN_DTB_NAME
 542         string "Built in DTB"
 543         help
 544           Set the name of the DTB to embed in the vmlinux binary
 545           Leaving it blank selects the minimal "skeleton" dtb
 546
 547 source "kernel/Kconfig.preempt"
 548
 549 menu "Executable file formats"
 550 source "fs/Kconfig.binfmt"
 551 endmenu
 552
 553 endmenu  # "ARC Architecture Configuration"
 554
 555 source "mm/Kconfig"
 556
 557 config FORCE_MAX_ZONEORDER
 558         int "Maximum zone order"
 559         default "12" if ARC_HUGEPAGE_16M
 560         default "11"
 561
 562 source "net/Kconfig"
 563 source "drivers/Kconfig"
 564
 565 menu "Bus Support"
 566
 567 config PCI
 568         bool "PCI support" if MIGHT_HAVE_PCI
 569         help
 570           PCI is the name of a bus system, i.e., the way the CPU talks to
 571           the other stuff inside your box.  Find out if your board/platform
 572           has PCI.
 573
 574           Note: PCIe support for Synopsys Device will be available only
 575           when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
 576           say Y, otherwise N.
 577
 578 config PCI_SYSCALL
 579         def_bool PCI
 580
 581 source "drivers/pci/Kconfig"
 582
 583 endmenu
 584
 585 source "fs/Kconfig"
 586 source "arch/arc/Kconfig.debug"
 587 source "security/Kconfig"
 588 source "crypto/Kconfig"
 589 source "lib/Kconfig"
 590 source "kernel/power/Kconfig"