2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12 select BUILDTIME_EXTABLE_SORT
14 select CLONE_BACKWARDS
15 select GENERIC_ATOMIC64
16 select GENERIC_CLOCKEVENTS
17 select GENERIC_FIND_FIRST_BIT
18 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_PENDING_IRQ if SMP
22 select GENERIC_SMP_IDLE_THREAD
24 select HAVE_ARCH_TRACEHOOK
25 select HAVE_FUTEX_CMPXCHG
26 select HAVE_IOREMAP_PROT
28 select HAVE_KRETPROBES
30 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
32 select HAVE_PERF_EVENTS
34 select MODULES_USE_ELF_RELA
37 select OF_EARLY_FLATTREE
38 select OF_RESERVED_MEM
39 select PERF_USE_VMALLOC
40 select HAVE_DEBUG_STACKOVERFLOW
41 select HAVE_GENERIC_DMA_COHERENT
46 config TRACE_IRQFLAGS_SUPPORT
49 config LOCKDEP_SUPPORT
52 config SCHED_OMIT_FRAME_POINTER
58 config RWSEM_GENERIC_SPINLOCK
61 config ARCH_DISCONTIGMEM_ENABLE
64 config ARCH_FLATMEM_ENABLE
73 config GENERIC_CALIBRATE_DELAY
76 config GENERIC_HWEIGHT
79 config STACKTRACE_SUPPORT
83 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
88 source "kernel/Kconfig.freezer"
90 menu "ARC Architecture Configuration"
92 menu "ARC Platform/SoC/Board"
94 source "arch/arc/plat-sim/Kconfig"
95 source "arch/arc/plat-tb10x/Kconfig"
96 source "arch/arc/plat-axs10x/Kconfig"
97 #New platform adds here
102 prompt "ARC Instruction Set"
103 default ISA_ARCOMPACT
108 The original ARC ISA of ARC600/700 cores
113 ISA for the Next Generation ARC-HS cores
117 menu "ARC CPU Configuration"
121 default ARC_CPU_770 if ISA_ARCOMPACT
122 default ARC_CPU_HS if ISA_ARCV2
130 Support for ARC750 core
136 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
137 This core has a bunch of cool new features:
138 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
139 Shared Address Spaces (for sharing TLB entires in MMU)
140 -Caches: New Prog Model, Region Flush
141 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
149 Support for ARC HS38x Cores based on ARCv2 ISA
150 The notable features are:
151 - SMP configurations of upto 4 core with coherency
152 - Optional L2 Cache and IO-Coherency
153 - Revised Interrupt Architecture (multiple priorites, reg banks,
154 auto stack switch, auto regfile save/restore)
155 - MMUv4 (PIPT dcache, Huge Pages)
157 * 64bit load/store: LDD, STD
158 * Hardware assisted divide/remainder: DIV, REM
159 * Function prologue/epilogue: ENTER_S, LEAVE_S
160 * IRQ enable/disable: CLRI, SETI
161 * pop count: FFS, FLS
162 * SETcc, BMSKN, XBFU...
166 config CPU_BIG_ENDIAN
167 bool "Enable Big Endian Mode"
170 Build kernel for Big Endian Mode of ARC CPU
173 bool "Symmetric Multi-Processing"
175 select ARC_HAS_COH_CACHES if ISA_ARCV2
176 select ARC_MCIP if ISA_ARCV2
178 This enables support for systems with more than one CPU.
182 config ARC_HAS_COH_CACHES
185 config ARC_HAS_REENTRANT_IRQ_LV2
189 bool "ARConnect Multicore IP (MCIP) Support "
192 This IP block enables SMP in ARC-HS38 cores.
193 It provides for cross-core interrupts, multi-core debug
194 hardware semaphores, shared memory,....
197 int "Maximum number of CPUs (2-4096)"
201 config ARC_SMP_HALT_ON_RESET
202 bool "Enable Halt-on-reset boot mode"
203 default y if ARC_UBOOT_SUPPORT
205 In SMP configuration cores can be configured as Halt-on-reset
206 or they could all start at same time. For Halt-on-reset, non
207 masters are parked until Master kicks them so they can start of
208 at designated entry point. For other case, all jump to common
209 entry point and spin wait for Master's signal.
214 bool "Enable Cache Support"
216 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
217 depends on !SMP || ARC_HAS_COH_CACHES
221 config ARC_CACHE_LINE_SHIFT
222 int "Cache Line Length (as power of 2)"
226 Starting with ARC700 4.9, Cache line length is configurable,
227 This option specifies "N", with Line-len = 2 power N
228 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
229 Linux only supports same line lengths for I and D caches.
231 config ARC_HAS_ICACHE
232 bool "Use Instruction Cache"
235 config ARC_HAS_DCACHE
236 bool "Use Data Cache"
239 config ARC_CACHE_PAGES
240 bool "Per Page Cache Control"
242 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
244 This can be used to over-ride the global I/D Cache Enable on a
245 per-page basis (but only for pages accessed via MMU such as
246 Kernel Virtual address or User Virtual Address)
247 TLB entries have a per-page Cache Enable Bit.
248 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
249 Global DISABLE + Per Page ENABLE won't work
251 config ARC_CACHE_VIPT_ALIASING
252 bool "Support VIPT Aliasing D$"
253 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
261 Single Cycle RAMS to store Fast Path Code
265 int "ICCM Size in KB"
267 depends on ARC_HAS_ICCM
272 Single Cycle RAMS to store Fast Path Data
276 int "DCCM Size in KB"
278 depends on ARC_HAS_DCCM
281 hex "DCCM map address"
283 depends on ARC_HAS_DCCM
287 default ARC_MMU_V3 if ARC_CPU_770
288 default ARC_MMU_V2 if ARC_CPU_750D
289 default ARC_MMU_V4 if ARC_CPU_HS
301 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
302 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
306 depends on ARC_CPU_770
308 Introduced with ARC700 4.10: New Features
309 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
310 Shared Address Spaces (SASID)
322 prompt "MMU Page Size"
323 default ARC_PAGE_SIZE_8K
325 config ARC_PAGE_SIZE_8K
328 Choose between 8k vs 16k
330 config ARC_PAGE_SIZE_16K
332 depends on ARC_MMU_V3 || ARC_MMU_V4
334 config ARC_PAGE_SIZE_4K
336 depends on ARC_MMU_V3 || ARC_MMU_V4
341 prompt "MMU Super Page Size"
342 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
343 default ARC_HUGEPAGE_2M
345 config ARC_HUGEPAGE_2M
348 config ARC_HUGEPAGE_16M
354 int "Maximum NUMA Nodes (as a power of 2)"
355 default "1" if !DISCONTIGMEM
356 default "2" if DISCONTIGMEM
357 depends on NEED_MULTIPLE_NODES
359 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
364 config ARC_COMPACT_IRQ_LEVELS
365 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
367 # Timer HAS to be high priority, for any other high priority config
369 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
370 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
372 if ARC_COMPACT_IRQ_LEVELS
383 endif #ARC_COMPACT_IRQ_LEVELS
385 config ARC_FPU_SAVE_RESTORE
386 bool "Enable FPU state persistence across context switch"
389 Double Precision Floating Point unit had dedictaed regs which
390 need to be saved/restored across context-switch.
391 Note that ARC FPU is overly simplistic, unlike say x86, which has
392 hardware pieces to allow software to conditionally save/restore,
393 based on actual usage of FPU by a task. Thus our implemn does
394 this for all tasks in system.
402 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
404 depends on !ARC_CANT_LLSC
406 config ARC_STAR_9000923308
407 bool "Workaround for llock/scond livelock"
409 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
412 bool "Insn: SWAPE (endian-swap)"
418 bool "Insn: 64bit LDD/STD"
420 Enable gcc to generate 64-bit load/store instructions
421 ISA mandates even/odd registers to allow encoding of two
422 dest operands with 2 possible source operands.
425 config ARC_HAS_DIV_REM
426 bool "Insn: div, divu, rem, remu"
430 bool "Local 64-bit r/o cycle counter"
435 bool "SMP synchronized 64-bit cycle counter"
439 config ARC_NUMBER_OF_INTERRUPTS
440 int "Number of interrupts"
444 This defines the number of interrupts on the ARCv2HS core.
445 It affects the size of vector table.
446 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
447 in hardware, it keep things simple for Linux to assume they are always
452 endmenu # "ARC CPU Configuration"
454 config LINUX_LINK_BASE
455 hex "Linux Link Address"
458 ARC700 divides the 32 bit phy address space into two equal halves
459 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
460 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
461 Typically Linux kernel is linked at the start of untransalted addr,
462 hence the default value of 0x8zs.
463 However some customers have peripherals mapped at this addr, so
464 Linux needs to be scooted a bit.
465 If you don't know what the above means, leave this setting alone.
466 This needs to match memory start address specified in Device Tree
469 bool "High Memory Support"
472 With ARC 2G:2G address split, only upper 2G is directly addressable by
473 kernel. Enable this to potentially allow access to rest of 2G and PAE
477 bool "Support for the 40-bit Physical Address Extension"
481 Enable access to physical memory beyond 4G, only supported on
482 ARC cores with 40 bit Physical Addressing support
484 config ARCH_PHYS_ADDR_T_64BIT
485 def_bool ARC_HAS_PAE40
487 config ARCH_DMA_ADDR_T_64BIT
490 config ARC_PLAT_NEEDS_PHYS_TO_DMA
493 config ARC_CURR_IN_REG
494 bool "Dedicate Register r25 for current_task pointer"
497 This reserved Register R25 to point to Current Task in
498 kernel mode. This saves memory access for each such access
501 config ARC_EMUL_UNALIGNED
502 bool "Emulate unaligned memory access (userspace only)"
504 select SYSCTL_ARCH_UNALIGN_NO_WARN
505 select SYSCTL_ARCH_UNALIGN_ALLOW
506 depends on ISA_ARCOMPACT
508 This enables misaligned 16 & 32 bit memory access from user space.
509 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
510 potential bugs in code
513 int "Timer Frequency"
516 config ARC_METAWARE_HLINK
517 bool "Support for Metaware debugger assisted Host access"
520 This options allows a Linux userland apps to directly access
521 host file system (open/creat/read/write etc) with help from
522 Metaware Debugger. This can come in handy for Linux-host communication
523 when there is no real usable peripheral such as EMAC.
531 config ARC_DW2_UNWIND
532 bool "Enable DWARF specific kernel stack unwind"
536 Compiles the kernel with DWARF unwind information and can be used
537 to get stack backtraces.
539 If you say Y here the resulting kernel image will be slightly larger
540 but not slower, and it will give very useful debugging information.
541 If you don't debug the kernel, you can say N, but we may not be able
542 to solve problems without frame unwind information
544 config ARC_DBG_TLB_PARANOIA
545 bool "Paranoia Checks in Low Level TLB Handlers"
548 config ARC_DBG_TLB_MISS_COUNT
549 bool "Profile TLB Misses"
553 Counts number of I and D TLB Misses and exports them via Debugfs
554 The counters can be cleared via Debugfs as well
558 config ARC_UBOOT_SUPPORT
559 bool "Support uboot arg Handling"
562 ARC Linux by default checks for uboot provided args as pointers to
563 external cmdline or DTB. This however breaks in absence of uboot,
564 when booting from Metaware debugger directly, as the registers are
565 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
566 registers look like uboot args to kernel which then chokes.
567 So only enable the uboot arg checking/processing if users are sure
568 of uboot being in play.
570 config ARC_BUILTIN_DTB_NAME
571 string "Built in DTB"
573 Set the name of the DTB to embed in the vmlinux binary
574 Leaving it blank selects the minimal "skeleton" dtb
576 source "kernel/Kconfig.preempt"
578 menu "Executable file formats"
579 source "fs/Kconfig.binfmt"
582 endmenu # "ARC Architecture Configuration"
586 config FORCE_MAX_ZONEORDER
587 int "Maximum zone order"
588 default "12" if ARC_HUGEPAGE_16M
592 source "drivers/Kconfig"
597 bool "PCI support" if MIGHT_HAVE_PCI
599 PCI is the name of a bus system, i.e., the way the CPU talks to
600 the other stuff inside your box. Find out if your board/platform
603 Note: PCIe support for Synopsys Device will be available only
604 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
610 source "drivers/pci/Kconfig"
615 source "arch/arc/Kconfig.debug"
616 source "security/Kconfig"
617 source "crypto/Kconfig"
619 source "kernel/power/Kconfig"