arch/arc/include/asm/arcregs.h

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef _ASM_ARC_ARCREGS_H
  10 #define _ASM_ARC_ARCREGS_H
  11
  12 #ifdef __KERNEL__
  13
  14 /* Build Configuration Registers */
  15 #define ARC_REG_DCCMBASE_BCR    0x61    /* DCCM Base Addr */
  16 #define ARC_REG_CRC_BCR         0x62
  17 #define ARC_REG_DVFB_BCR        0x64
  18 #define ARC_REG_EXTARITH_BCR    0x65
  19 #define ARC_REG_VECBASE_BCR     0x68
  20 #define ARC_REG_PERIBASE_BCR    0x69
  21 #define ARC_REG_FP_BCR          0x6B    /* Single-Precision FPU */
  22 #define ARC_REG_DPFP_BCR        0x6C    /* Dbl Precision FPU */
  23 #define ARC_REG_DCCM_BCR        0x74    /* DCCM Present + SZ */
  24 #define ARC_REG_TIMERS_BCR      0x75
  25 #define ARC_REG_ICCM_BCR        0x78
  26 #define ARC_REG_XY_MEM_BCR      0x79
  27 #define ARC_REG_MAC_BCR         0x7a
  28 #define ARC_REG_MUL_BCR         0x7b
  29 #define ARC_REG_SWAP_BCR        0x7c
  30 #define ARC_REG_NORM_BCR        0x7d
  31 #define ARC_REG_MIXMAX_BCR      0x7e
  32 #define ARC_REG_BARREL_BCR      0x7f
  33 #define ARC_REG_D_UNCACH_BCR    0x6A
  34
  35 /* status32 Bits Positions */
  36 #define STATUS_AE_BIT           5       /* Exception active */
  37 #define STATUS_DE_BIT           6       /* PC is in delay slot */
  38 #define STATUS_U_BIT            7       /* User/Kernel mode */
  39 #define STATUS_L_BIT            12      /* Loop inhibit */
  40
  41 /* These masks correspond to the status word(STATUS_32) bits */
  42 #define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
  43 #define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
  44 #define STATUS_U_MASK           (1<<STATUS_U_BIT)
  45 #define STATUS_L_MASK           (1<<STATUS_L_BIT)
  46
  47 /*
  48  * ECR: Exception Cause Reg bits-n-pieces
  49  * [23:16] = Exception Vector
  50  * [15: 8] = Exception Cause Code
  51  * [ 7: 0] = Exception Parameters (for certain types only)
  52  */
  53 #define ECR_VEC_MASK                    0xff0000
  54 #define ECR_CODE_MASK                   0x00ff00
  55 #define ECR_PARAM_MASK                  0x0000ff
  56
  57 /* Exception Cause Vector Values */
  58 #define ECR_V_INSN_ERR                  0x02
  59 #define ECR_V_MACH_CHK                  0x20
  60 #define ECR_V_ITLB_MISS                 0x21
  61 #define ECR_V_DTLB_MISS                 0x22
  62 #define ECR_V_PROTV                     0x23
  63
  64 /* Protection Violation Exception Cause Code Values */
  65 #define ECR_C_PROTV_INST_FETCH          0x00
  66 #define ECR_C_PROTV_LOAD                0x01
  67 #define ECR_C_PROTV_STORE               0x02
  68 #define ECR_C_PROTV_XCHG                0x03
  69 #define ECR_C_PROTV_MISALIG_DATA        0x04
  70
  71 /* DTLB Miss Exception Cause Code Values */
  72 #define ECR_C_BIT_DTLB_LD_MISS          8
  73 #define ECR_C_BIT_DTLB_ST_MISS          9
  74
  75
  76 /* Auxiliary registers */
  77 #define AUX_IDENTITY            4
  78 #define AUX_INTR_VEC_BASE       0x25
  79
  80
  81 /*
  82  * Floating Pt Registers
  83  * Status regs are read-only (build-time) so need not be saved/restored
  84  */
  85 #define ARC_AUX_FP_STAT         0x300
  86 #define ARC_AUX_DPFP_1L         0x301
  87 #define ARC_AUX_DPFP_1H         0x302
  88 #define ARC_AUX_DPFP_2L         0x303
  89 #define ARC_AUX_DPFP_2H         0x304
  90 #define ARC_AUX_DPFP_STAT       0x305
  91
  92 #ifndef __ASSEMBLY__
  93
  94 /*
  95  ******************************************************************
  96  *      Inline ASM macros to read/write AUX Regs
  97  *      Essentially invocation of lr/sr insns from "C"
  98  */
  99
 100 #if 1
 101
 102 #define read_aux_reg(reg)       __builtin_arc_lr(reg)
 103
 104 /* gcc builtin sr needs reg param to be long immediate */
 105 #define write_aux_reg(reg_immed, val)           \
 106                 __builtin_arc_sr((unsigned int)val, reg_immed)
 107
 108 #else
 109
 110 #define read_aux_reg(reg)               \
 111 ({                                      \
 112         unsigned int __ret;             \
 113         __asm__ __volatile__(           \
 114         "       lr    %0, [%1]"         \
 115         : "=r"(__ret)                   \
 116         : "i"(reg));                    \
 117         __ret;                          \
 118 })
 119
 120 /*
 121  * Aux Reg address is specified as long immediate by caller
 122  * e.g.
 123  *    write_aux_reg(0x69, some_val);
 124  * This generates tightest code.
 125  */
 126 #define write_aux_reg(reg_imm, val)     \
 127 ({                                      \
 128         __asm__ __volatile__(           \
 129         "       sr   %0, [%1]   \n"     \
 130         :                               \
 131         : "ir"(val), "i"(reg_imm));     \
 132 })
 133
 134 /*
 135  * Aux Reg address is specified in a variable
 136  *  * e.g.
 137  *      reg_num = 0x69
 138  *      write_aux_reg2(reg_num, some_val);
 139  * This has to generate glue code to load the reg num from
 140  *  memory to a reg hence not recommended.
 141  */
 142 #define write_aux_reg2(reg_in_var, val)         \
 143 ({                                              \
 144         unsigned int tmp;                       \
 145                                                 \
 146         __asm__ __volatile__(                   \
 147         "       ld   %0, [%2]   \n\t"           \
 148         "       sr   %1, [%0]   \n\t"           \
 149         : "=&r"(tmp)                            \
 150         : "r"(val), "memory"(&reg_in_var));     \
 151 })
 152
 153 #endif
 154
 155 #define READ_BCR(reg, into)                             \
 156 {                                                       \
 157         unsigned int tmp;                               \
 158         tmp = read_aux_reg(reg);                        \
 159         if (sizeof(tmp) == sizeof(into)) {              \
 160                 into = *((typeof(into) *)&tmp);         \
 161         } else {                                        \
 162                 extern void bogus_undefined(void);      \
 163                 bogus_undefined();                      \
 164         }                                               \
 165 }
 166
 167 #define WRITE_BCR(reg, into)                            \
 168 {                                                       \
 169         unsigned int tmp;                               \
 170         if (sizeof(tmp) == sizeof(into)) {              \
 171                 tmp = (*(unsigned int *)(into));        \
 172                 write_aux_reg(reg, tmp);                \
 173         } else  {                                       \
 174                 extern void bogus_undefined(void);      \
 175                 bogus_undefined();                      \
 176         }                                               \
 177 }
 178
 179 /* Helpers */
 180 #define TO_KB(bytes)            ((bytes) >> 10)
 181 #define TO_MB(bytes)            (TO_KB(bytes) >> 10)
 182 #define PAGES_TO_KB(n_pages)    ((n_pages) << (PAGE_SHIFT - 10))
 183 #define PAGES_TO_MB(n_pages)    (PAGES_TO_KB(n_pages) >> 10)
 184
 185 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
 186 /* These DPFP regs need to be saved/restored across ctx-sw */
 187 struct arc_fpu {
 188         struct {
 189                 unsigned int l, h;
 190         } aux_dpfp[2];
 191 };
 192 #endif
 193
 194 /*
 195  ***************************************************************
 196  * Build Configuration Registers, with encoded hardware config
 197  */
 198 struct bcr_identity {
 199 #ifdef CONFIG_CPU_BIG_ENDIAN
 200         unsigned int chip_id:16, cpu_id:8, family:8;
 201 #else
 202         unsigned int family:8, cpu_id:8, chip_id:16;
 203 #endif
 204 };
 205
 206 #define EXTN_SWAP_VALID     0x1
 207 #define EXTN_NORM_VALID     0x2
 208 #define EXTN_MINMAX_VALID   0x2
 209 #define EXTN_BARREL_VALID   0x2
 210
 211 struct bcr_extn {
 212 #ifdef CONFIG_CPU_BIG_ENDIAN
 213         unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
 214                      norm:2, swap:1;
 215 #else
 216         unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
 217                      crc:1, pad:20;
 218 #endif
 219 };
 220
 221 /* DSP Options Ref Manual */
 222 struct bcr_extn_mac_mul {
 223 #ifdef CONFIG_CPU_BIG_ENDIAN
 224         unsigned int pad:16, type:8, ver:8;
 225 #else
 226         unsigned int ver:8, type:8, pad:16;
 227 #endif
 228 };
 229
 230 struct bcr_extn_xymem {
 231 #ifdef CONFIG_CPU_BIG_ENDIAN
 232         unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
 233 #else
 234         unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
 235 #endif
 236 };
 237
 238 struct bcr_perip {
 239 #ifdef CONFIG_CPU_BIG_ENDIAN
 240         unsigned int start:8, pad2:8, sz:8, pad:8;
 241 #else
 242         unsigned int pad:8, sz:8, pad2:8, start:8;
 243 #endif
 244 };
 245 struct bcr_iccm {
 246 #ifdef CONFIG_CPU_BIG_ENDIAN
 247         unsigned int base:16, pad:5, sz:3, ver:8;
 248 #else
 249         unsigned int ver:8, sz:3, pad:5, base:16;
 250 #endif
 251 };
 252
 253 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
 254 struct bcr_dccm_base {
 255 #ifdef CONFIG_CPU_BIG_ENDIAN
 256         unsigned int addr:24, ver:8;
 257 #else
 258         unsigned int ver:8, addr:24;
 259 #endif
 260 };
 261
 262 /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
 263 struct bcr_dccm {
 264 #ifdef CONFIG_CPU_BIG_ENDIAN
 265         unsigned int res:21, sz:3, ver:8;
 266 #else
 267         unsigned int ver:8, sz:3, res:21;
 268 #endif
 269 };
 270
 271 /* Both SP and DP FPU BCRs have same format */
 272 struct bcr_fp {
 273 #ifdef CONFIG_CPU_BIG_ENDIAN
 274         unsigned int fast:1, ver:8;
 275 #else
 276         unsigned int ver:8, fast:1;
 277 #endif
 278 };
 279
 280 /*
 281  *******************************************************************
 282  * Generic structures to hold build configuration used at runtime
 283  */
 284
 285 struct cpuinfo_arc_mmu {
 286         unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
 287 };
 288
 289 struct cpuinfo_arc_cache {
 290         unsigned int has_aliasing, sz, line_len, assoc, ver;
 291 };
 292
 293 struct cpuinfo_arc_ccm {
 294         unsigned int base_addr, sz;
 295 };
 296
 297 struct cpuinfo_arc {
 298         struct cpuinfo_arc_cache icache, dcache;
 299         struct cpuinfo_arc_mmu mmu;
 300         struct bcr_identity core;
 301         unsigned int timers;
 302         unsigned int vec_base;
 303         unsigned int uncached_base;
 304         struct cpuinfo_arc_ccm iccm, dccm;
 305         struct bcr_extn extn;
 306         struct bcr_extn_xymem extn_xymem;
 307         struct bcr_extn_mac_mul extn_mac_mul;
 308         struct bcr_fp fp, dpfp;
 309 };
 310
 311 extern struct cpuinfo_arc cpuinfo_arc700[];
 312
 313 #endif /* __ASEMBLY__ */
 314
 315 #endif /* __KERNEL__ */
 316
 317 #endif /* _ASM_ARC_ARCREGS_H */