2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef _ASM_ARC_ARCREGS_H
10 #define _ASM_ARC_ARCREGS_H
12 /* Build Configuration Registers */
13 #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
14 #define ARC_REG_CRC_BCR 0x62
15 #define ARC_REG_VECBASE_BCR 0x68
16 #define ARC_REG_PERIBASE_BCR 0x69
17 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
18 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
19 #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
20 #define ARC_REG_TIMERS_BCR 0x75
21 #define ARC_REG_AP_BCR 0x76
22 #define ARC_REG_ICCM_BCR 0x78
23 #define ARC_REG_XY_MEM_BCR 0x79
24 #define ARC_REG_MAC_BCR 0x7a
25 #define ARC_REG_MUL_BCR 0x7b
26 #define ARC_REG_SWAP_BCR 0x7c
27 #define ARC_REG_NORM_BCR 0x7d
28 #define ARC_REG_MIXMAX_BCR 0x7e
29 #define ARC_REG_BARREL_BCR 0x7f
30 #define ARC_REG_D_UNCACH_BCR 0x6A
31 #define ARC_REG_BPU_BCR 0xc0
32 #define ARC_REG_ISA_CFG_BCR 0xc1
33 #define ARC_REG_SMART_BCR 0xFF
35 /* status32 Bits Positions */
36 #define STATUS_AE_BIT 5 /* Exception active */
37 #define STATUS_DE_BIT 6 /* PC is in delay slot */
38 #define STATUS_U_BIT 7 /* User/Kernel mode */
39 #define STATUS_L_BIT 12 /* Loop inhibit */
41 /* These masks correspond to the status word(STATUS_32) bits */
42 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
43 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
44 #define STATUS_U_MASK (1<<STATUS_U_BIT)
45 #define STATUS_L_MASK (1<<STATUS_L_BIT)
48 * ECR: Exception Cause Reg bits-n-pieces
49 * [23:16] = Exception Vector
50 * [15: 8] = Exception Cause Code
51 * [ 7: 0] = Exception Parameters (for certain types only)
53 #define ECR_VEC_MASK 0xff0000
54 #define ECR_CODE_MASK 0x00ff00
55 #define ECR_PARAM_MASK 0x0000ff
57 /* Exception Cause Vector Values */
58 #define ECR_V_INSN_ERR 0x02
59 #define ECR_V_MACH_CHK 0x20
60 #define ECR_V_ITLB_MISS 0x21
61 #define ECR_V_DTLB_MISS 0x22
62 #define ECR_V_PROTV 0x23
63 #define ECR_V_TRAP 0x25
65 /* Protection Violation Exception Cause Code Values */
66 #define ECR_C_PROTV_INST_FETCH 0x00
67 #define ECR_C_PROTV_LOAD 0x01
68 #define ECR_C_PROTV_STORE 0x02
69 #define ECR_C_PROTV_XCHG 0x03
70 #define ECR_C_PROTV_MISALIG_DATA 0x04
72 #define ECR_C_BIT_PROTV_MISALIG_DATA 10
74 /* Machine Check Cause Code Values */
75 #define ECR_C_MCHK_DUP_TLB 0x01
77 /* DTLB Miss Exception Cause Code Values */
78 #define ECR_C_BIT_DTLB_LD_MISS 8
79 #define ECR_C_BIT_DTLB_ST_MISS 9
81 /* Dummy ECR values for Interrupts */
82 #define event_IRQ1 0x0031abcd
83 #define event_IRQ2 0x0032abcd
85 /* Auxiliary registers */
86 #define AUX_IDENTITY 4
87 #define AUX_INTR_VEC_BASE 0x25
91 * Floating Pt Registers
92 * Status regs are read-only (build-time) so need not be saved/restored
94 #define ARC_AUX_FP_STAT 0x300
95 #define ARC_AUX_DPFP_1L 0x301
96 #define ARC_AUX_DPFP_1H 0x302
97 #define ARC_AUX_DPFP_2L 0x303
98 #define ARC_AUX_DPFP_2H 0x304
99 #define ARC_AUX_DPFP_STAT 0x305
104 ******************************************************************
105 * Inline ASM macros to read/write AUX Regs
106 * Essentially invocation of lr/sr insns from "C"
111 #define read_aux_reg(reg) __builtin_arc_lr(reg)
113 /* gcc builtin sr needs reg param to be long immediate */
114 #define write_aux_reg(reg_immed, val) \
115 __builtin_arc_sr((unsigned int)val, reg_immed)
119 #define read_aux_reg(reg) \
121 unsigned int __ret; \
122 __asm__ __volatile__( \
130 * Aux Reg address is specified as long immediate by caller
132 * write_aux_reg(0x69, some_val);
133 * This generates tightest code.
135 #define write_aux_reg(reg_imm, val) \
137 __asm__ __volatile__( \
140 : "ir"(val), "i"(reg_imm)); \
144 * Aux Reg address is specified in a variable
147 * write_aux_reg2(reg_num, some_val);
148 * This has to generate glue code to load the reg num from
149 * memory to a reg hence not recommended.
151 #define write_aux_reg2(reg_in_var, val) \
155 __asm__ __volatile__( \
156 " ld %0, [%2] \n\t" \
157 " sr %1, [%0] \n\t" \
159 : "r"(val), "memory"(®_in_var)); \
164 #define READ_BCR(reg, into) \
167 tmp = read_aux_reg(reg); \
168 if (sizeof(tmp) == sizeof(into)) { \
169 into = *((typeof(into) *)&tmp); \
171 extern void bogus_undefined(void); \
176 #define WRITE_BCR(reg, into) \
179 if (sizeof(tmp) == sizeof(into)) { \
180 tmp = (*(unsigned int *)(into)); \
181 write_aux_reg(reg, tmp); \
183 extern void bogus_undefined(void); \
189 #define TO_KB(bytes) ((bytes) >> 10)
190 #define TO_MB(bytes) (TO_KB(bytes) >> 10)
191 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
192 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
196 ***************************************************************
197 * Build Configuration Registers, with encoded hardware config
199 struct bcr_identity
{
200 #ifdef CONFIG_CPU_BIG_ENDIAN
201 unsigned int chip_id
:16, cpu_id
:8, family
:8;
203 unsigned int family
:8, cpu_id
:8, chip_id
:16;
208 #ifdef CONFIG_CPU_BIG_ENDIAN
209 unsigned int pad1
:23, atomic1
:1, ver
:8;
211 unsigned int ver
:8, atomic1
:1, pad1
:23;
216 #ifdef CONFIG_CPU_BIG_ENDIAN
217 unsigned int pad
:8, x1616
:8, dsp
:4, cycles
:2, type
:2, ver
:8;
219 unsigned int ver
:8, type
:2, cycles
:2, dsp
:4, x1616
:8, pad
:8;
223 struct bcr_extn_xymem
{
224 #ifdef CONFIG_CPU_BIG_ENDIAN
225 unsigned int ram_org
:2, num_banks
:4, bank_sz
:4, ver
:8;
227 unsigned int ver
:8, bank_sz
:4, num_banks
:4, ram_org
:2;
232 #ifdef CONFIG_CPU_BIG_ENDIAN
233 unsigned int start
:8, pad2
:8, sz
:8, pad
:8;
235 unsigned int pad
:8, sz
:8, pad2
:8, start
:8;
240 #ifdef CONFIG_CPU_BIG_ENDIAN
241 unsigned int base
:16, pad
:5, sz
:3, ver
:8;
243 unsigned int ver
:8, sz
:3, pad
:5, base
:16;
247 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
248 struct bcr_dccm_base
{
249 #ifdef CONFIG_CPU_BIG_ENDIAN
250 unsigned int addr
:24, ver
:8;
252 unsigned int ver
:8, addr
:24;
256 /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
258 #ifdef CONFIG_CPU_BIG_ENDIAN
259 unsigned int res
:21, sz
:3, ver
:8;
261 unsigned int ver
:8, sz
:3, res
:21;
265 /* ARCompact: Both SP and DP FPU BCRs have same format */
266 struct bcr_fp_arcompact
{
267 #ifdef CONFIG_CPU_BIG_ENDIAN
268 unsigned int fast
:1, ver
:8;
270 unsigned int ver
:8, fast
:1;
275 #ifdef CONFIG_CPU_BIG_ENDIAN
276 unsigned int pad2
:15, rtsc
:1, pad1
:6, t1
:1, t0
:1, ver
:8;
278 unsigned int ver
:8, t0
:1, t1
:1, pad1
:6, rtsc
:1, pad2
:15;
282 struct bcr_bpu_arcompact
{
283 #ifdef CONFIG_CPU_BIG_ENDIAN
284 unsigned int pad2
:19, fam
:1, pad
:2, ent
:2, ver
:8;
286 unsigned int ver
:8, ent
:2, pad
:2, fam
:1, pad2
:19;
291 #ifdef CONFIG_CPU_BIG_ENDIAN
292 unsigned int pad
:24, ver
:8;
294 unsigned int ver
:8, pad
:24;
299 *******************************************************************
300 * Generic structures to hold build configuration used at runtime
303 struct cpuinfo_arc_mmu
{
304 unsigned int ver
, pg_sz
, sets
, ways
, u_dtlb
, u_itlb
, num_tlb
;
307 struct cpuinfo_arc_cache
{
308 unsigned int sz_k
:8, line_len
:8, assoc
:4, ver
:4, alias
:1, vipt
:1, pad
:6;
311 struct cpuinfo_arc_bpu
{
312 unsigned int ver
, full
, num_cache
, num_pred
;
315 struct cpuinfo_arc_ccm
{
316 unsigned int base_addr
, sz
;
320 struct cpuinfo_arc_cache icache
, dcache
;
321 struct cpuinfo_arc_mmu mmu
;
322 struct cpuinfo_arc_bpu bpu
;
323 struct bcr_identity core
;
325 struct bcr_timer timers
;
326 unsigned int vec_base
;
327 unsigned int uncached_base
;
328 struct cpuinfo_arc_ccm iccm
, dccm
;
330 unsigned int swap
:1, norm
:1, minmax
:1, barrel
:1, crc
:1, pad1
:3,
331 fpu_sp
:1, fpu_dp
:1, pad2
:6,
332 debug
:1, ap
:1, smart
:1, rtt
:1, pad3
:4,
335 struct bcr_mpy extn_mpy
;
336 struct bcr_extn_xymem extn_xymem
;
339 extern struct cpuinfo_arc cpuinfo_arc700
[];
341 #endif /* __ASEMBLY__ */
343 #endif /* _ASM_ARC_ARCREGS_H */