arch/arc/include/asm/arcregs.h

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef _ASM_ARC_ARCREGS_H
  10 #define _ASM_ARC_ARCREGS_H
  11
  12 /* Build Configuration Registers */
  13 #define ARC_REG_AUX_DCCM        0x18    /* DCCM Base Addr ARCv2 */
  14 #define ARC_REG_DCCM_BASE_BUILD 0x61    /* DCCM Base Addr ARCompact */
  15 #define ARC_REG_CRC_BCR         0x62
  16 #define ARC_REG_VECBASE_BCR     0x68
  17 #define ARC_REG_PERIBASE_BCR    0x69
  18 #define ARC_REG_FP_BCR          0x6B    /* ARCompact: Single-Precision FPU */
  19 #define ARC_REG_DPFP_BCR        0x6C    /* ARCompact: Dbl Precision FPU */
  20 #define ARC_REG_FP_V2_BCR       0xc8    /* ARCv2 FPU */
  21 #define ARC_REG_SLC_BCR         0xce
  22 #define ARC_REG_DCCM_BUILD      0x74    /* DCCM size (common) */
  23 #define ARC_REG_AP_BCR          0x76
  24 #define ARC_REG_ICCM_BUILD      0x78    /* ICCM size (common) */
  25 #define ARC_REG_XY_MEM_BCR      0x79
  26 #define ARC_REG_MAC_BCR         0x7a
  27 #define ARC_REG_MUL_BCR         0x7b
  28 #define ARC_REG_SWAP_BCR        0x7c
  29 #define ARC_REG_NORM_BCR        0x7d
  30 #define ARC_REG_MIXMAX_BCR      0x7e
  31 #define ARC_REG_BARREL_BCR      0x7f
  32 #define ARC_REG_D_UNCACH_BCR    0x6A
  33 #define ARC_REG_BPU_BCR         0xc0
  34 #define ARC_REG_ISA_CFG_BCR     0xc1
  35 #define ARC_REG_RTT_BCR         0xF2
  36 #define ARC_REG_IRQ_BCR         0xF3
  37 #define ARC_REG_SMART_BCR       0xFF
  38 #define ARC_REG_CLUSTER_BCR     0xcf
  39 #define ARC_REG_AUX_ICCM        0x208   /* ICCM Base Addr (ARCv2) */
  40
  41 /* status32 Bits Positions */
  42 #define STATUS_AE_BIT           5       /* Exception active */
  43 #define STATUS_DE_BIT           6       /* PC is in delay slot */
  44 #define STATUS_U_BIT            7       /* User/Kernel mode */
  45 #define STATUS_Z_BIT            11
  46 #define STATUS_L_BIT            12      /* Loop inhibit */
  47
  48 /* These masks correspond to the status word(STATUS_32) bits */
  49 #define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
  50 #define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
  51 #define STATUS_U_MASK           (1<<STATUS_U_BIT)
  52 #define STATUS_Z_MASK           (1<<STATUS_Z_BIT)
  53 #define STATUS_L_MASK           (1<<STATUS_L_BIT)
  54
  55 /*
  56  * ECR: Exception Cause Reg bits-n-pieces
  57  * [23:16] = Exception Vector
  58  * [15: 8] = Exception Cause Code
  59  * [ 7: 0] = Exception Parameters (for certain types only)
  60  */
  61 #ifdef CONFIG_ISA_ARCOMPACT
  62 #define ECR_V_MEM_ERR                   0x01
  63 #define ECR_V_INSN_ERR                  0x02
  64 #define ECR_V_MACH_CHK                  0x20
  65 #define ECR_V_ITLB_MISS                 0x21
  66 #define ECR_V_DTLB_MISS                 0x22
  67 #define ECR_V_PROTV                     0x23
  68 #define ECR_V_TRAP                      0x25
  69 #else
  70 #define ECR_V_MEM_ERR                   0x01
  71 #define ECR_V_INSN_ERR                  0x02
  72 #define ECR_V_MACH_CHK                  0x03
  73 #define ECR_V_ITLB_MISS                 0x04
  74 #define ECR_V_DTLB_MISS                 0x05
  75 #define ECR_V_PROTV                     0x06
  76 #define ECR_V_TRAP                      0x09
  77 #endif
  78
  79 /* DTLB Miss and Protection Violation Cause Codes */
  80
  81 #define ECR_C_PROTV_INST_FETCH          0x00
  82 #define ECR_C_PROTV_LOAD                0x01
  83 #define ECR_C_PROTV_STORE               0x02
  84 #define ECR_C_PROTV_XCHG                0x03
  85 #define ECR_C_PROTV_MISALIG_DATA        0x04
  86
  87 #define ECR_C_BIT_PROTV_MISALIG_DATA    10
  88
  89 /* Machine Check Cause Code Values */
  90 #define ECR_C_MCHK_DUP_TLB              0x01
  91
  92 /* DTLB Miss Exception Cause Code Values */
  93 #define ECR_C_BIT_DTLB_LD_MISS          8
  94 #define ECR_C_BIT_DTLB_ST_MISS          9
  95
  96 /* Auxiliary registers */
  97 #define AUX_IDENTITY            4
  98 #define AUX_INTR_VEC_BASE       0x25
  99 #define AUX_VOL                 0x5e
 100
 101 /*
 102  * Floating Pt Registers
 103  * Status regs are read-only (build-time) so need not be saved/restored
 104  */
 105 #define ARC_AUX_FP_STAT         0x300
 106 #define ARC_AUX_DPFP_1L         0x301
 107 #define ARC_AUX_DPFP_1H         0x302
 108 #define ARC_AUX_DPFP_2L         0x303
 109 #define ARC_AUX_DPFP_2H         0x304
 110 #define ARC_AUX_DPFP_STAT       0x305
 111
 112 #ifndef __ASSEMBLY__
 113
 114 #include <soc/arc/aux.h>
 115
 116 /* Helpers */
 117 #define TO_KB(bytes)            ((bytes) >> 10)
 118 #define TO_MB(bytes)            (TO_KB(bytes) >> 10)
 119 #define PAGES_TO_KB(n_pages)    ((n_pages) << (PAGE_SHIFT - 10))
 120 #define PAGES_TO_MB(n_pages)    (PAGES_TO_KB(n_pages) >> 10)
 121
 122
 123 /*
 124  ***************************************************************
 125  * Build Configuration Registers, with encoded hardware config
 126  */
 127 struct bcr_identity {
 128 #ifdef CONFIG_CPU_BIG_ENDIAN
 129         unsigned int chip_id:16, cpu_id:8, family:8;
 130 #else
 131         unsigned int family:8, cpu_id:8, chip_id:16;
 132 #endif
 133 };
 134
 135 struct bcr_isa {
 136 #ifdef CONFIG_CPU_BIG_ENDIAN
 137         unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
 138                      pad1:11, atomic1:1, ver:8;
 139 #else
 140         unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
 141                      ldd:1, pad2:4, div_rem:4;
 142 #endif
 143 };
 144
 145 struct bcr_mpy {
 146 #ifdef CONFIG_CPU_BIG_ENDIAN
 147         unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
 148 #else
 149         unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
 150 #endif
 151 };
 152
 153 struct bcr_extn_xymem {
 154 #ifdef CONFIG_CPU_BIG_ENDIAN
 155         unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
 156 #else
 157         unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
 158 #endif
 159 };
 160
 161 struct bcr_iccm_arcompact {
 162 #ifdef CONFIG_CPU_BIG_ENDIAN
 163         unsigned int base:16, pad:5, sz:3, ver:8;
 164 #else
 165         unsigned int ver:8, sz:3, pad:5, base:16;
 166 #endif
 167 };
 168
 169 struct bcr_iccm_arcv2 {
 170 #ifdef CONFIG_CPU_BIG_ENDIAN
 171         unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
 172 #else
 173         unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
 174 #endif
 175 };
 176
 177 struct bcr_dccm_arcompact {
 178 #ifdef CONFIG_CPU_BIG_ENDIAN
 179         unsigned int res:21, sz:3, ver:8;
 180 #else
 181         unsigned int ver:8, sz:3, res:21;
 182 #endif
 183 };
 184
 185 struct bcr_dccm_arcv2 {
 186 #ifdef CONFIG_CPU_BIG_ENDIAN
 187         unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
 188 #else
 189         unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
 190 #endif
 191 };
 192
 193 /* ARCompact: Both SP and DP FPU BCRs have same format */
 194 struct bcr_fp_arcompact {
 195 #ifdef CONFIG_CPU_BIG_ENDIAN
 196         unsigned int fast:1, ver:8;
 197 #else
 198         unsigned int ver:8, fast:1;
 199 #endif
 200 };
 201
 202 struct bcr_fp_arcv2 {
 203 #ifdef CONFIG_CPU_BIG_ENDIAN
 204         unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
 205 #else
 206         unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
 207 #endif
 208 };
 209
 210 #include <soc/arc/timers.h>
 211
 212 struct bcr_bpu_arcompact {
 213 #ifdef CONFIG_CPU_BIG_ENDIAN
 214         unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
 215 #else
 216         unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
 217 #endif
 218 };
 219
 220 struct bcr_bpu_arcv2 {
 221 #ifdef CONFIG_CPU_BIG_ENDIAN
 222         unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
 223 #else
 224         unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
 225 #endif
 226 };
 227
 228 struct bcr_generic {
 229 #ifdef CONFIG_CPU_BIG_ENDIAN
 230         unsigned int info:24, ver:8;
 231 #else
 232         unsigned int ver:8, info:24;
 233 #endif
 234 };
 235
 236 /*
 237  *******************************************************************
 238  * Generic structures to hold build configuration used at runtime
 239  */
 240
 241 struct cpuinfo_arc_mmu {
 242         unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
 243         unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
 244 };
 245
 246 struct cpuinfo_arc_cache {
 247         unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
 248 };
 249
 250 struct cpuinfo_arc_bpu {
 251         unsigned int ver, full, num_cache, num_pred;
 252 };
 253
 254 struct cpuinfo_arc_ccm {
 255         unsigned int base_addr, sz;
 256 };
 257
 258 struct cpuinfo_arc {
 259         struct cpuinfo_arc_cache icache, dcache, slc;
 260         struct cpuinfo_arc_mmu mmu;
 261         struct cpuinfo_arc_bpu bpu;
 262         struct bcr_identity core;
 263         struct bcr_isa isa;
 264         const char *details, *name;
 265         unsigned int vec_base;
 266         struct cpuinfo_arc_ccm iccm, dccm;
 267         struct {
 268                 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
 269                              fpu_sp:1, fpu_dp:1, pad2:6,
 270                              debug:1, ap:1, smart:1, rtt:1, pad3:4,
 271                              timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
 272         } extn;
 273         struct bcr_mpy extn_mpy;
 274         struct bcr_extn_xymem extn_xymem;
 275 };
 276
 277 extern struct cpuinfo_arc cpuinfo_arc700[];
 278
 279 static inline int is_isa_arcv2(void)
 280 {
 281         return IS_ENABLED(CONFIG_ISA_ARCV2);
 282 }
 283
 284 static inline int is_isa_arcompact(void)
 285 {
 286         return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
 287 }
 288
 289 #endif /* __ASEMBLY__ */
 290
 291 #endif /* _ASM_ARC_ARCREGS_H */