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2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #ifndef _LINUX_BITOPS_H
13 #error only <linux/bitops.h> can be included directly
18 #include <linux/types.h>
19 #include <linux/compiler.h>
20 #include <asm/barrier.h>
21 #ifndef CONFIG_ARC_HAS_LLSC
25 #if defined(CONFIG_ARC_HAS_LLSC)
28 * Hardware assisted Atomic-R-M-W
31 #define BIT_OP(op, c_op, asm_op) \
32 static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
39 * ARC ISA micro-optimization: \
41 * Instructions dealing with bitpos only consider lower 5 bits \
42 * e.g (x << 33) is handled like (x << 1) by ASL instruction \
43 * (mem pointer still needs adjustment to point to next word) \
45 * Hence the masking to clamp @nr arg can be elided in general. \
47 * However if @nr is a constant (above assumed in a register), \
48 * and greater than 31, gcc can optimize away (x << 33) to 0, \
49 * as overflow, given the 32-bit ISA. Thus masking needs to be \
50 * done for const @nr, but no code is generated due to gcc \
55 __asm__ __volatile__( \
56 "1: llock %0, [%1] \n" \
57 " " #asm_op " %0, %0, %2 \n" \
58 " scond %0, [%1] \n" \
60 : "=&r"(temp) /* Early clobber, to prevent reg reuse */ \
61 : "r"(m), /* Not "m": llock only supports reg direct addr mode */ \
70 * set it and return 0 (old value)
72 * return 1 (old value).
74 * Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
75 * and the old value of bit is returned
77 #define TEST_N_BIT_OP(op, c_op, asm_op) \
78 static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
80 unsigned long old, temp; \
87 * Explicit full memory barrier needed before/after as \
88 * LLOCK/SCOND themselves don't provide any such smenatic \
92 __asm__ __volatile__( \
93 "1: llock %0, [%2] \n" \
94 " " #asm_op " %1, %0, %3 \n" \
95 " scond %1, [%2] \n" \
97 : "=&r"(old), "=&r"(temp) \
103 return (old & (1 << nr)) != 0; \
106 #else /* !CONFIG_ARC_HAS_LLSC */
109 * Non hardware assisted Atomic-R-M-W
110 * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
112 * There's "significant" micro-optimization in writing our own variants of
113 * bitops (over generic variants)
115 * (1) The generic APIs have "signed" @nr while we have it "unsigned"
116 * This avoids extra code to be generated for pointer arithmatic, since
117 * is "not sure" that index is NOT -ve
118 * (2) Utilize the fact that ARCompact bit fidding insn (BSET/BCLR/ASL) etc
119 * only consider bottom 5 bits of @nr, so NO need to mask them off.
120 * (GCC Quirk: however for constant @nr we still need to do the masking
124 #define BIT_OP(op, c_op, asm_op) \
125 static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
127 unsigned long temp, flags; \
131 * spin lock/unlock provide the needed smp_mb() before/after \
133 bitops_lock(flags); \
136 *m = temp c_op (1UL << (nr & 0x1f)); \
138 bitops_unlock(flags); \
141 #define TEST_N_BIT_OP(op, c_op, asm_op) \
142 static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
144 unsigned long old, flags; \
147 bitops_lock(flags); \
150 *m = old c_op (1UL << (nr & 0x1f)); \
152 bitops_unlock(flags); \
154 return (old & (1UL << (nr & 0x1f))) != 0; \
157 #endif /* CONFIG_ARC_HAS_LLSC */
159 /***************************************
160 * Non atomic variants
161 **************************************/
163 #define __BIT_OP(op, c_op, asm_op) \
164 static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \
166 unsigned long temp; \
170 *m = temp c_op (1UL << (nr & 0x1f)); \
173 #define __TEST_N_BIT_OP(op, c_op, asm_op) \
174 static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
180 *m = old c_op (1UL << (nr & 0x1f)); \
182 return (old & (1UL << (nr & 0x1f))) != 0; \
185 #define BIT_OPS(op, c_op, asm_op) \
187 /* set_bit(), clear_bit(), change_bit() */ \
188 BIT_OP(op, c_op, asm_op) \
190 /* test_and_set_bit(), test_and_clear_bit(), test_and_change_bit() */\
191 TEST_N_BIT_OP(op, c_op, asm_op) \
193 /* __set_bit(), __clear_bit(), __change_bit() */ \
194 __BIT_OP(op, c_op, asm_op) \
196 /* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
197 __TEST_N_BIT_OP(op, c_op, asm_op)
199 BIT_OPS(set
, |, bset
)
200 BIT_OPS(clear
, & ~, bclr
)
201 BIT_OPS(change
, ^, bxor
)
204 * This routine doesn't need to be atomic.
207 test_bit(unsigned int nr
, const volatile unsigned long *addr
)
213 mask
= 1UL << (nr
& 0x1f);
215 return ((mask
& *addr
) != 0);
218 #ifdef CONFIG_ISA_ARCOMPACT
221 * Count the number of zeros, starting from MSB
222 * Helper for fls( ) friends
223 * This is a pure count, so (1-32) or (0-31) doesn't apply
224 * It could be 0 to 32, based on num of 0's in there
225 * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
227 static inline __attribute__ ((const)) int clz(unsigned int x
)
231 __asm__
__volatile__(
234 " add.p %0, %0, 1 \n"
242 static inline int constant_fls(int x
)
248 if (!(x
& 0xffff0000u
)) {
252 if (!(x
& 0xff000000u
)) {
256 if (!(x
& 0xf0000000u
)) {
260 if (!(x
& 0xc0000000u
)) {
264 if (!(x
& 0x80000000u
)) {
272 * fls = Find Last Set in word
274 * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
276 static inline __attribute__ ((const)) int fls(unsigned long x
)
278 if (__builtin_constant_p(x
))
279 return constant_fls(x
);
285 * __fls: Similar to fls, but zero based (0-31)
287 static inline __attribute__ ((const)) int __fls(unsigned long x
)
296 * ffs = Find First Set in word (LSB to MSB)
297 * @result: [1-32], 0 if all 0's
299 #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
302 * __ffs: Similar to ffs, but zero based (0-31)
304 static inline __attribute__ ((const)) int __ffs(unsigned long word
)
309 return ffs(word
) - 1;
312 #else /* CONFIG_ISA_ARCV2 */
315 * fls = Find Last Set in word
317 * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
319 static inline __attribute__ ((const)) int fls(unsigned long x
)
324 " fls.f %0, %1 \n" /* 0:31; 0(Z) if src 0 */
325 " add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */
326 : "=r"(n
) /* Early clobber not needed */
334 * __fls: Similar to fls, but zero based (0-31). Also 0 if no bit set
336 static inline __attribute__ ((const)) int __fls(unsigned long x
)
338 /* FLS insn has exactly same semantics as the API */
339 return __builtin_arc_fls(x
);
343 * ffs = Find First Set in word (LSB to MSB)
344 * @result: [1-32], 0 if all 0's
346 static inline __attribute__ ((const)) int ffs(unsigned long x
)
351 " ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */
352 " add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */
353 " mov.z %0, 0 \n" /* 31(Z)-> 0 */
354 : "=r"(n
) /* Early clobber not needed */
362 * __ffs: Similar to ffs, but zero based (0-31)
364 static inline __attribute__ ((const)) int __ffs(unsigned long x
)
369 " ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */
370 " mov.z %0, 0 \n" /* 31(Z)-> 0 */
379 #endif /* CONFIG_ISA_ARCOMPACT */
382 * ffz = Find First Zero in word.
383 * @return:[0-31], 32 if all 1's
385 #define ffz(x) __ffs(~(x))
387 #include <asm-generic/bitops/hweight.h>
388 #include <asm-generic/bitops/fls64.h>
389 #include <asm-generic/bitops/sched.h>
390 #include <asm-generic/bitops/lock.h>
392 #include <asm-generic/bitops/find.h>
393 #include <asm-generic/bitops/le.h>
394 #include <asm-generic/bitops/ext2-atomic-setbit.h>
396 #endif /* !__ASSEMBLY__ */