arch/arc/include/asm/mcip.h

   1 /*
   2  * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
   3  *
   4  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __ASM_MCIP_H
  12 #define __ASM_MCIP_H
  13
  14 #ifdef CONFIG_ISA_ARCV2
  15
  16 #include <asm/arcregs.h>
  17
  18 #define ARC_REG_MCIP_BCR        0x0d0
  19 #define ARC_REG_MCIP_CMD        0x600
  20 #define ARC_REG_MCIP_WDATA      0x601
  21 #define ARC_REG_MCIP_READBACK   0x602
  22
  23 struct mcip_cmd {
  24 #ifdef CONFIG_CPU_BIG_ENDIAN
  25         unsigned int pad:8, param:16, cmd:8;
  26 #else
  27         unsigned int cmd:8, param:16, pad:8;
  28 #endif
  29
  30 #define CMD_INTRPT_GENERATE_IRQ         0x01
  31 #define CMD_INTRPT_GENERATE_ACK         0x02
  32 #define CMD_INTRPT_READ_STATUS          0x03
  33 #define CMD_INTRPT_CHECK_SOURCE         0x04
  34
  35 /* Semaphore Commands */
  36 #define CMD_SEMA_CLAIM_AND_READ         0x11
  37 #define CMD_SEMA_RELEASE                0x12
  38
  39 #define CMD_DEBUG_SET_MASK              0x34
  40 #define CMD_DEBUG_SET_SELECT            0x36
  41
  42 #define CMD_GFRC_READ_LO                0x42
  43 #define CMD_GFRC_READ_HI                0x43
  44
  45 #define CMD_IDU_ENABLE                  0x71
  46 #define CMD_IDU_DISABLE                 0x72
  47 #define CMD_IDU_SET_MODE                0x74
  48 #define CMD_IDU_SET_DEST                0x76
  49 #define CMD_IDU_SET_MASK                0x7C
  50
  51 #define IDU_M_TRIG_LEVEL                0x0
  52 #define IDU_M_TRIG_EDGE                 0x1
  53
  54 #define IDU_M_DISTRI_RR                 0x0
  55 #define IDU_M_DISTRI_DEST               0x2
  56 };
  57
  58 struct mcip_bcr {
  59 #ifdef CONFIG_CPU_BIG_ENDIAN
  60                 unsigned int pad3:8,
  61                              idu:1, llm:1, num_cores:6,
  62                              iocoh:1,  gfrc:1, dbg:1, pad2:1,
  63                              msg:1, sem:1, ipi:1, pad:1,
  64                              ver:8;
  65 #else
  66                 unsigned int ver:8,
  67                              pad:1, ipi:1, sem:1, msg:1,
  68                              pad2:1, dbg:1, gfrc:1, iocoh:1,
  69                              num_cores:6, llm:1, idu:1,
  70                              pad3:8;
  71 #endif
  72 };
  73
  74 /*
  75  * MCIP programming model
  76  *
  77  * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
  78  *   (param could be irq, common_irq, core_id ...)
  79  * - More involved commands setup MCIP_WDATA with cmd specific data
  80  *   before invoking the simple command
  81  */
  82 static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
  83 {
  84         struct mcip_cmd buf;
  85
  86         buf.pad = 0;
  87         buf.cmd = cmd;
  88         buf.param = param;
  89
  90         WRITE_AUX(ARC_REG_MCIP_CMD, buf);
  91 }
  92
  93 /*
  94  * Setup additional data for a cmd
  95  * Callers need to lock to ensure atomicity
  96  */
  97 static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
  98                                    unsigned int data)
  99 {
 100         write_aux_reg(ARC_REG_MCIP_WDATA, data);
 101
 102         __mcip_cmd(cmd, param);
 103 }
 104
 105 #endif
 106
 107 #endif