arch/arc/kernel/head.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * ARC CPU startup Code
   4  *
   5  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   6  *
   7  * Vineetg: Dec 2007
   8  *  -Check if we are running on Simulator or on real hardware
   9  *      to skip certain things during boot on simulator
  10  */
  11
  12 #include <linux/linkage.h>
  13 #include <asm/asm-offsets.h>
  14 #include <asm/entry.h>
  15 #include <asm/arcregs.h>
  16 #include <asm/cache.h>
  17 #include <asm/irqflags.h>
  18
  19 .macro CPU_EARLY_SETUP
  20
  21         ; Setting up Vectror Table (in case exception happens in early boot
  22         sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
  23
  24         ; Disable I-cache/D-cache if kernel so configured
  25         lr      r5, [ARC_REG_IC_BCR]
  26         breq    r5, 0, 1f               ; I$ doesn't exist
  27         lr      r5, [ARC_REG_IC_CTRL]
  28 #ifdef CONFIG_ARC_HAS_ICACHE
  29         bclr    r5, r5, 0               ; 0 - Enable, 1 is Disable
  30 #else
  31         bset    r5, r5, 0               ; I$ exists, but is not used
  32 #endif
  33         sr      r5, [ARC_REG_IC_CTRL]
  34
  35 1:
  36         lr      r5, [ARC_REG_DC_BCR]
  37         breq    r5, 0, 1f               ; D$ doesn't exist
  38         lr      r5, [ARC_REG_DC_CTRL]
  39         bclr    r5, r5, 6               ; Invalidate (discard w/o wback)
  40 #ifdef CONFIG_ARC_HAS_DCACHE
  41         bclr    r5, r5, 0               ; Enable (+Inv)
  42 #else
  43         bset    r5, r5, 0               ; Disable (+Inv)
  44 #endif
  45         sr      r5, [ARC_REG_DC_CTRL]
  46
  47 1:
  48
  49 #ifdef CONFIG_ISA_ARCV2
  50         ; Unaligned access is disabled at reset, so re-enable early as
  51         ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access
  52         ; by default
  53         lr      r5, [status32]
  54 #ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
  55         bset    r5, r5, STATUS_AD_BIT
  56 #else
  57         ; Although disabled at reset, bootloader might have enabled it
  58         bclr    r5, r5, STATUS_AD_BIT
  59 #endif
  60         kflag   r5
  61 #endif
  62 .endm
  63
  64         .section .init.text, "ax",@progbits
  65
  66 ;----------------------------------------------------------------
  67 ; Default Reset Handler (jumped into from Reset vector)
  68 ; - Don't clobber r0,r1,r2 as they might have u-boot provided args
  69 ; - Platforms can override this weak version if needed
  70 ;----------------------------------------------------------------
  71 WEAK(res_service)
  72         j       stext
  73 END(res_service)
  74
  75 ;----------------------------------------------------------------
  76 ; Kernel Entry point
  77 ;----------------------------------------------------------------
  78 ENTRY(stext)
  79
  80         CPU_EARLY_SETUP
  81
  82 #ifdef CONFIG_SMP
  83         GET_CPU_ID  r5
  84         cmp     r5, 0
  85         mov.nz  r0, r5
  86         bz      .Lmaster_proceed
  87
  88         ; Non-Masters wait for Master to boot enough and bring them up
  89         ; when they resume, tail-call to entry point
  90         mov     blink, @first_lines_of_secondary
  91         j       arc_platform_smp_wait_to_boot
  92
  93 .Lmaster_proceed:
  94 #endif
  95
  96         ; Clear BSS before updating any globals
  97         ; XXX: use ZOL here
  98         mov     r5, __bss_start
  99         sub     r6, __bss_stop, r5
 100         lsr.f   lp_count, r6, 2
 101         lpnz    1f
 102         st.ab   0, [r5, 4]
 103 1:
 104
 105         ; Uboot - kernel ABI
 106         ;    r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
 107         ;    r1 = magic number (always zero as of now)
 108         ;    r2 = pointer to uboot provided cmdline or external DTB in mem
 109         ; These are handled later in handle_uboot_args()
 110         st      r0, [@uboot_tag]
 111         st      r1, [@uboot_magic]
 112         st      r2, [@uboot_arg]
 113
 114         ; setup "current" tsk and optionally cache it in dedicated r25
 115         mov     r9, @init_task
 116         SET_CURR_TASK_ON_CPU  r9, r0    ; r9 = tsk, r0 = scratch
 117
 118         ; setup stack (fp, sp)
 119         mov     fp, 0
 120
 121         ; tsk->thread_info is really a PAGE, whose bottom hoists stack
 122         GET_TSK_STACK_BASE r9, sp       ; r9 = tsk, sp = stack base(output)
 123
 124         j       start_kernel    ; "C" entry point
 125 END(stext)
 126
 127 #ifdef CONFIG_SMP
 128 ;----------------------------------------------------------------
 129 ;     First lines of code run by secondary before jumping to 'C'
 130 ;----------------------------------------------------------------
 131         .section .text, "ax",@progbits
 132 ENTRY(first_lines_of_secondary)
 133
 134         ; setup per-cpu idle task as "current" on this CPU
 135         ld      r0, [@secondary_idle_tsk]
 136         SET_CURR_TASK_ON_CPU  r0, r1
 137
 138         ; setup stack (fp, sp)
 139         mov     fp, 0
 140
 141         ; set it's stack base to tsk->thread_info bottom
 142         GET_TSK_STACK_BASE r0, sp
 143
 144         j       start_kernel_secondary
 145 END(first_lines_of_secondary)
 146 #endif