arch/arc/kernel/head.S

   1 /*
   2  * ARC CPU startup Code
   3  *
   4  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Vineetg: Dec 2007
  11  *  -Check if we are running on Simulator or on real hardware
  12  *      to skip certain things during boot on simulator
  13  */
  14
  15 #include <linux/linkage.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/entry.h>
  18 #include <asm/arcregs.h>
  19 #include <asm/cache.h>
  20 #include <asm/irqflags.h>
  21
  22 .macro CPU_EARLY_SETUP
  23
  24         ; Setting up Vectror Table (in case exception happens in early boot
  25         sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
  26
  27         ; Disable I-cache/D-cache if kernel so configured
  28         lr      r5, [ARC_REG_IC_BCR]
  29         breq    r5, 0, 1f               ; I$ doesn't exist
  30         lr      r5, [ARC_REG_IC_CTRL]
  31 #ifdef CONFIG_ARC_HAS_ICACHE
  32         bclr    r5, r5, 0               ; 0 - Enable, 1 is Disable
  33 #else
  34         bset    r5, r5, 0               ; I$ exists, but is not used
  35 #endif
  36         sr      r5, [ARC_REG_IC_CTRL]
  37
  38 1:
  39         lr      r5, [ARC_REG_DC_BCR]
  40         breq    r5, 0, 1f               ; D$ doesn't exist
  41         lr      r5, [ARC_REG_DC_CTRL]
  42         bclr    r5, r5, 6               ; Invalidate (discard w/o wback)
  43 #ifdef CONFIG_ARC_HAS_DCACHE
  44         bclr    r5, r5, 0               ; Enable (+Inv)
  45 #else
  46         bset    r5, r5, 0               ; Disable (+Inv)
  47 #endif
  48         sr      r5, [ARC_REG_DC_CTRL]
  49
  50 1:
  51
  52 #ifdef CONFIG_ISA_ARCV2
  53         ; Unaligned access is disabled at reset, so re-enable early as
  54         ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access
  55         ; by default
  56         lr      r5, [status32]
  57 #ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
  58         bset    r5, r5, STATUS_AD_BIT
  59 #else
  60         ; Although disabled at reset, bootloader might have enabled it
  61         bclr    r5, r5, STATUS_AD_BIT
  62 #endif
  63         kflag   r5
  64 #endif
  65 .endm
  66
  67         .section .init.text, "ax",@progbits
  68
  69 ;----------------------------------------------------------------
  70 ; Default Reset Handler (jumped into from Reset vector)
  71 ; - Don't clobber r0,r1,r2 as they might have u-boot provided args
  72 ; - Platforms can override this weak version if needed
  73 ;----------------------------------------------------------------
  74 WEAK(res_service)
  75         j       stext
  76 END(res_service)
  77
  78 ;----------------------------------------------------------------
  79 ; Kernel Entry point
  80 ;----------------------------------------------------------------
  81 ENTRY(stext)
  82
  83         CPU_EARLY_SETUP
  84
  85 #ifdef CONFIG_SMP
  86         GET_CPU_ID  r5
  87         cmp     r5, 0
  88         mov.nz  r0, r5
  89         bz      .Lmaster_proceed
  90
  91         ; Non-Masters wait for Master to boot enough and bring them up
  92         ; when they resume, tail-call to entry point
  93         mov     blink, @first_lines_of_secondary
  94         j       arc_platform_smp_wait_to_boot
  95
  96 .Lmaster_proceed:
  97 #endif
  98
  99         ; Clear BSS before updating any globals
 100         ; XXX: use ZOL here
 101         mov     r5, __bss_start
 102         sub     r6, __bss_stop, r5
 103         lsr.f   lp_count, r6, 2
 104         lpnz    1f
 105         st.ab   0, [r5, 4]
 106 1:
 107
 108         ; Uboot - kernel ABI
 109         ;    r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
 110         ;    r1 = magic number (always zero as of now)
 111         ;    r2 = pointer to uboot provided cmdline or external DTB in mem
 112         ; These are handled later in handle_uboot_args()
 113         st      r0, [@uboot_tag]
 114         st      r1, [@uboot_magic]
 115         st      r2, [@uboot_arg]
 116
 117         ; setup "current" tsk and optionally cache it in dedicated r25
 118         mov     r9, @init_task
 119         SET_CURR_TASK_ON_CPU  r9, r0    ; r9 = tsk, r0 = scratch
 120
 121         ; setup stack (fp, sp)
 122         mov     fp, 0
 123
 124         ; tsk->thread_info is really a PAGE, whose bottom hoists stack
 125         GET_TSK_STACK_BASE r9, sp       ; r9 = tsk, sp = stack base(output)
 126
 127         j       start_kernel    ; "C" entry point
 128 END(stext)
 129
 130 #ifdef CONFIG_SMP
 131 ;----------------------------------------------------------------
 132 ;     First lines of code run by secondary before jumping to 'C'
 133 ;----------------------------------------------------------------
 134         .section .text, "ax",@progbits
 135 ENTRY(first_lines_of_secondary)
 136
 137         ; setup per-cpu idle task as "current" on this CPU
 138         ld      r0, [@secondary_idle_tsk]
 139         SET_CURR_TASK_ON_CPU  r0, r1
 140
 141         ; setup stack (fp, sp)
 142         mov     fp, 0
 143
 144         ; set it's stack base to tsk->thread_info bottom
 145         GET_TSK_STACK_BASE r0, sp
 146
 147         j       start_kernel_secondary
 148 END(first_lines_of_secondary)
 149 #endif