2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
13 #include <linux/irqdomain.h>
14 #include <linux/irqchip.h>
17 #define NR_CPU_IRQS 32 /* number of irq lines coming in */
18 #define TIMER0_IRQ 3 /* Fixed by ISA */
21 * Early Hardware specific Interrupt setup
22 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
23 * -Called very early (start_kernel -> setup_arch -> setup_processor)
26 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
28 void arc_init_IRQ(void)
32 /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
33 level_mask
|= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS
) << TIMER0_IRQ
;
36 * Write to register, even if no LV2 IRQs configured to reset it
37 * in case bootloader had mucked with it
39 write_aux_reg(AUX_IRQ_LEV
, level_mask
);
42 pr_info("Level-2 interrupts bitset %x\n", level_mask
);
46 * ARC700 core includes a simple on-chip intc supporting
47 * -per IRQ enable/disable
48 * -2 levels of interrupts (high/low)
49 * -all interrupts being level triggered
51 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
52 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
56 static void arc_irq_mask(struct irq_data
*data
)
60 ienb
= read_aux_reg(AUX_IENABLE
);
61 ienb
&= ~(1 << data
->hwirq
);
62 write_aux_reg(AUX_IENABLE
, ienb
);
65 static void arc_irq_unmask(struct irq_data
*data
)
69 ienb
= read_aux_reg(AUX_IENABLE
);
70 ienb
|= (1 << data
->hwirq
);
71 write_aux_reg(AUX_IENABLE
, ienb
);
74 static struct irq_chip onchip_intc
= {
75 .name
= "ARC In-core Intc",
76 .irq_mask
= arc_irq_mask
,
77 .irq_unmask
= arc_irq_unmask
,
80 static int arc_intc_domain_map(struct irq_domain
*d
, unsigned int irq
,
85 irq_set_percpu_devid(irq
);
86 irq_set_chip_and_handler(irq
, &onchip_intc
, handle_percpu_irq
);
89 irq_set_chip_and_handler(irq
, &onchip_intc
, handle_level_irq
);
94 static const struct irq_domain_ops arc_intc_domain_ops
= {
95 .xlate
= irq_domain_xlate_onecell
,
96 .map
= arc_intc_domain_map
,
100 init_onchip_IRQ(struct device_node
*intc
, struct device_node
*parent
)
102 struct irq_domain
*root_domain
;
105 panic("DeviceTree incore intc not a root irq controller\n");
107 root_domain
= irq_domain_add_linear(intc
, NR_CPU_IRQS
,
108 &arc_intc_domain_ops
, NULL
);
110 panic("root irq domain not avail\n");
113 * Needed for primary domain lookup to succeed
114 * This is a primary irqchip, and can never have a parent
116 irq_set_default_host(root_domain
);
121 IRQCHIP_DECLARE(arc_intc
, "snps,arc700-intc", init_onchip_IRQ
);
124 * arch_local_irq_enable - Enable interrupts.
126 * 1. Explicitly called to re-enable interrupts
127 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
128 * which maybe in hard ISR itself
130 * Semantics of this function change depending on where it is called from:
132 * -If called from hard-ISR, it must not invert interrupt priorities
133 * e.g. suppose TIMER is high priority (Level 2) IRQ
134 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
135 * Here local_irq_enable( ) shd not re-enable lower priority interrupts
136 * -If called from soft-ISR, it must re-enable all interrupts
137 * soft ISR are low prioity jobs which can be very slow, thus all IRQs
138 * must be enabled while they run.
139 * Now hardware context wise we may still be in L2 ISR (not done rtie)
140 * still we must re-enable both L1 and L2 IRQs
141 * Another twist is prev scenario with flow being
142 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
143 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
144 * over-written (this is deficiency in ARC700 Interrupt mechanism)
147 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
149 void arch_local_irq_enable(void)
151 unsigned long flags
= arch_local_save_flags();
153 if (flags
& STATUS_A2_MASK
)
154 flags
|= STATUS_E2_MASK
;
155 else if (flags
& STATUS_A1_MASK
)
156 flags
|= STATUS_E1_MASK
;
158 arch_local_irq_restore(flags
);
161 EXPORT_SYMBOL(arch_local_irq_enable
);