arch/arc/kernel/mcip.c

   1 /*
   2  * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
   3  *
   4  * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/smp.h>
  12 #include <linux/irq.h>
  13 #include <linux/spinlock.h>
  14 #include <asm/mcip.h>
  15 #include <asm/setup.h>
  16
  17 static char smp_cpuinfo_buf[128];
  18 static int idu_detected;
  19
  20 static DEFINE_RAW_SPINLOCK(mcip_lock);
  21
  22 /*
  23  * Any SMP specific init any CPU does when it comes up.
  24  * Here we setup the CPU to enable Inter-Processor-Interrupts
  25  * Called for each CPU
  26  * -Master      : init_IRQ()
  27  * -Other(s)    : start_kernel_secondary()
  28  */
  29 void mcip_init_smp(unsigned int cpu)
  30 {
  31         smp_ipi_irq_setup(cpu, IPI_IRQ);
  32 }
  33
  34 static void mcip_ipi_send(int cpu)
  35 {
  36         unsigned long flags;
  37         int ipi_was_pending;
  38
  39         /*
  40          * NOTE: We must spin here if the other cpu hasn't yet
  41          * serviced a previous message. This can burn lots
  42          * of time, but we MUST follows this protocol or
  43          * ipi messages can be lost!!!
  44          * Also, we must release the lock in this loop because
  45          * the other side may get to this same loop and not
  46          * be able to ack -- thus causing deadlock.
  47          */
  48
  49         do {
  50                 raw_spin_lock_irqsave(&mcip_lock, flags);
  51                 __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
  52                 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
  53                 if (ipi_was_pending == 0)
  54                         break; /* break out but keep lock */
  55                 raw_spin_unlock_irqrestore(&mcip_lock, flags);
  56         } while (1);
  57
  58         __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
  59         raw_spin_unlock_irqrestore(&mcip_lock, flags);
  60
  61 #ifdef CONFIG_ARC_IPI_DBG
  62         if (ipi_was_pending)
  63                 pr_info("IPI ACK delayed from cpu %d\n", cpu);
  64 #endif
  65 }
  66
  67 static void mcip_ipi_clear(int irq)
  68 {
  69         unsigned int cpu, c;
  70         unsigned long flags;
  71         unsigned int __maybe_unused copy;
  72
  73         raw_spin_lock_irqsave(&mcip_lock, flags);
  74
  75         /* Who sent the IPI */
  76         __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
  77
  78         copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK);       /* 1,2,4,8... */
  79
  80         /*
  81          * In rare case, multiple concurrent IPIs sent to same target can
  82          * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
  83          * "vectored" (multiple bits sets) as opposed to typical single bit
  84          */
  85         do {
  86                 c = __ffs(cpu);                 /* 0,1,2,3 */
  87                 __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
  88                 cpu &= ~(1U << c);
  89         } while (cpu);
  90
  91         raw_spin_unlock_irqrestore(&mcip_lock, flags);
  92
  93 #ifdef CONFIG_ARC_IPI_DBG
  94         if (c != __ffs(copy))
  95                 pr_info("IPIs from %x coalesced to %x\n",
  96                         copy, raw_smp_processor_id());
  97 #endif
  98 }
  99
 100 static void mcip_probe_n_setup(void)
 101 {
 102         struct mcip_bcr {
 103 #ifdef CONFIG_CPU_BIG_ENDIAN
 104                 unsigned int pad3:8,
 105                              idu:1, llm:1, num_cores:6,
 106                              iocoh:1,  grtc:1, dbg:1, pad2:1,
 107                              msg:1, sem:1, ipi:1, pad:1,
 108                              ver:8;
 109 #else
 110                 unsigned int ver:8,
 111                              pad:1, ipi:1, sem:1, msg:1,
 112                              pad2:1, dbg:1, grtc:1, iocoh:1,
 113                              num_cores:6, llm:1, idu:1,
 114                              pad3:8;
 115 #endif
 116         } mp;
 117
 118         READ_BCR(ARC_REG_MCIP_BCR, mp);
 119
 120         sprintf(smp_cpuinfo_buf,
 121                 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
 122                 mp.ver, mp.num_cores,
 123                 IS_AVAIL1(mp.ipi, "IPI "),
 124                 IS_AVAIL1(mp.idu, "IDU "),
 125                 IS_AVAIL1(mp.dbg, "DEBUG "),
 126                 IS_AVAIL1(mp.grtc, "GRTC"));
 127
 128         idu_detected = mp.idu;
 129
 130         if (mp.dbg) {
 131                 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
 132                 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
 133         }
 134
 135         if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
 136                 panic("kernel trying to use non-existent GRTC\n");
 137 }
 138
 139 struct plat_smp_ops plat_smp_ops = {
 140         .info           = smp_cpuinfo_buf,
 141         .init_early_smp = mcip_probe_n_setup,
 142         .ipi_send       = mcip_ipi_send,
 143         .ipi_clear      = mcip_ipi_clear,
 144 };
 145
 146 /***************************************************************************
 147  * ARCv2 Interrupt Distribution Unit (IDU)
 148  *
 149  * Connects external "COMMON" IRQs to core intc, providing:
 150  *  -dynamic routing (IRQ affinity)
 151  *  -load balancing (Round Robin interrupt distribution)
 152  *  -1:N distribution
 153  *
 154  * It physically resides in the MCIP hw block
 155  */
 156
 157 #include <linux/irqchip.h>
 158 #include <linux/of.h>
 159 #include <linux/of_irq.h>
 160
 161 /*
 162  * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
 163  */
 164 static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
 165 {
 166         __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
 167 }
 168
 169 static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
 170                            unsigned int distr)
 171 {
 172         union {
 173                 unsigned int word;
 174                 struct {
 175                         unsigned int distr:2, pad:2, lvl:1, pad2:27;
 176                 };
 177         } data;
 178
 179         data.distr = distr;
 180         data.lvl = lvl;
 181         __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
 182 }
 183
 184 static void idu_irq_mask(struct irq_data *data)
 185 {
 186         unsigned long flags;
 187
 188         raw_spin_lock_irqsave(&mcip_lock, flags);
 189         __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
 190         raw_spin_unlock_irqrestore(&mcip_lock, flags);
 191 }
 192
 193 static void idu_irq_unmask(struct irq_data *data)
 194 {
 195         unsigned long flags;
 196
 197         raw_spin_lock_irqsave(&mcip_lock, flags);
 198         __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
 199         raw_spin_unlock_irqrestore(&mcip_lock, flags);
 200 }
 201
 202 #ifdef CONFIG_SMP
 203 static int
 204 idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
 205                      bool force)
 206 {
 207         unsigned long flags;
 208         cpumask_t online;
 209
 210         /* errout if no online cpu per @cpumask */
 211         if (!cpumask_and(&online, cpumask, cpu_online_mask))
 212                 return -EINVAL;
 213
 214         raw_spin_lock_irqsave(&mcip_lock, flags);
 215
 216         idu_set_dest(data->hwirq, cpumask_bits(&online)[0]);
 217         idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
 218
 219         raw_spin_unlock_irqrestore(&mcip_lock, flags);
 220
 221         return IRQ_SET_MASK_OK;
 222 }
 223 #endif
 224
 225 static struct irq_chip idu_irq_chip = {
 226         .name                   = "MCIP IDU Intc",
 227         .irq_mask               = idu_irq_mask,
 228         .irq_unmask             = idu_irq_unmask,
 229 #ifdef CONFIG_SMP
 230         .irq_set_affinity       = idu_irq_set_affinity,
 231 #endif
 232
 233 };
 234
 235 static int idu_first_irq;
 236
 237 static void idu_cascade_isr(struct irq_desc *desc)
 238 {
 239         struct irq_domain *domain = irq_desc_get_handler_data(desc);
 240         unsigned int core_irq = irq_desc_get_irq(desc);
 241         unsigned int idu_irq;
 242
 243         idu_irq = core_irq - idu_first_irq;
 244         generic_handle_irq(irq_find_mapping(domain, idu_irq));
 245 }
 246
 247 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
 248 {
 249         irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
 250         irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
 251
 252         return 0;
 253 }
 254
 255 static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
 256                          const u32 *intspec, unsigned int intsize,
 257                          irq_hw_number_t *out_hwirq, unsigned int *out_type)
 258 {
 259         irq_hw_number_t hwirq = *out_hwirq = intspec[0];
 260         int distri = intspec[1];
 261         unsigned long flags;
 262
 263         *out_type = IRQ_TYPE_NONE;
 264
 265         /* XXX: validate distribution scheme again online cpu mask */
 266         if (distri == 0) {
 267                 /* 0 - Round Robin to all cpus, otherwise 1 bit per core */
 268                 raw_spin_lock_irqsave(&mcip_lock, flags);
 269                 idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
 270                 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
 271                 raw_spin_unlock_irqrestore(&mcip_lock, flags);
 272         } else {
 273                 /*
 274                  * DEST based distribution for Level Triggered intr can only
 275                  * have 1 CPU, so generalize it to always contain 1 cpu
 276                  */
 277                 int cpu = ffs(distri);
 278
 279                 if (cpu != fls(distri))
 280                         pr_warn("IDU irq %lx distri mode set to cpu %x\n",
 281                                 hwirq, cpu);
 282
 283                 raw_spin_lock_irqsave(&mcip_lock, flags);
 284                 idu_set_dest(hwirq, cpu);
 285                 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
 286                 raw_spin_unlock_irqrestore(&mcip_lock, flags);
 287         }
 288
 289         return 0;
 290 }
 291
 292 static const struct irq_domain_ops idu_irq_ops = {
 293         .xlate  = idu_irq_xlate,
 294         .map    = idu_irq_map,
 295 };
 296
 297 /*
 298  * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
 299  * [24, 23+C]: If C > 0 then "C" common IRQs
 300  * [24+C, N]: Not statically assigned, private-per-core
 301  */
 302
 303
 304 static int __init
 305 idu_of_init(struct device_node *intc, struct device_node *parent)
 306 {
 307         struct irq_domain *domain;
 308         /* Read IDU BCR to confirm nr_irqs */
 309         int nr_irqs = of_irq_count(intc);
 310         int i, irq;
 311
 312         if (!idu_detected)
 313                 panic("IDU not detected, but DeviceTree using it");
 314
 315         pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
 316
 317         domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
 318
 319         /* Parent interrupts (core-intc) are already mapped */
 320
 321         for (i = 0; i < nr_irqs; i++) {
 322                 /*
 323                  * Return parent uplink IRQs (towards core intc) 24,25,.....
 324                  * this step has been done before already
 325                  * however we need it to get the parent virq and set IDU handler
 326                  * as first level isr
 327                  */
 328                 irq = irq_of_parse_and_map(intc, i);
 329                 if (!i)
 330                         idu_first_irq = irq;
 331
 332                 irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain);
 333         }
 334
 335         __mcip_cmd(CMD_IDU_ENABLE, 0);
 336
 337         return 0;
 338 }
 339 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);