2 * Linux performance counter support for ARC700 series
4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
6 * This code is inspired by the perf support of various other architectures.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/errno.h>
14 #include <linux/module.h>
16 #include <linux/perf_event.h>
17 #include <linux/platform_device.h>
18 #include <asm/arcregs.h>
22 int counter_size
; /* in bits */
24 unsigned long used_mask
[BITS_TO_LONGS(ARC_PMU_MAX_HWEVENTS
)];
25 int ev_hw_idx
[PERF_COUNT_ARC_HW_MAX
];
28 /* read counter #idx; note that counter# != event# on ARC! */
29 static uint64_t arc_pmu_read_counter(int idx
)
35 * ARC supports making 'snapshots' of the counters, so we don't
36 * need to care about counters wrapping to 0 underneath our feet
38 write_aux_reg(ARC_REG_PCT_INDEX
, idx
);
39 tmp
= read_aux_reg(ARC_REG_PCT_CONTROL
);
40 write_aux_reg(ARC_REG_PCT_CONTROL
, tmp
| ARC_REG_PCT_CONTROL_SN
);
41 result
= (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH
)) << 32;
42 result
|= read_aux_reg(ARC_REG_PCT_SNAPL
);
47 static void arc_perf_event_update(struct perf_event
*event
,
48 struct hw_perf_event
*hwc
, int idx
)
50 struct arc_pmu
*arc_pmu
= container_of(event
->pmu
, struct arc_pmu
, pmu
);
51 uint64_t prev_raw_count
, new_raw_count
;
55 prev_raw_count
= local64_read(&hwc
->prev_count
);
56 new_raw_count
= arc_pmu_read_counter(idx
);
57 } while (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
58 new_raw_count
) != prev_raw_count
);
60 delta
= (new_raw_count
- prev_raw_count
) &
61 ((1ULL << arc_pmu
->counter_size
) - 1ULL);
63 local64_add(delta
, &event
->count
);
64 local64_sub(delta
, &hwc
->period_left
);
67 static void arc_pmu_read(struct perf_event
*event
)
69 arc_perf_event_update(event
, &event
->hw
, event
->hw
.idx
);
72 static int arc_pmu_cache_event(u64 config
)
74 unsigned int cache_type
, cache_op
, cache_result
;
77 cache_type
= (config
>> 0) & 0xff;
78 cache_op
= (config
>> 8) & 0xff;
79 cache_result
= (config
>> 16) & 0xff;
80 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
82 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
84 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
87 ret
= arc_pmu_cache_map
[cache_type
][cache_op
][cache_result
];
89 if (ret
== CACHE_OP_UNSUPPORTED
)
95 /* initializes hw_perf_event structure if event is supported */
96 static int arc_pmu_event_init(struct perf_event
*event
)
98 struct arc_pmu
*arc_pmu
= container_of(event
->pmu
, struct arc_pmu
, pmu
);
99 struct hw_perf_event
*hwc
= &event
->hw
;
102 /* ARC 700 PMU does not support sampling events */
103 if (is_sampling_event(event
))
106 switch (event
->attr
.type
) {
107 case PERF_TYPE_HARDWARE
:
108 if (event
->attr
.config
>= PERF_COUNT_HW_MAX
)
110 if (arc_pmu
->ev_hw_idx
[event
->attr
.config
] < 0)
112 hwc
->config
= arc_pmu
->ev_hw_idx
[event
->attr
.config
];
113 pr_debug("initializing event %d with cfg %d\n",
114 (int) event
->attr
.config
, (int) hwc
->config
);
116 case PERF_TYPE_HW_CACHE
:
117 ret
= arc_pmu_cache_event(event
->attr
.config
);
120 hwc
->config
= arc_pmu
->ev_hw_idx
[ret
];
127 /* starts all counters */
128 static void arc_pmu_enable(struct pmu
*pmu
)
131 tmp
= read_aux_reg(ARC_REG_PCT_CONTROL
);
132 write_aux_reg(ARC_REG_PCT_CONTROL
, (tmp
& 0xffff0000) | 0x1);
135 /* stops all counters */
136 static void arc_pmu_disable(struct pmu
*pmu
)
139 tmp
= read_aux_reg(ARC_REG_PCT_CONTROL
);
140 write_aux_reg(ARC_REG_PCT_CONTROL
, (tmp
& 0xffff0000) | 0x0);
144 * Assigns hardware counter to hardware condition.
145 * Note that there is no separate start/stop mechanism;
146 * stopping is achieved by assigning the 'never' condition
148 static void arc_pmu_start(struct perf_event
*event
, int flags
)
150 struct hw_perf_event
*hwc
= &event
->hw
;
153 if (WARN_ON_ONCE(idx
== -1))
156 if (flags
& PERF_EF_RELOAD
)
157 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
161 /* enable ARC pmu here */
162 write_aux_reg(ARC_REG_PCT_INDEX
, idx
);
163 write_aux_reg(ARC_REG_PCT_CONFIG
, hwc
->config
);
166 static void arc_pmu_stop(struct perf_event
*event
, int flags
)
168 struct hw_perf_event
*hwc
= &event
->hw
;
171 if (!(event
->hw
.state
& PERF_HES_STOPPED
)) {
172 /* stop ARC pmu here */
173 write_aux_reg(ARC_REG_PCT_INDEX
, idx
);
175 /* condition code #0 is always "never" */
176 write_aux_reg(ARC_REG_PCT_CONFIG
, 0);
178 event
->hw
.state
|= PERF_HES_STOPPED
;
181 if ((flags
& PERF_EF_UPDATE
) &&
182 !(event
->hw
.state
& PERF_HES_UPTODATE
)) {
183 arc_perf_event_update(event
, &event
->hw
, idx
);
184 event
->hw
.state
|= PERF_HES_UPTODATE
;
188 static void arc_pmu_del(struct perf_event
*event
, int flags
)
190 struct arc_pmu
*arc_pmu
= container_of(event
->pmu
, struct arc_pmu
, pmu
);
192 arc_pmu_stop(event
, PERF_EF_UPDATE
);
193 __clear_bit(event
->hw
.idx
, arc_pmu
->used_mask
);
195 perf_event_update_userpage(event
);
198 /* allocate hardware counter and optionally start counting */
199 static int arc_pmu_add(struct perf_event
*event
, int flags
)
201 struct arc_pmu
*arc_pmu
= container_of(event
->pmu
, struct arc_pmu
, pmu
);
202 struct hw_perf_event
*hwc
= &event
->hw
;
205 if (__test_and_set_bit(idx
, arc_pmu
->used_mask
)) {
206 idx
= find_first_zero_bit(arc_pmu
->used_mask
,
207 arc_pmu
->n_counters
);
208 if (idx
== arc_pmu
->n_counters
)
211 __set_bit(idx
, arc_pmu
->used_mask
);
215 write_aux_reg(ARC_REG_PCT_INDEX
, idx
);
216 write_aux_reg(ARC_REG_PCT_CONFIG
, 0);
217 write_aux_reg(ARC_REG_PCT_COUNTL
, 0);
218 write_aux_reg(ARC_REG_PCT_COUNTH
, 0);
219 local64_set(&hwc
->prev_count
, 0);
221 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
222 if (flags
& PERF_EF_START
)
223 arc_pmu_start(event
, PERF_EF_RELOAD
);
225 perf_event_update_userpage(event
);
230 static int arc_pmu_device_probe(struct platform_device
*pdev
)
232 struct arc_pmu
*arc_pmu
;
233 struct arc_reg_pct_build pct_bcr
;
234 struct arc_reg_cc_build cc_bcr
;
239 uint32_t word0
, word1
;
246 READ_BCR(ARC_REG_PCT_BUILD
, pct_bcr
);
248 pr_err("This core does not have performance counters!\n");
252 arc_pmu
= devm_kzalloc(&pdev
->dev
, sizeof(struct arc_pmu
),
257 arc_pmu
->n_counters
= pct_bcr
.c
;
258 BUG_ON(arc_pmu
->n_counters
> ARC_PMU_MAX_HWEVENTS
);
260 arc_pmu
->counter_size
= 32 + (pct_bcr
.s
<< 4);
261 pr_info("ARC PMU found with %d counters of size %d bits\n",
262 arc_pmu
->n_counters
, arc_pmu
->counter_size
);
264 READ_BCR(ARC_REG_CC_BUILD
, cc_bcr
);
267 pr_err("Strange! Performance counters exist, but no countable conditions?\n");
269 pr_info("ARC PMU has %d countable conditions\n", cc_bcr
.c
);
272 for (i
= 0; i
< PERF_COUNT_HW_MAX
; i
++)
273 arc_pmu
->ev_hw_idx
[i
] = -1;
275 for (j
= 0; j
< cc_bcr
.c
; j
++) {
276 write_aux_reg(ARC_REG_CC_INDEX
, j
);
277 cc_name
.indiv
.word0
= read_aux_reg(ARC_REG_CC_NAME0
);
278 cc_name
.indiv
.word1
= read_aux_reg(ARC_REG_CC_NAME1
);
279 for (i
= 0; i
< ARRAY_SIZE(arc_pmu_ev_hw_map
); i
++) {
280 if (arc_pmu_ev_hw_map
[i
] &&
281 !strcmp(arc_pmu_ev_hw_map
[i
], cc_name
.str
) &&
282 strlen(arc_pmu_ev_hw_map
[i
])) {
283 pr_debug("mapping %d to idx %d with name %s\n",
285 arc_pmu
->ev_hw_idx
[i
] = j
;
290 arc_pmu
->pmu
= (struct pmu
) {
291 .pmu_enable
= arc_pmu_enable
,
292 .pmu_disable
= arc_pmu_disable
,
293 .event_init
= arc_pmu_event_init
,
296 .start
= arc_pmu_start
,
297 .stop
= arc_pmu_stop
,
298 .read
= arc_pmu_read
,
301 ret
= perf_pmu_register(&arc_pmu
->pmu
, pdev
->name
, PERF_TYPE_RAW
);
307 static const struct of_device_id arc_pmu_match
[] = {
308 { .compatible
= "snps,arc700-pmu" },
311 MODULE_DEVICE_TABLE(of
, arc_pmu_match
);
314 static struct platform_driver arc_pmu_driver
= {
316 .name
= "arc700-pmu",
317 .of_match_table
= of_match_ptr(arc_pmu_match
),
319 .probe
= arc_pmu_device_probe
,
322 module_platform_driver(arc_pmu_driver
);
324 MODULE_LICENSE("GPL");
325 MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>");
326 MODULE_DESCRIPTION("ARC PMU driver");