arch/arc/plat-hsdk/platform.c

   1 /*
   2  * ARC HSDK Platform support code
   3  *
   4  * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/smp.h>
  13 #include <asm/arcregs.h>
  14 #include <asm/io.h>
  15 #include <asm/mach_desc.h>
  16
  17 #define ARC_CCM_UNUSED_ADDR     0x60000000
  18
  19 static void __init hsdk_init_per_cpu(unsigned int cpu)
  20 {
  21         /*
  22          * By default ICCM is mapped to 0x7z while this area is used for
  23          * kernel virtual mappings, so move it to currently unused area.
  24          */
  25         if (cpuinfo_arc700[cpu].iccm.sz)
  26                 write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
  27
  28         /*
  29          * By default DCCM is mapped to 0x8z while this area is used by kernel,
  30          * so move it to currently unused area.
  31          */
  32         if (cpuinfo_arc700[cpu].dccm.sz)
  33                 write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
  34 }
  35
  36 #define ARC_PERIPHERAL_BASE     0xf0000000
  37 #define CREG_BASE               (ARC_PERIPHERAL_BASE + 0x1000)
  38 #define CREG_PAE                (CREG_BASE + 0x180)
  39 #define CREG_PAE_UPDATE         (CREG_BASE + 0x194)
  40
  41 #define SDIO_BASE               (ARC_PERIPHERAL_BASE + 0xA000)
  42 #define SDIO_UHS_REG_EXT        (SDIO_BASE + 0x108)
  43 #define SDIO_UHS_REG_EXT_DIV_2  (2 << 30)
  44
  45 static void __init hsdk_init_early(void)
  46 {
  47         /*
  48          * PAE remapping for DMA clients does not work due to an RTL bug, so
  49          * CREG_PAE register must be programmed to all zeroes, otherwise it
  50          * will cause problems with DMA to/from peripherals even if PAE40 is
  51          * not used.
  52          */
  53
  54         /* Default is 1, which means "PAE offset = 4GByte" */
  55         writel_relaxed(0, (void __iomem *) CREG_PAE);
  56
  57         /* Really apply settings made above */
  58         writel(1, (void __iomem *) CREG_PAE_UPDATE);
  59
  60         /*
  61          * Switch SDIO external ciu clock divider from default div-by-8 to
  62          * minimum possible div-by-2.
  63          */
  64         iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
  65 }
  66
  67 static const char *hsdk_compat[] __initconst = {
  68         "snps,hsdk",
  69         NULL,
  70 };
  71
  72 MACHINE_START(SIMULATION, "hsdk")
  73         .dt_compat      = hsdk_compat,
  74         .init_early     = hsdk_init_early,
  75         .init_per_cpu   = hsdk_init_per_cpu,
  76 MACHINE_END