arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_CLOCKSOURCE_DATA
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_HARDENED_USERCOPY
  39         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  41         select HAVE_ARCH_MMAP_RND_BITS if MMU
  42         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  43         select HAVE_ARCH_TRACEHOOK
  44         select HAVE_ARM_SMCCC if CPU_V7
  45         select HAVE_CBPF_JIT
  46         select HAVE_CC_STACKPROTECTOR
  47         select HAVE_CONTEXT_TRACKING
  48         select HAVE_C_RECORDMCOUNT
  49         select HAVE_DEBUG_KMEMLEAK
  50         select HAVE_DMA_API_DEBUG
  51         select HAVE_DMA_CONTIGUOUS if MMU
  52         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  53         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  54         select HAVE_EXIT_THREAD
  55         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  56         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  57         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  58         select HAVE_GCC_PLUGINS
  59         select HAVE_GENERIC_DMA_COHERENT
  60         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  61         select HAVE_IDE if PCI || ISA || PCMCIA
  62         select HAVE_IRQ_TIME_ACCOUNTING
  63         select HAVE_KERNEL_GZIP
  64         select HAVE_KERNEL_LZ4
  65         select HAVE_KERNEL_LZMA
  66         select HAVE_KERNEL_LZO
  67         select HAVE_KERNEL_XZ
  68         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  69         select HAVE_KRETPROBES if (HAVE_KPROBES)
  70         select HAVE_MEMBLOCK
  71         select HAVE_MOD_ARCH_SPECIFIC
  72         select HAVE_NMI
  73         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  74         select HAVE_OPTPROBES if !THUMB2_KERNEL
  75         select HAVE_PERF_EVENTS
  76         select HAVE_PERF_REGS
  77         select HAVE_PERF_USER_STACK_DUMP
  78         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  79         select HAVE_REGS_AND_STACK_ACCESS_API
  80         select HAVE_SYSCALL_TRACEPOINTS
  81         select HAVE_UID16
  82         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  83         select IRQ_FORCED_THREADING
  84         select MODULES_USE_ELF_REL
  85         select NO_BOOTMEM
  86         select OF_EARLY_FLATTREE if OF
  87         select OF_RESERVED_MEM if OF
  88         select OLD_SIGACTION
  89         select OLD_SIGSUSPEND3
  90         select PERF_USE_VMALLOC
  91         select RTC_LIB
  92         select SYS_SUPPORTS_APM_EMULATION
  93         # Above selects are sorted alphabetically; please add new ones
  94         # according to that.  Thanks.
  95         help
  96           The ARM series is a line of low-power-consumption RISC chip designs
  97           licensed by ARM Ltd and targeted at embedded applications and
  98           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  99           manufactured, but legacy ARM-based PC hardware remains popular in
 100           Europe.  There is an ARM Linux project with a web page at
 101           <http://www.arm.linux.org.uk/>.
 102
 103 config ARM_HAS_SG_CHAIN
 104         select ARCH_HAS_SG_CHAIN
 105         bool
 106
 107 config NEED_SG_DMA_LENGTH
 108         bool
 109
 110 config ARM_DMA_USE_IOMMU
 111         bool
 112         select ARM_HAS_SG_CHAIN
 113         select NEED_SG_DMA_LENGTH
 114
 115 if ARM_DMA_USE_IOMMU
 116
 117 config ARM_DMA_IOMMU_ALIGNMENT
 118         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 119         range 4 9
 120         default 8
 121         help
 122           DMA mapping framework by default aligns all buffers to the smallest
 123           PAGE_SIZE order which is greater than or equal to the requested buffer
 124           size. This works well for buffers up to a few hundreds kilobytes, but
 125           for larger buffers it just a waste of address space. Drivers which has
 126           relatively small addressing window (like 64Mib) might run out of
 127           virtual space with just a few allocations.
 128
 129           With this parameter you can specify the maximum PAGE_SIZE order for
 130           DMA IOMMU buffers. Larger buffers will be aligned only to this
 131           specified order. The order is expressed as a power of two multiplied
 132           by the PAGE_SIZE.
 133
 134 endif
 135
 136 config MIGHT_HAVE_PCI
 137         bool
 138
 139 config SYS_SUPPORTS_APM_EMULATION
 140         bool
 141
 142 config HAVE_TCM
 143         bool
 144         select GENERIC_ALLOCATOR
 145
 146 config HAVE_PROC_CPU
 147         bool
 148
 149 config NO_IOPORT_MAP
 150         bool
 151
 152 config EISA
 153         bool
 154         ---help---
 155           The Extended Industry Standard Architecture (EISA) bus was
 156           developed as an open alternative to the IBM MicroChannel bus.
 157
 158           The EISA bus provided some of the features of the IBM MicroChannel
 159           bus while maintaining backward compatibility with cards made for
 160           the older ISA bus.  The EISA bus saw limited use between 1988 and
 161           1995 when it was made obsolete by the PCI bus.
 162
 163           Say Y here if you are building a kernel for an EISA-based machine.
 164
 165           Otherwise, say N.
 166
 167 config SBUS
 168         bool
 169
 170 config STACKTRACE_SUPPORT
 171         bool
 172         default y
 173
 174 config LOCKDEP_SUPPORT
 175         bool
 176         default y
 177
 178 config TRACE_IRQFLAGS_SUPPORT
 179         bool
 180         default !CPU_V7M
 181
 182 config RWSEM_XCHGADD_ALGORITHM
 183         bool
 184         default y
 185
 186 config ARCH_HAS_ILOG2_U32
 187         bool
 188
 189 config ARCH_HAS_ILOG2_U64
 190         bool
 191
 192 config ARCH_HAS_BANDGAP
 193         bool
 194
 195 config FIX_EARLYCON_MEM
 196         def_bool y if MMU
 197
 198 config GENERIC_HWEIGHT
 199         bool
 200         default y
 201
 202 config GENERIC_CALIBRATE_DELAY
 203         bool
 204         default y
 205
 206 config ARCH_MAY_HAVE_PC_FDC
 207         bool
 208
 209 config ZONE_DMA
 210         bool
 211
 212 config NEED_DMA_MAP_STATE
 213        def_bool y
 214
 215 config ARCH_SUPPORTS_UPROBES
 216         def_bool y
 217
 218 config ARCH_HAS_DMA_SET_COHERENT_MASK
 219         bool
 220
 221 config GENERIC_ISA_DMA
 222         bool
 223
 224 config FIQ
 225         bool
 226
 227 config NEED_RET_TO_USER
 228         bool
 229
 230 config ARCH_MTD_XIP
 231         bool
 232
 233 config VECTORS_BASE
 234         hex
 235         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 236         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 237         default 0x00000000
 238         help
 239           The base address of exception vectors.  This must be two pages
 240           in size.
 241
 242 config ARM_PATCH_PHYS_VIRT
 243         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 244         default y
 245         depends on !XIP_KERNEL && MMU
 246         help
 247           Patch phys-to-virt and virt-to-phys translation functions at
 248           boot and module load time according to the position of the
 249           kernel in system memory.
 250
 251           This can only be used with non-XIP MMU kernels where the base
 252           of physical memory is at a 16MB boundary.
 253
 254           Only disable this option if you know that you do not require
 255           this feature (eg, building a kernel for a single machine) and
 256           you need to shrink the kernel to the minimal size.
 257
 258 config NEED_MACH_IO_H
 259         bool
 260         help
 261           Select this when mach/io.h is required to provide special
 262           definitions for this platform.  The need for mach/io.h should
 263           be avoided when possible.
 264
 265 config NEED_MACH_MEMORY_H
 266         bool
 267         help
 268           Select this when mach/memory.h is required to provide special
 269           definitions for this platform.  The need for mach/memory.h should
 270           be avoided when possible.
 271
 272 config PHYS_OFFSET
 273         hex "Physical address of main memory" if MMU
 274         depends on !ARM_PATCH_PHYS_VIRT
 275         default DRAM_BASE if !MMU
 276         default 0x00000000 if ARCH_EBSA110 || \
 277                         ARCH_FOOTBRIDGE || \
 278                         ARCH_INTEGRATOR || \
 279                         ARCH_IOP13XX || \
 280                         ARCH_KS8695 || \
 281                         ARCH_REALVIEW
 282         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 283         default 0x20000000 if ARCH_S5PV210
 284         default 0xc0000000 if ARCH_SA1100
 285         help
 286           Please provide the physical address corresponding to the
 287           location of main memory in your system.
 288
 289 config GENERIC_BUG
 290         def_bool y
 291         depends on BUG
 292
 293 config PGTABLE_LEVELS
 294         int
 295         default 3 if ARM_LPAE
 296         default 2
 297
 298 source "init/Kconfig"
 299
 300 source "kernel/Kconfig.freezer"
 301
 302 menu "System Type"
 303
 304 config MMU
 305         bool "MMU-based Paged Memory Management Support"
 306         default y
 307         help
 308           Select if you want MMU-based virtualised addressing space
 309           support by paged memory management. If unsure, say 'Y'.
 310
 311 config ARCH_MMAP_RND_BITS_MIN
 312         default 8
 313
 314 config ARCH_MMAP_RND_BITS_MAX
 315         default 14 if PAGE_OFFSET=0x40000000
 316         default 15 if PAGE_OFFSET=0x80000000
 317         default 16
 318
 319 #
 320 # The "ARM system type" choice list is ordered alphabetically by option
 321 # text.  Please add new entries in the option alphabetic order.
 322 #
 323 choice
 324         prompt "ARM system type"
 325         default ARM_SINGLE_ARMV7M if !MMU
 326         default ARCH_MULTIPLATFORM if MMU
 327
 328 config ARCH_MULTIPLATFORM
 329         bool "Allow multiple platforms to be selected"
 330         depends on MMU
 331         select ARM_HAS_SG_CHAIN
 332         select ARM_PATCH_PHYS_VIRT
 333         select AUTO_ZRELADDR
 334         select CLKSRC_OF
 335         select COMMON_CLK
 336         select GENERIC_CLOCKEVENTS
 337         select MIGHT_HAVE_PCI
 338         select MULTI_IRQ_HANDLER
 339         select PCI_DOMAINS if PCI
 340         select SPARSE_IRQ
 341         select USE_OF
 342
 343 config ARM_SINGLE_ARMV7M
 344         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 345         depends on !MMU
 346         select ARM_NVIC
 347         select AUTO_ZRELADDR
 348         select CLKSRC_OF
 349         select COMMON_CLK
 350         select CPU_V7M
 351         select GENERIC_CLOCKEVENTS
 352         select NO_IOPORT_MAP
 353         select SPARSE_IRQ
 354         select USE_OF
 355
 356 config ARCH_GEMINI
 357         bool "Cortina Systems Gemini"
 358         select CLKSRC_MMIO
 359         select CPU_FA526
 360         select GENERIC_CLOCKEVENTS
 361         select GPIOLIB
 362         help
 363           Support for the Cortina Systems Gemini family SoCs
 364
 365 config ARCH_EBSA110
 366         bool "EBSA-110"
 367         select ARCH_USES_GETTIMEOFFSET
 368         select CPU_SA110
 369         select ISA
 370         select NEED_MACH_IO_H
 371         select NEED_MACH_MEMORY_H
 372         select NO_IOPORT_MAP
 373         help
 374           This is an evaluation board for the StrongARM processor available
 375           from Digital. It has limited hardware on-board, including an
 376           Ethernet interface, two PCMCIA sockets, two serial ports and a
 377           parallel port.
 378
 379 config ARCH_EP93XX
 380         bool "EP93xx-based"
 381         select ARCH_HAS_HOLES_MEMORYMODEL
 382         select ARM_AMBA
 383         select ARM_PATCH_PHYS_VIRT
 384         select ARM_VIC
 385         select AUTO_ZRELADDR
 386         select CLKDEV_LOOKUP
 387         select CLKSRC_MMIO
 388         select CPU_ARM920T
 389         select GENERIC_CLOCKEVENTS
 390         select GPIOLIB
 391         help
 392           This enables support for the Cirrus EP93xx series of CPUs.
 393
 394 config ARCH_FOOTBRIDGE
 395         bool "FootBridge"
 396         select CPU_SA110
 397         select FOOTBRIDGE
 398         select GENERIC_CLOCKEVENTS
 399         select HAVE_IDE
 400         select NEED_MACH_IO_H if !MMU
 401         select NEED_MACH_MEMORY_H
 402         help
 403           Support for systems based on the DC21285 companion chip
 404           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 405
 406 config ARCH_NETX
 407         bool "Hilscher NetX based"
 408         select ARM_VIC
 409         select CLKSRC_MMIO
 410         select CPU_ARM926T
 411         select GENERIC_CLOCKEVENTS
 412         help
 413           This enables support for systems based on the Hilscher NetX Soc
 414
 415 config ARCH_IOP13XX
 416         bool "IOP13xx-based"
 417         depends on MMU
 418         select CPU_XSC3
 419         select NEED_MACH_MEMORY_H
 420         select NEED_RET_TO_USER
 421         select PCI
 422         select PLAT_IOP
 423         select VMSPLIT_1G
 424         select SPARSE_IRQ
 425         help
 426           Support for Intel's IOP13XX (XScale) family of processors.
 427
 428 config ARCH_IOP32X
 429         bool "IOP32x-based"
 430         depends on MMU
 431         select CPU_XSCALE
 432         select GPIO_IOP
 433         select GPIOLIB
 434         select NEED_RET_TO_USER
 435         select PCI
 436         select PLAT_IOP
 437         help
 438           Support for Intel's 80219 and IOP32X (XScale) family of
 439           processors.
 440
 441 config ARCH_IOP33X
 442         bool "IOP33x-based"
 443         depends on MMU
 444         select CPU_XSCALE
 445         select GPIO_IOP
 446         select GPIOLIB
 447         select NEED_RET_TO_USER
 448         select PCI
 449         select PLAT_IOP
 450         help
 451           Support for Intel's IOP33X (XScale) family of processors.
 452
 453 config ARCH_IXP4XX
 454         bool "IXP4xx-based"
 455         depends on MMU
 456         select ARCH_HAS_DMA_SET_COHERENT_MASK
 457         select ARCH_SUPPORTS_BIG_ENDIAN
 458         select CLKSRC_MMIO
 459         select CPU_XSCALE
 460         select DMABOUNCE if PCI
 461         select GENERIC_CLOCKEVENTS
 462         select GPIOLIB
 463         select MIGHT_HAVE_PCI
 464         select NEED_MACH_IO_H
 465         select USB_EHCI_BIG_ENDIAN_DESC
 466         select USB_EHCI_BIG_ENDIAN_MMIO
 467         help
 468           Support for Intel's IXP4XX (XScale) family of processors.
 469
 470 config ARCH_DOVE
 471         bool "Marvell Dove"
 472         select CPU_PJ4
 473         select GENERIC_CLOCKEVENTS
 474         select GPIOLIB
 475         select MIGHT_HAVE_PCI
 476         select MULTI_IRQ_HANDLER
 477         select MVEBU_MBUS
 478         select PINCTRL
 479         select PINCTRL_DOVE
 480         select PLAT_ORION_LEGACY
 481         select SPARSE_IRQ
 482         select PM_GENERIC_DOMAINS if PM
 483         help
 484           Support for the Marvell Dove SoC 88AP510
 485
 486 config ARCH_KS8695
 487         bool "Micrel/Kendin KS8695"
 488         select CLKSRC_MMIO
 489         select CPU_ARM922T
 490         select GENERIC_CLOCKEVENTS
 491         select GPIOLIB
 492         select NEED_MACH_MEMORY_H
 493         help
 494           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 495           System-on-Chip devices.
 496
 497 config ARCH_W90X900
 498         bool "Nuvoton W90X900 CPU"
 499         select CLKDEV_LOOKUP
 500         select CLKSRC_MMIO
 501         select CPU_ARM926T
 502         select GENERIC_CLOCKEVENTS
 503         select GPIOLIB
 504         help
 505           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 506           At present, the w90x900 has been renamed nuc900, regarding
 507           the ARM series product line, you can login the following
 508           link address to know more.
 509
 510           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 511                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 512
 513 config ARCH_LPC32XX
 514         bool "NXP LPC32XX"
 515         select ARM_AMBA
 516         select CLKDEV_LOOKUP
 517         select CLKSRC_LPC32XX
 518         select COMMON_CLK
 519         select CPU_ARM926T
 520         select GENERIC_CLOCKEVENTS
 521         select GPIOLIB
 522         select MULTI_IRQ_HANDLER
 523         select SPARSE_IRQ
 524         select USE_OF
 525         help
 526           Support for the NXP LPC32XX family of processors
 527
 528 config ARCH_PXA
 529         bool "PXA2xx/PXA3xx-based"
 530         depends on MMU
 531         select ARCH_MTD_XIP
 532         select ARM_CPU_SUSPEND if PM
 533         select AUTO_ZRELADDR
 534         select COMMON_CLK
 535         select CLKDEV_LOOKUP
 536         select CLKSRC_PXA
 537         select CLKSRC_MMIO
 538         select CLKSRC_OF
 539         select CPU_XSCALE if !CPU_XSC3
 540         select GENERIC_CLOCKEVENTS
 541         select GPIO_PXA
 542         select GPIOLIB
 543         select HAVE_IDE
 544         select IRQ_DOMAIN
 545         select MULTI_IRQ_HANDLER
 546         select PLAT_PXA
 547         select SPARSE_IRQ
 548         help
 549           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 550
 551 config ARCH_RPC
 552         bool "RiscPC"
 553         depends on MMU
 554         select ARCH_ACORN
 555         select ARCH_MAY_HAVE_PC_FDC
 556         select ARCH_SPARSEMEM_ENABLE
 557         select ARCH_USES_GETTIMEOFFSET
 558         select CPU_SA110
 559         select FIQ
 560         select HAVE_IDE
 561         select HAVE_PATA_PLATFORM
 562         select ISA_DMA_API
 563         select NEED_MACH_IO_H
 564         select NEED_MACH_MEMORY_H
 565         select NO_IOPORT_MAP
 566         help
 567           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 568           CD-ROM interface, serial and parallel port, and the floppy drive.
 569
 570 config ARCH_SA1100
 571         bool "SA1100-based"
 572         select ARCH_MTD_XIP
 573         select ARCH_SPARSEMEM_ENABLE
 574         select CLKDEV_LOOKUP
 575         select CLKSRC_MMIO
 576         select CLKSRC_PXA
 577         select CLKSRC_OF if OF
 578         select CPU_FREQ
 579         select CPU_SA1100
 580         select GENERIC_CLOCKEVENTS
 581         select GPIOLIB
 582         select HAVE_IDE
 583         select IRQ_DOMAIN
 584         select ISA
 585         select MULTI_IRQ_HANDLER
 586         select NEED_MACH_MEMORY_H
 587         select SPARSE_IRQ
 588         help
 589           Support for StrongARM 11x0 based boards.
 590
 591 config ARCH_S3C24XX
 592         bool "Samsung S3C24XX SoCs"
 593         select ATAGS
 594         select CLKDEV_LOOKUP
 595         select CLKSRC_SAMSUNG_PWM
 596         select GENERIC_CLOCKEVENTS
 597         select GPIO_SAMSUNG
 598         select GPIOLIB
 599         select HAVE_S3C2410_I2C if I2C
 600         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 601         select HAVE_S3C_RTC if RTC_CLASS
 602         select MULTI_IRQ_HANDLER
 603         select NEED_MACH_IO_H
 604         select SAMSUNG_ATAGS
 605         help
 606           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 607           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 608           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 609           Samsung SMDK2410 development board (and derivatives).
 610
 611 config ARCH_DAVINCI
 612         bool "TI DaVinci"
 613         select ARCH_HAS_HOLES_MEMORYMODEL
 614         select CLKDEV_LOOKUP
 615         select CPU_ARM926T
 616         select GENERIC_ALLOCATOR
 617         select GENERIC_CLOCKEVENTS
 618         select GENERIC_IRQ_CHIP
 619         select GPIOLIB
 620         select HAVE_IDE
 621         select USE_OF
 622         select ZONE_DMA
 623         help
 624           Support for TI's DaVinci platform.
 625
 626 config ARCH_OMAP1
 627         bool "TI OMAP1"
 628         depends on MMU
 629         select ARCH_HAS_HOLES_MEMORYMODEL
 630         select ARCH_OMAP
 631         select CLKDEV_LOOKUP
 632         select CLKSRC_MMIO
 633         select GENERIC_CLOCKEVENTS
 634         select GENERIC_IRQ_CHIP
 635         select GPIOLIB
 636         select HAVE_IDE
 637         select IRQ_DOMAIN
 638         select MULTI_IRQ_HANDLER
 639         select NEED_MACH_IO_H if PCCARD
 640         select NEED_MACH_MEMORY_H
 641         select SPARSE_IRQ
 642         help
 643           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 644
 645 endchoice
 646
 647 menu "Multiple platform selection"
 648         depends on ARCH_MULTIPLATFORM
 649
 650 comment "CPU Core family selection"
 651
 652 config ARCH_MULTI_V4
 653         bool "ARMv4 based platforms (FA526)"
 654         depends on !ARCH_MULTI_V6_V7
 655         select ARCH_MULTI_V4_V5
 656         select CPU_FA526
 657
 658 config ARCH_MULTI_V4T
 659         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 660         depends on !ARCH_MULTI_V6_V7
 661         select ARCH_MULTI_V4_V5
 662         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 663                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 664                 CPU_ARM925T || CPU_ARM940T)
 665
 666 config ARCH_MULTI_V5
 667         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 668         depends on !ARCH_MULTI_V6_V7
 669         select ARCH_MULTI_V4_V5
 670         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 671                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 672                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 673
 674 config ARCH_MULTI_V4_V5
 675         bool
 676
 677 config ARCH_MULTI_V6
 678         bool "ARMv6 based platforms (ARM11)"
 679         select ARCH_MULTI_V6_V7
 680         select CPU_V6K
 681
 682 config ARCH_MULTI_V7
 683         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 684         default y
 685         select ARCH_MULTI_V6_V7
 686         select CPU_V7
 687         select HAVE_SMP
 688
 689 config ARCH_MULTI_V6_V7
 690         bool
 691         select MIGHT_HAVE_CACHE_L2X0
 692
 693 config ARCH_MULTI_CPU_AUTO
 694         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 695         select ARCH_MULTI_V5
 696
 697 endmenu
 698
 699 config ARCH_VIRT
 700         bool "Dummy Virtual Machine"
 701         depends on ARCH_MULTI_V7
 702         select ARM_AMBA
 703         select ARM_GIC
 704         select ARM_GIC_V2M if PCI
 705         select ARM_GIC_V3
 706         select ARM_GIC_V3_ITS if PCI
 707         select ARM_PSCI
 708         select HAVE_ARM_ARCH_TIMER
 709
 710 #
 711 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 712 # Kconfigs may be included either alphabetically (according to the
 713 # plat- suffix) or along side the corresponding mach-* source.
 714 #
 715 source "arch/arm/mach-mvebu/Kconfig"
 716
 717 source "arch/arm/mach-alpine/Kconfig"
 718
 719 source "arch/arm/mach-artpec/Kconfig"
 720
 721 source "arch/arm/mach-asm9260/Kconfig"
 722
 723 source "arch/arm/mach-at91/Kconfig"
 724
 725 source "arch/arm/mach-axxia/Kconfig"
 726
 727 source "arch/arm/mach-bcm/Kconfig"
 728
 729 source "arch/arm/mach-berlin/Kconfig"
 730
 731 source "arch/arm/mach-clps711x/Kconfig"
 732
 733 source "arch/arm/mach-cns3xxx/Kconfig"
 734
 735 source "arch/arm/mach-davinci/Kconfig"
 736
 737 source "arch/arm/mach-digicolor/Kconfig"
 738
 739 source "arch/arm/mach-dove/Kconfig"
 740
 741 source "arch/arm/mach-ep93xx/Kconfig"
 742
 743 source "arch/arm/mach-footbridge/Kconfig"
 744
 745 source "arch/arm/mach-gemini/Kconfig"
 746
 747 source "arch/arm/mach-highbank/Kconfig"
 748
 749 source "arch/arm/mach-hisi/Kconfig"
 750
 751 source "arch/arm/mach-integrator/Kconfig"
 752
 753 source "arch/arm/mach-iop32x/Kconfig"
 754
 755 source "arch/arm/mach-iop33x/Kconfig"
 756
 757 source "arch/arm/mach-iop13xx/Kconfig"
 758
 759 source "arch/arm/mach-ixp4xx/Kconfig"
 760
 761 source "arch/arm/mach-keystone/Kconfig"
 762
 763 source "arch/arm/mach-ks8695/Kconfig"
 764
 765 source "arch/arm/mach-meson/Kconfig"
 766
 767 source "arch/arm/mach-moxart/Kconfig"
 768
 769 source "arch/arm/mach-aspeed/Kconfig"
 770
 771 source "arch/arm/mach-mv78xx0/Kconfig"
 772
 773 source "arch/arm/mach-imx/Kconfig"
 774
 775 source "arch/arm/mach-mediatek/Kconfig"
 776
 777 source "arch/arm/mach-mxs/Kconfig"
 778
 779 source "arch/arm/mach-netx/Kconfig"
 780
 781 source "arch/arm/mach-nomadik/Kconfig"
 782
 783 source "arch/arm/mach-nspire/Kconfig"
 784
 785 source "arch/arm/plat-omap/Kconfig"
 786
 787 source "arch/arm/mach-omap1/Kconfig"
 788
 789 source "arch/arm/mach-omap2/Kconfig"
 790
 791 source "arch/arm/mach-orion5x/Kconfig"
 792
 793 source "arch/arm/mach-picoxcell/Kconfig"
 794
 795 source "arch/arm/mach-pxa/Kconfig"
 796 source "arch/arm/plat-pxa/Kconfig"
 797
 798 source "arch/arm/mach-mmp/Kconfig"
 799
 800 source "arch/arm/mach-oxnas/Kconfig"
 801
 802 source "arch/arm/mach-qcom/Kconfig"
 803
 804 source "arch/arm/mach-realview/Kconfig"
 805
 806 source "arch/arm/mach-rockchip/Kconfig"
 807
 808 source "arch/arm/mach-sa1100/Kconfig"
 809
 810 source "arch/arm/mach-socfpga/Kconfig"
 811
 812 source "arch/arm/mach-spear/Kconfig"
 813
 814 source "arch/arm/mach-sti/Kconfig"
 815
 816 source "arch/arm/mach-s3c24xx/Kconfig"
 817
 818 source "arch/arm/mach-s3c64xx/Kconfig"
 819
 820 source "arch/arm/mach-s5pv210/Kconfig"
 821
 822 source "arch/arm/mach-exynos/Kconfig"
 823 source "arch/arm/plat-samsung/Kconfig"
 824
 825 source "arch/arm/mach-shmobile/Kconfig"
 826
 827 source "arch/arm/mach-sunxi/Kconfig"
 828
 829 source "arch/arm/mach-prima2/Kconfig"
 830
 831 source "arch/arm/mach-tango/Kconfig"
 832
 833 source "arch/arm/mach-tegra/Kconfig"
 834
 835 source "arch/arm/mach-u300/Kconfig"
 836
 837 source "arch/arm/mach-uniphier/Kconfig"
 838
 839 source "arch/arm/mach-ux500/Kconfig"
 840
 841 source "arch/arm/mach-versatile/Kconfig"
 842
 843 source "arch/arm/mach-vexpress/Kconfig"
 844 source "arch/arm/plat-versatile/Kconfig"
 845
 846 source "arch/arm/mach-vt8500/Kconfig"
 847
 848 source "arch/arm/mach-w90x900/Kconfig"
 849
 850 source "arch/arm/mach-zx/Kconfig"
 851
 852 source "arch/arm/mach-zynq/Kconfig"
 853
 854 # ARMv7-M architecture
 855 config ARCH_EFM32
 856         bool "Energy Micro efm32"
 857         depends on ARM_SINGLE_ARMV7M
 858         select GPIOLIB
 859         help
 860           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 861           processors.
 862
 863 config ARCH_LPC18XX
 864         bool "NXP LPC18xx/LPC43xx"
 865         depends on ARM_SINGLE_ARMV7M
 866         select ARCH_HAS_RESET_CONTROLLER
 867         select ARM_AMBA
 868         select CLKSRC_LPC32XX
 869         select PINCTRL
 870         help
 871           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 872           high performance microcontrollers.
 873
 874 config ARCH_STM32
 875         bool "STMicrolectronics STM32"
 876         depends on ARM_SINGLE_ARMV7M
 877         select ARCH_HAS_RESET_CONTROLLER
 878         select ARMV7M_SYSTICK
 879         select CLKSRC_STM32
 880         select PINCTRL
 881         select RESET_CONTROLLER
 882         select STM32_EXTI
 883         help
 884           Support for STMicroelectronics STM32 processors.
 885
 886 config MACH_STM32F429
 887         bool "STMicrolectronics STM32F429"
 888         depends on ARCH_STM32
 889         default y
 890
 891 config MACH_STM32F746
 892         bool "STMicrolectronics STM32F746"
 893         depends on ARCH_STM32
 894         default y
 895
 896 config ARCH_MPS2
 897         bool "ARM MPS2 platform"
 898         depends on ARM_SINGLE_ARMV7M
 899         select ARM_AMBA
 900         select CLKSRC_MPS2
 901         help
 902           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 903           with a range of available cores like Cortex-M3/M4/M7.
 904
 905           Please, note that depends which Application Note is used memory map
 906           for the platform may vary, so adjustment of RAM base might be needed.
 907
 908 # Definitions to make life easier
 909 config ARCH_ACORN
 910         bool
 911
 912 config PLAT_IOP
 913         bool
 914         select GENERIC_CLOCKEVENTS
 915
 916 config PLAT_ORION
 917         bool
 918         select CLKSRC_MMIO
 919         select COMMON_CLK
 920         select GENERIC_IRQ_CHIP
 921         select IRQ_DOMAIN
 922
 923 config PLAT_ORION_LEGACY
 924         bool
 925         select PLAT_ORION
 926
 927 config PLAT_PXA
 928         bool
 929
 930 config PLAT_VERSATILE
 931         bool
 932
 933 source "arch/arm/firmware/Kconfig"
 934
 935 source arch/arm/mm/Kconfig
 936
 937 config IWMMXT
 938         bool "Enable iWMMXt support"
 939         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 940         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 941         help
 942           Enable support for iWMMXt context switching at run time if
 943           running on a CPU that supports it.
 944
 945 config MULTI_IRQ_HANDLER
 946         bool
 947         help
 948           Allow each machine to specify it's own IRQ handler at run time.
 949
 950 if !MMU
 951 source "arch/arm/Kconfig-nommu"
 952 endif
 953
 954 config PJ4B_ERRATA_4742
 955         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 956         depends on CPU_PJ4B && MACH_ARMADA_370
 957         default y
 958         help
 959           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 960           Event (WFE) IDLE states, a specific timing sensitivity exists between
 961           the retiring WFI/WFE instructions and the newly issued subsequent
 962           instructions.  This sensitivity can result in a CPU hang scenario.
 963           Workaround:
 964           The software must insert either a Data Synchronization Barrier (DSB)
 965           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 966           instruction
 967
 968 config ARM_ERRATA_326103
 969         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 970         depends on CPU_V6
 971         help
 972           Executing a SWP instruction to read-only memory does not set bit 11
 973           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 974           treat the access as a read, preventing a COW from occurring and
 975           causing the faulting task to livelock.
 976
 977 config ARM_ERRATA_411920
 978         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 979         depends on CPU_V6 || CPU_V6K
 980         help
 981           Invalidation of the Instruction Cache operation can
 982           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 983           It does not affect the MPCore. This option enables the ARM Ltd.
 984           recommended workaround.
 985
 986 config ARM_ERRATA_430973
 987         bool "ARM errata: Stale prediction on replaced interworking branch"
 988         depends on CPU_V7
 989         help
 990           This option enables the workaround for the 430973 Cortex-A8
 991           r1p* erratum. If a code sequence containing an ARM/Thumb
 992           interworking branch is replaced with another code sequence at the
 993           same virtual address, whether due to self-modifying code or virtual
 994           to physical address re-mapping, Cortex-A8 does not recover from the
 995           stale interworking branch prediction. This results in Cortex-A8
 996           executing the new code sequence in the incorrect ARM or Thumb state.
 997           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 998           and also flushes the branch target cache at every context switch.
 999           Note that setting specific bits in the ACTLR register may not be
1000           available in non-secure mode.
1001
1002 config ARM_ERRATA_458693
1003         bool "ARM errata: Processor deadlock when a false hazard is created"
1004         depends on CPU_V7
1005         depends on !ARCH_MULTIPLATFORM
1006         help
1007           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1008           erratum. For very specific sequences of memory operations, it is
1009           possible for a hazard condition intended for a cache line to instead
1010           be incorrectly associated with a different cache line. This false
1011           hazard might then cause a processor deadlock. The workaround enables
1012           the L1 caching of the NEON accesses and disables the PLD instruction
1013           in the ACTLR register. Note that setting specific bits in the ACTLR
1014           register may not be available in non-secure mode.
1015
1016 config ARM_ERRATA_460075
1017         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1018         depends on CPU_V7
1019         depends on !ARCH_MULTIPLATFORM
1020         help
1021           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1022           erratum. Any asynchronous access to the L2 cache may encounter a
1023           situation in which recent store transactions to the L2 cache are lost
1024           and overwritten with stale memory contents from external memory. The
1025           workaround disables the write-allocate mode for the L2 cache via the
1026           ACTLR register. Note that setting specific bits in the ACTLR register
1027           may not be available in non-secure mode.
1028
1029 config ARM_ERRATA_742230
1030         bool "ARM errata: DMB operation may be faulty"
1031         depends on CPU_V7 && SMP
1032         depends on !ARCH_MULTIPLATFORM
1033         help
1034           This option enables the workaround for the 742230 Cortex-A9
1035           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1036           between two write operations may not ensure the correct visibility
1037           ordering of the two writes. This workaround sets a specific bit in
1038           the diagnostic register of the Cortex-A9 which causes the DMB
1039           instruction to behave as a DSB, ensuring the correct behaviour of
1040           the two writes.
1041
1042 config ARM_ERRATA_742231
1043         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1044         depends on CPU_V7 && SMP
1045         depends on !ARCH_MULTIPLATFORM
1046         help
1047           This option enables the workaround for the 742231 Cortex-A9
1048           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1049           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1050           accessing some data located in the same cache line, may get corrupted
1051           data due to bad handling of the address hazard when the line gets
1052           replaced from one of the CPUs at the same time as another CPU is
1053           accessing it. This workaround sets specific bits in the diagnostic
1054           register of the Cortex-A9 which reduces the linefill issuing
1055           capabilities of the processor.
1056
1057 config ARM_ERRATA_643719
1058         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1059         depends on CPU_V7 && SMP
1060         default y
1061         help
1062           This option enables the workaround for the 643719 Cortex-A9 (prior to
1063           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1064           register returns zero when it should return one. The workaround
1065           corrects this value, ensuring cache maintenance operations which use
1066           it behave as intended and avoiding data corruption.
1067
1068 config ARM_ERRATA_720789
1069         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1070         depends on CPU_V7
1071         help
1072           This option enables the workaround for the 720789 Cortex-A9 (prior to
1073           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1074           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1075           As a consequence of this erratum, some TLB entries which should be
1076           invalidated are not, resulting in an incoherency in the system page
1077           tables. The workaround changes the TLB flushing routines to invalidate
1078           entries regardless of the ASID.
1079
1080 config ARM_ERRATA_743622
1081         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1082         depends on CPU_V7
1083         depends on !ARCH_MULTIPLATFORM
1084         help
1085           This option enables the workaround for the 743622 Cortex-A9
1086           (r2p*) erratum. Under very rare conditions, a faulty
1087           optimisation in the Cortex-A9 Store Buffer may lead to data
1088           corruption. This workaround sets a specific bit in the diagnostic
1089           register of the Cortex-A9 which disables the Store Buffer
1090           optimisation, preventing the defect from occurring. This has no
1091           visible impact on the overall performance or power consumption of the
1092           processor.
1093
1094 config ARM_ERRATA_751472
1095         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1096         depends on CPU_V7
1097         depends on !ARCH_MULTIPLATFORM
1098         help
1099           This option enables the workaround for the 751472 Cortex-A9 (prior
1100           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1101           completion of a following broadcasted operation if the second
1102           operation is received by a CPU before the ICIALLUIS has completed,
1103           potentially leading to corrupted entries in the cache or TLB.
1104
1105 config ARM_ERRATA_754322
1106         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1107         depends on CPU_V7
1108         help
1109           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1110           r3p*) erratum. A speculative memory access may cause a page table walk
1111           which starts prior to an ASID switch but completes afterwards. This
1112           can populate the micro-TLB with a stale entry which may be hit with
1113           the new ASID. This workaround places two dsb instructions in the mm
1114           switching code so that no page table walks can cross the ASID switch.
1115
1116 config ARM_ERRATA_754327
1117         bool "ARM errata: no automatic Store Buffer drain"
1118         depends on CPU_V7 && SMP
1119         help
1120           This option enables the workaround for the 754327 Cortex-A9 (prior to
1121           r2p0) erratum. The Store Buffer does not have any automatic draining
1122           mechanism and therefore a livelock may occur if an external agent
1123           continuously polls a memory location waiting to observe an update.
1124           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1125           written polling loops from denying visibility of updates to memory.
1126
1127 config ARM_ERRATA_364296
1128         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1129         depends on CPU_V6
1130         help
1131           This options enables the workaround for the 364296 ARM1136
1132           r0p2 erratum (possible cache data corruption with
1133           hit-under-miss enabled). It sets the undocumented bit 31 in
1134           the auxiliary control register and the FI bit in the control
1135           register, thus disabling hit-under-miss without putting the
1136           processor into full low interrupt latency mode. ARM11MPCore
1137           is not affected.
1138
1139 config ARM_ERRATA_764369
1140         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1141         depends on CPU_V7 && SMP
1142         help
1143           This option enables the workaround for erratum 764369
1144           affecting Cortex-A9 MPCore with two or more processors (all
1145           current revisions). Under certain timing circumstances, a data
1146           cache line maintenance operation by MVA targeting an Inner
1147           Shareable memory region may fail to proceed up to either the
1148           Point of Coherency or to the Point of Unification of the
1149           system. This workaround adds a DSB instruction before the
1150           relevant cache maintenance functions and sets a specific bit
1151           in the diagnostic control register of the SCU.
1152
1153 config ARM_ERRATA_775420
1154        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1155        depends on CPU_V7
1156        help
1157          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1158          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1159          operation aborts with MMU exception, it might cause the processor
1160          to deadlock. This workaround puts DSB before executing ISB if
1161          an abort may occur on cache maintenance.
1162
1163 config ARM_ERRATA_798181
1164         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1165         depends on CPU_V7 && SMP
1166         help
1167           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1168           adequately shooting down all use of the old entries. This
1169           option enables the Linux kernel workaround for this erratum
1170           which sends an IPI to the CPUs that are running the same ASID
1171           as the one being invalidated.
1172
1173 config ARM_ERRATA_773022
1174         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1175         depends on CPU_V7
1176         help
1177           This option enables the workaround for the 773022 Cortex-A15
1178           (up to r0p4) erratum. In certain rare sequences of code, the
1179           loop buffer may deliver incorrect instructions. This
1180           workaround disables the loop buffer to avoid the erratum.
1181
1182 config ARM_ERRATA_818325_852422
1183         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1184         depends on CPU_V7
1185         help
1186           This option enables the workaround for:
1187           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1188             instruction might deadlock.  Fixed in r0p1.
1189           - Cortex-A12 852422: Execution of a sequence of instructions might
1190             lead to either a data corruption or a CPU deadlock.  Not fixed in
1191             any Cortex-A12 cores yet.
1192           This workaround for all both errata involves setting bit[12] of the
1193           Feature Register. This bit disables an optimisation applied to a
1194           sequence of 2 instructions that use opposing condition codes.
1195
1196 config ARM_ERRATA_821420
1197         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1198         depends on CPU_V7
1199         help
1200           This option enables the workaround for the 821420 Cortex-A12
1201           (all revs) erratum. In very rare timing conditions, a sequence
1202           of VMOV to Core registers instructions, for which the second
1203           one is in the shadow of a branch or abort, can lead to a
1204           deadlock when the VMOV instructions are issued out-of-order.
1205
1206 config ARM_ERRATA_825619
1207         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1208         depends on CPU_V7
1209         help
1210           This option enables the workaround for the 825619 Cortex-A12
1211           (all revs) erratum. Within rare timing constraints, executing a
1212           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1213           and Device/Strongly-Ordered loads and stores might cause deadlock
1214
1215 config ARM_ERRATA_852421
1216         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1217         depends on CPU_V7
1218         help
1219           This option enables the workaround for the 852421 Cortex-A17
1220           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1221           execution of a DMB ST instruction might fail to properly order
1222           stores from GroupA and stores from GroupB.
1223
1224 config ARM_ERRATA_852423
1225         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1226         depends on CPU_V7
1227         help
1228           This option enables the workaround for:
1229           - Cortex-A17 852423: Execution of a sequence of instructions might
1230             lead to either a data corruption or a CPU deadlock.  Not fixed in
1231             any Cortex-A17 cores yet.
1232           This is identical to Cortex-A12 erratum 852422.  It is a separate
1233           config option from the A12 erratum due to the way errata are checked
1234           for and handled.
1235
1236 endmenu
1237
1238 source "arch/arm/common/Kconfig"
1239
1240 menu "Bus support"
1241
1242 config ISA
1243         bool
1244         help
1245           Find out whether you have ISA slots on your motherboard.  ISA is the
1246           name of a bus system, i.e. the way the CPU talks to the other stuff
1247           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1248           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1249           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1250
1251 # Select ISA DMA controller support
1252 config ISA_DMA
1253         bool
1254         select ISA_DMA_API
1255
1256 # Select ISA DMA interface
1257 config ISA_DMA_API
1258         bool
1259
1260 config PCI
1261         bool "PCI support" if MIGHT_HAVE_PCI
1262         help
1263           Find out whether you have a PCI motherboard. PCI is the name of a
1264           bus system, i.e. the way the CPU talks to the other stuff inside
1265           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1266           VESA. If you have PCI, say Y, otherwise N.
1267
1268 config PCI_DOMAINS
1269         bool
1270         depends on PCI
1271
1272 config PCI_DOMAINS_GENERIC
1273         def_bool PCI_DOMAINS
1274
1275 config PCI_NANOENGINE
1276         bool "BSE nanoEngine PCI support"
1277         depends on SA1100_NANOENGINE
1278         help
1279           Enable PCI on the BSE nanoEngine board.
1280
1281 config PCI_SYSCALL
1282         def_bool PCI
1283
1284 config PCI_HOST_ITE8152
1285         bool
1286         depends on PCI && MACH_ARMCORE
1287         default y
1288         select DMABOUNCE
1289
1290 source "drivers/pci/Kconfig"
1291
1292 source "drivers/pcmcia/Kconfig"
1293
1294 endmenu
1295
1296 menu "Kernel Features"
1297
1298 config HAVE_SMP
1299         bool
1300         help
1301           This option should be selected by machines which have an SMP-
1302           capable CPU.
1303
1304           The only effect of this option is to make the SMP-related
1305           options available to the user for configuration.
1306
1307 config SMP
1308         bool "Symmetric Multi-Processing"
1309         depends on CPU_V6K || CPU_V7
1310         depends on GENERIC_CLOCKEVENTS
1311         depends on HAVE_SMP
1312         depends on MMU || ARM_MPU
1313         select IRQ_WORK
1314         help
1315           This enables support for systems with more than one CPU. If you have
1316           a system with only one CPU, say N. If you have a system with more
1317           than one CPU, say Y.
1318
1319           If you say N here, the kernel will run on uni- and multiprocessor
1320           machines, but will use only one CPU of a multiprocessor machine. If
1321           you say Y here, the kernel will run on many, but not all,
1322           uniprocessor machines. On a uniprocessor machine, the kernel
1323           will run faster if you say N here.
1324
1325           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1326           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1327           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1328
1329           If you don't know what to do here, say N.
1330
1331 config SMP_ON_UP
1332         bool "Allow booting SMP kernel on uniprocessor systems"
1333         depends on SMP && !XIP_KERNEL && MMU
1334         default y
1335         help
1336           SMP kernels contain instructions which fail on non-SMP processors.
1337           Enabling this option allows the kernel to modify itself to make
1338           these instructions safe.  Disabling it allows about 1K of space
1339           savings.
1340
1341           If you don't know what to do here, say Y.
1342
1343 config ARM_CPU_TOPOLOGY
1344         bool "Support cpu topology definition"
1345         depends on SMP && CPU_V7
1346         default y
1347         help
1348           Support ARM cpu topology definition. The MPIDR register defines
1349           affinity between processors which is then used to describe the cpu
1350           topology of an ARM System.
1351
1352 config SCHED_MC
1353         bool "Multi-core scheduler support"
1354         depends on ARM_CPU_TOPOLOGY
1355         help
1356           Multi-core scheduler support improves the CPU scheduler's decision
1357           making when dealing with multi-core CPU chips at a cost of slightly
1358           increased overhead in some places. If unsure say N here.
1359
1360 config SCHED_SMT
1361         bool "SMT scheduler support"
1362         depends on ARM_CPU_TOPOLOGY
1363         help
1364           Improves the CPU scheduler's decision making when dealing with
1365           MultiThreading at a cost of slightly increased overhead in some
1366           places. If unsure say N here.
1367
1368 config HAVE_ARM_SCU
1369         bool
1370         help
1371           This option enables support for the ARM system coherency unit
1372
1373 config HAVE_ARM_ARCH_TIMER
1374         bool "Architected timer support"
1375         depends on CPU_V7
1376         select ARM_ARCH_TIMER
1377         select GENERIC_CLOCKEVENTS
1378         help
1379           This option enables support for the ARM architected timer
1380
1381 config HAVE_ARM_TWD
1382         bool
1383         select CLKSRC_OF if OF
1384         help
1385           This options enables support for the ARM timer and watchdog unit
1386
1387 config MCPM
1388         bool "Multi-Cluster Power Management"
1389         depends on CPU_V7 && SMP
1390         help
1391           This option provides the common power management infrastructure
1392           for (multi-)cluster based systems, such as big.LITTLE based
1393           systems.
1394
1395 config MCPM_QUAD_CLUSTER
1396         bool
1397         depends on MCPM
1398         help
1399           To avoid wasting resources unnecessarily, MCPM only supports up
1400           to 2 clusters by default.
1401           Platforms with 3 or 4 clusters that use MCPM must select this
1402           option to allow the additional clusters to be managed.
1403
1404 config BIG_LITTLE
1405         bool "big.LITTLE support (Experimental)"
1406         depends on CPU_V7 && SMP
1407         select MCPM
1408         help
1409           This option enables support selections for the big.LITTLE
1410           system architecture.
1411
1412 config BL_SWITCHER
1413         bool "big.LITTLE switcher support"
1414         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1415         select CPU_PM
1416         help
1417           The big.LITTLE "switcher" provides the core functionality to
1418           transparently handle transition between a cluster of A15's
1419           and a cluster of A7's in a big.LITTLE system.
1420
1421 config BL_SWITCHER_DUMMY_IF
1422         tristate "Simple big.LITTLE switcher user interface"
1423         depends on BL_SWITCHER && DEBUG_KERNEL
1424         help
1425           This is a simple and dummy char dev interface to control
1426           the big.LITTLE switcher core code.  It is meant for
1427           debugging purposes only.
1428
1429 choice
1430         prompt "Memory split"
1431         depends on MMU
1432         default VMSPLIT_3G
1433         help
1434           Select the desired split between kernel and user memory.
1435
1436           If you are not absolutely sure what you are doing, leave this
1437           option alone!
1438
1439         config VMSPLIT_3G
1440                 bool "3G/1G user/kernel split"
1441         config VMSPLIT_3G_OPT
1442                 bool "3G/1G user/kernel split (for full 1G low memory)"
1443         config VMSPLIT_2G
1444                 bool "2G/2G user/kernel split"
1445         config VMSPLIT_1G
1446                 bool "1G/3G user/kernel split"
1447 endchoice
1448
1449 config PAGE_OFFSET
1450         hex
1451         default PHYS_OFFSET if !MMU
1452         default 0x40000000 if VMSPLIT_1G
1453         default 0x80000000 if VMSPLIT_2G
1454         default 0xB0000000 if VMSPLIT_3G_OPT
1455         default 0xC0000000
1456
1457 config NR_CPUS
1458         int "Maximum number of CPUs (2-32)"
1459         range 2 32
1460         depends on SMP
1461         default "4"
1462
1463 config HOTPLUG_CPU
1464         bool "Support for hot-pluggable CPUs"
1465         depends on SMP
1466         help
1467           Say Y here to experiment with turning CPUs off and on.  CPUs
1468           can be controlled through /sys/devices/system/cpu.
1469
1470 config ARM_PSCI
1471         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1472         depends on HAVE_ARM_SMCCC
1473         select ARM_PSCI_FW
1474         help
1475           Say Y here if you want Linux to communicate with system firmware
1476           implementing the PSCI specification for CPU-centric power
1477           management operations described in ARM document number ARM DEN
1478           0022A ("Power State Coordination Interface System Software on
1479           ARM processors").
1480
1481 # The GPIO number here must be sorted by descending number. In case of
1482 # a multiplatform kernel, we just want the highest value required by the
1483 # selected platforms.
1484 config ARCH_NR_GPIO
1485         int
1486         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1487                 ARCH_ZYNQ
1488         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1489                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1490         default 416 if ARCH_SUNXI
1491         default 392 if ARCH_U8500
1492         default 352 if ARCH_VT8500
1493         default 288 if ARCH_ROCKCHIP
1494         default 264 if MACH_H4700
1495         default 0
1496         help
1497           Maximum number of GPIOs in the system.
1498
1499           If unsure, leave the default value.
1500
1501 source kernel/Kconfig.preempt
1502
1503 config HZ_FIXED
1504         int
1505         default 200 if ARCH_EBSA110
1506         default 128 if SOC_AT91RM9200
1507         default 0
1508
1509 choice
1510         depends on HZ_FIXED = 0
1511         prompt "Timer frequency"
1512
1513 config HZ_100
1514         bool "100 Hz"
1515
1516 config HZ_200
1517         bool "200 Hz"
1518
1519 config HZ_250
1520         bool "250 Hz"
1521
1522 config HZ_300
1523         bool "300 Hz"
1524
1525 config HZ_500
1526         bool "500 Hz"
1527
1528 config HZ_1000
1529         bool "1000 Hz"
1530
1531 endchoice
1532
1533 config HZ
1534         int
1535         default HZ_FIXED if HZ_FIXED != 0
1536         default 100 if HZ_100
1537         default 200 if HZ_200
1538         default 250 if HZ_250
1539         default 300 if HZ_300
1540         default 500 if HZ_500
1541         default 1000
1542
1543 config SCHED_HRTICK
1544         def_bool HIGH_RES_TIMERS
1545
1546 config THUMB2_KERNEL
1547         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1548         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1549         default y if CPU_THUMBONLY
1550         select AEABI
1551         select ARM_ASM_UNIFIED
1552         select ARM_UNWIND
1553         help
1554           By enabling this option, the kernel will be compiled in
1555           Thumb-2 mode. A compiler/assembler that understand the unified
1556           ARM-Thumb syntax is needed.
1557
1558           If unsure, say N.
1559
1560 config THUMB2_AVOID_R_ARM_THM_JUMP11
1561         bool "Work around buggy Thumb-2 short branch relocations in gas"
1562         depends on THUMB2_KERNEL && MODULES
1563         default y
1564         help
1565           Various binutils versions can resolve Thumb-2 branches to
1566           locally-defined, preemptible global symbols as short-range "b.n"
1567           branch instructions.
1568
1569           This is a problem, because there's no guarantee the final
1570           destination of the symbol, or any candidate locations for a
1571           trampoline, are within range of the branch.  For this reason, the
1572           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1573           relocation in modules at all, and it makes little sense to add
1574           support.
1575
1576           The symptom is that the kernel fails with an "unsupported
1577           relocation" error when loading some modules.
1578
1579           Until fixed tools are available, passing
1580           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1581           code which hits this problem, at the cost of a bit of extra runtime
1582           stack usage in some cases.
1583
1584           The problem is described in more detail at:
1585               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1586
1587           Only Thumb-2 kernels are affected.
1588
1589           Unless you are sure your tools don't have this problem, say Y.
1590
1591 config ARM_ASM_UNIFIED
1592         bool
1593
1594 config ARM_PATCH_IDIV
1595         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1596         depends on CPU_32v7 && !XIP_KERNEL
1597         default y
1598         help
1599           The ARM compiler inserts calls to __aeabi_idiv() and
1600           __aeabi_uidiv() when it needs to perform division on signed
1601           and unsigned integers. Some v7 CPUs have support for the sdiv
1602           and udiv instructions that can be used to implement those
1603           functions.
1604
1605           Enabling this option allows the kernel to modify itself to
1606           replace the first two instructions of these library functions
1607           with the sdiv or udiv plus "bx lr" instructions when the CPU
1608           it is running on supports them. Typically this will be faster
1609           and less power intensive than running the original library
1610           code to do integer division.
1611
1612 config AEABI
1613         bool "Use the ARM EABI to compile the kernel"
1614         help
1615           This option allows for the kernel to be compiled using the latest
1616           ARM ABI (aka EABI).  This is only useful if you are using a user
1617           space environment that is also compiled with EABI.
1618
1619           Since there are major incompatibilities between the legacy ABI and
1620           EABI, especially with regard to structure member alignment, this
1621           option also changes the kernel syscall calling convention to
1622           disambiguate both ABIs and allow for backward compatibility support
1623           (selected with CONFIG_OABI_COMPAT).
1624
1625           To use this you need GCC version 4.0.0 or later.
1626
1627 config OABI_COMPAT
1628         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1629         depends on AEABI && !THUMB2_KERNEL
1630         help
1631           This option preserves the old syscall interface along with the
1632           new (ARM EABI) one. It also provides a compatibility layer to
1633           intercept syscalls that have structure arguments which layout
1634           in memory differs between the legacy ABI and the new ARM EABI
1635           (only for non "thumb" binaries). This option adds a tiny
1636           overhead to all syscalls and produces a slightly larger kernel.
1637
1638           The seccomp filter system will not be available when this is
1639           selected, since there is no way yet to sensibly distinguish
1640           between calling conventions during filtering.
1641
1642           If you know you'll be using only pure EABI user space then you
1643           can say N here. If this option is not selected and you attempt
1644           to execute a legacy ABI binary then the result will be
1645           UNPREDICTABLE (in fact it can be predicted that it won't work
1646           at all). If in doubt say N.
1647
1648 config ARCH_HAS_HOLES_MEMORYMODEL
1649         bool
1650
1651 config ARCH_SPARSEMEM_ENABLE
1652         bool
1653
1654 config ARCH_SPARSEMEM_DEFAULT
1655         def_bool ARCH_SPARSEMEM_ENABLE
1656
1657 config ARCH_SELECT_MEMORY_MODEL
1658         def_bool ARCH_SPARSEMEM_ENABLE
1659
1660 config HAVE_ARCH_PFN_VALID
1661         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1662
1663 config HAVE_GENERIC_RCU_GUP
1664         def_bool y
1665         depends on ARM_LPAE
1666
1667 config HIGHMEM
1668         bool "High Memory Support"
1669         depends on MMU
1670         help
1671           The address space of ARM processors is only 4 Gigabytes large
1672           and it has to accommodate user address space, kernel address
1673           space as well as some memory mapped IO. That means that, if you
1674           have a large amount of physical memory and/or IO, not all of the
1675           memory can be "permanently mapped" by the kernel. The physical
1676           memory that is not permanently mapped is called "high memory".
1677
1678           Depending on the selected kernel/user memory split, minimum
1679           vmalloc space and actual amount of RAM, you may not need this
1680           option which should result in a slightly faster kernel.
1681
1682           If unsure, say n.
1683
1684 config HIGHPTE
1685         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1686         depends on HIGHMEM
1687         default y
1688         help
1689           The VM uses one page of physical memory for each page table.
1690           For systems with a lot of processes, this can use a lot of
1691           precious low memory, eventually leading to low memory being
1692           consumed by page tables.  Setting this option will allow
1693           user-space 2nd level page tables to reside in high memory.
1694
1695 config CPU_SW_DOMAIN_PAN
1696         bool "Enable use of CPU domains to implement privileged no-access"
1697         depends on MMU && !ARM_LPAE
1698         default y
1699         help
1700           Increase kernel security by ensuring that normal kernel accesses
1701           are unable to access userspace addresses.  This can help prevent
1702           use-after-free bugs becoming an exploitable privilege escalation
1703           by ensuring that magic values (such as LIST_POISON) will always
1704           fault when dereferenced.
1705
1706           CPUs with low-vector mappings use a best-efforts implementation.
1707           Their lower 1MB needs to remain accessible for the vectors, but
1708           the remainder of userspace will become appropriately inaccessible.
1709
1710 config HW_PERF_EVENTS
1711         def_bool y
1712         depends on ARM_PMU
1713
1714 config SYS_SUPPORTS_HUGETLBFS
1715        def_bool y
1716        depends on ARM_LPAE
1717
1718 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1719        def_bool y
1720        depends on ARM_LPAE
1721
1722 config ARCH_WANT_GENERAL_HUGETLB
1723         def_bool y
1724
1725 config ARM_MODULE_PLTS
1726         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1727         depends on MODULES
1728         help
1729           Allocate PLTs when loading modules so that jumps and calls whose
1730           targets are too far away for their relative offsets to be encoded
1731           in the instructions themselves can be bounced via veneers in the
1732           module's PLT. This allows modules to be allocated in the generic
1733           vmalloc area after the dedicated module memory area has been
1734           exhausted. The modules will use slightly more memory, but after
1735           rounding up to page size, the actual memory footprint is usually
1736           the same.
1737
1738           Say y if you are getting out of memory errors while loading modules
1739
1740 source "mm/Kconfig"
1741
1742 config FORCE_MAX_ZONEORDER
1743         int "Maximum zone order"
1744         default "12" if SOC_AM33XX
1745         default "9" if SA1111 || ARCH_EFM32
1746         default "11"
1747         help
1748           The kernel memory allocator divides physically contiguous memory
1749           blocks into "zones", where each zone is a power of two number of
1750           pages.  This option selects the largest power of two that the kernel
1751           keeps in the memory allocator.  If you need to allocate very large
1752           blocks of physically contiguous memory, then you may need to
1753           increase this value.
1754
1755           This config option is actually maximum order plus one. For example,
1756           a value of 11 means that the largest free memory block is 2^10 pages.
1757
1758 config ALIGNMENT_TRAP
1759         bool
1760         depends on CPU_CP15_MMU
1761         default y if !ARCH_EBSA110
1762         select HAVE_PROC_CPU if PROC_FS
1763         help
1764           ARM processors cannot fetch/store information which is not
1765           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1766           address divisible by 4. On 32-bit ARM processors, these non-aligned
1767           fetch/store instructions will be emulated in software if you say
1768           here, which has a severe performance impact. This is necessary for
1769           correct operation of some network protocols. With an IP-only
1770           configuration it is safe to say N, otherwise say Y.
1771
1772 config UACCESS_WITH_MEMCPY
1773         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1774         depends on MMU
1775         default y if CPU_FEROCEON
1776         help
1777           Implement faster copy_to_user and clear_user methods for CPU
1778           cores where a 8-word STM instruction give significantly higher
1779           memory write throughput than a sequence of individual 32bit stores.
1780
1781           A possible side effect is a slight increase in scheduling latency
1782           between threads sharing the same address space if they invoke
1783           such copy operations with large buffers.
1784
1785           However, if the CPU data cache is using a write-allocate mode,
1786           this option is unlikely to provide any performance gain.
1787
1788 config SECCOMP
1789         bool
1790         prompt "Enable seccomp to safely compute untrusted bytecode"
1791         ---help---
1792           This kernel feature is useful for number crunching applications
1793           that may need to compute untrusted bytecode during their
1794           execution. By using pipes or other transports made available to
1795           the process as file descriptors supporting the read/write
1796           syscalls, it's possible to isolate those applications in
1797           their own address space using seccomp. Once seccomp is
1798           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1799           and the task is only allowed to execute a few safe syscalls
1800           defined by each seccomp mode.
1801
1802 config SWIOTLB
1803         def_bool y
1804
1805 config IOMMU_HELPER
1806         def_bool SWIOTLB
1807
1808 config PARAVIRT
1809         bool "Enable paravirtualization code"
1810         help
1811           This changes the kernel so it can modify itself when it is run
1812           under a hypervisor, potentially improving performance significantly
1813           over full virtualization.
1814
1815 config PARAVIRT_TIME_ACCOUNTING
1816         bool "Paravirtual steal time accounting"
1817         select PARAVIRT
1818         default n
1819         help
1820           Select this option to enable fine granularity task steal time
1821           accounting. Time spent executing other tasks in parallel with
1822           the current vCPU is discounted from the vCPU power. To account for
1823           that, there can be a small performance impact.
1824
1825           If in doubt, say N here.
1826
1827 config XEN_DOM0
1828         def_bool y
1829         depends on XEN
1830
1831 config XEN
1832         bool "Xen guest support on ARM"
1833         depends on ARM && AEABI && OF
1834         depends on CPU_V7 && !CPU_V6
1835         depends on !GENERIC_ATOMIC64
1836         depends on MMU
1837         select ARCH_DMA_ADDR_T_64BIT
1838         select ARM_PSCI
1839         select SWIOTLB_XEN
1840         select PARAVIRT
1841         help
1842           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1843
1844 endmenu
1845
1846 menu "Boot options"
1847
1848 config USE_OF
1849         bool "Flattened Device Tree support"
1850         select IRQ_DOMAIN
1851         select OF
1852         help
1853           Include support for flattened device tree machine descriptions.
1854
1855 config ATAGS
1856         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1857         default y
1858         help
1859           This is the traditional way of passing data to the kernel at boot
1860           time. If you are solely relying on the flattened device tree (or
1861           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1862           to remove ATAGS support from your kernel binary.  If unsure,
1863           leave this to y.
1864
1865 config DEPRECATED_PARAM_STRUCT
1866         bool "Provide old way to pass kernel parameters"
1867         depends on ATAGS
1868         help
1869           This was deprecated in 2001 and announced to live on for 5 years.
1870           Some old boot loaders still use this way.
1871
1872 # Compressed boot loader in ROM.  Yes, we really want to ask about
1873 # TEXT and BSS so we preserve their values in the config files.
1874 config ZBOOT_ROM_TEXT
1875         hex "Compressed ROM boot loader base address"
1876         default "0"
1877         help
1878           The physical address at which the ROM-able zImage is to be
1879           placed in the target.  Platforms which normally make use of
1880           ROM-able zImage formats normally set this to a suitable
1881           value in their defconfig file.
1882
1883           If ZBOOT_ROM is not enabled, this has no effect.
1884
1885 config ZBOOT_ROM_BSS
1886         hex "Compressed ROM boot loader BSS address"
1887         default "0"
1888         help
1889           The base address of an area of read/write memory in the target
1890           for the ROM-able zImage which must be available while the
1891           decompressor is running. It must be large enough to hold the
1892           entire decompressed kernel plus an additional 128 KiB.
1893           Platforms which normally make use of ROM-able zImage formats
1894           normally set this to a suitable value in their defconfig file.
1895
1896           If ZBOOT_ROM is not enabled, this has no effect.
1897
1898 config ZBOOT_ROM
1899         bool "Compressed boot loader in ROM/flash"
1900         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1901         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1902         help
1903           Say Y here if you intend to execute your compressed kernel image
1904           (zImage) directly from ROM or flash.  If unsure, say N.
1905
1906 config ARM_APPENDED_DTB
1907         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1908         depends on OF
1909         help
1910           With this option, the boot code will look for a device tree binary
1911           (DTB) appended to zImage
1912           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1913
1914           This is meant as a backward compatibility convenience for those
1915           systems with a bootloader that can't be upgraded to accommodate
1916           the documented boot protocol using a device tree.
1917
1918           Beware that there is very little in terms of protection against
1919           this option being confused by leftover garbage in memory that might
1920           look like a DTB header after a reboot if no actual DTB is appended
1921           to zImage.  Do not leave this option active in a production kernel
1922           if you don't intend to always append a DTB.  Proper passing of the
1923           location into r2 of a bootloader provided DTB is always preferable
1924           to this option.
1925
1926 config ARM_ATAG_DTB_COMPAT
1927         bool "Supplement the appended DTB with traditional ATAG information"
1928         depends on ARM_APPENDED_DTB
1929         help
1930           Some old bootloaders can't be updated to a DTB capable one, yet
1931           they provide ATAGs with memory configuration, the ramdisk address,
1932           the kernel cmdline string, etc.  Such information is dynamically
1933           provided by the bootloader and can't always be stored in a static
1934           DTB.  To allow a device tree enabled kernel to be used with such
1935           bootloaders, this option allows zImage to extract the information
1936           from the ATAG list and store it at run time into the appended DTB.
1937
1938 choice
1939         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1940         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1941
1942 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1943         bool "Use bootloader kernel arguments if available"
1944         help
1945           Uses the command-line options passed by the boot loader instead of
1946           the device tree bootargs property. If the boot loader doesn't provide
1947           any, the device tree bootargs property will be used.
1948
1949 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1950         bool "Extend with bootloader kernel arguments"
1951         help
1952           The command-line arguments provided by the boot loader will be
1953           appended to the the device tree bootargs property.
1954
1955 endchoice
1956
1957 config CMDLINE
1958         string "Default kernel command string"
1959         default ""
1960         help
1961           On some architectures (EBSA110 and CATS), there is currently no way
1962           for the boot loader to pass arguments to the kernel. For these
1963           architectures, you should supply some command-line options at build
1964           time by entering them here. As a minimum, you should specify the
1965           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1966
1967 choice
1968         prompt "Kernel command line type" if CMDLINE != ""
1969         default CMDLINE_FROM_BOOTLOADER
1970         depends on ATAGS
1971
1972 config CMDLINE_FROM_BOOTLOADER
1973         bool "Use bootloader kernel arguments if available"
1974         help
1975           Uses the command-line options passed by the boot loader. If
1976           the boot loader doesn't provide any, the default kernel command
1977           string provided in CMDLINE will be used.
1978
1979 config CMDLINE_EXTEND
1980         bool "Extend bootloader kernel arguments"
1981         help
1982           The command-line arguments provided by the boot loader will be
1983           appended to the default kernel command string.
1984
1985 config CMDLINE_FORCE
1986         bool "Always use the default kernel command string"
1987         help
1988           Always use the default kernel command string, even if the boot
1989           loader passes other arguments to the kernel.
1990           This is useful if you cannot or don't want to change the
1991           command-line options your boot loader passes to the kernel.
1992 endchoice
1993
1994 config XIP_KERNEL
1995         bool "Kernel Execute-In-Place from ROM"
1996         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1997         help
1998           Execute-In-Place allows the kernel to run from non-volatile storage
1999           directly addressable by the CPU, such as NOR flash. This saves RAM
2000           space since the text section of the kernel is not loaded from flash
2001           to RAM.  Read-write sections, such as the data section and stack,
2002           are still copied to RAM.  The XIP kernel is not compressed since
2003           it has to run directly from flash, so it will take more space to
2004           store it.  The flash address used to link the kernel object files,
2005           and for storing it, is configuration dependent. Therefore, if you
2006           say Y here, you must know the proper physical address where to
2007           store the kernel image depending on your own flash memory usage.
2008
2009           Also note that the make target becomes "make xipImage" rather than
2010           "make zImage" or "make Image".  The final kernel binary to put in
2011           ROM memory will be arch/arm/boot/xipImage.
2012
2013           If unsure, say N.
2014
2015 config XIP_PHYS_ADDR
2016         hex "XIP Kernel Physical Location"
2017         depends on XIP_KERNEL
2018         default "0x00080000"
2019         help
2020           This is the physical address in your flash memory the kernel will
2021           be linked for and stored to.  This address is dependent on your
2022           own flash usage.
2023
2024 config KEXEC
2025         bool "Kexec system call (EXPERIMENTAL)"
2026         depends on (!SMP || PM_SLEEP_SMP)
2027         depends on !CPU_V7M
2028         select KEXEC_CORE
2029         help
2030           kexec is a system call that implements the ability to shutdown your
2031           current kernel, and to start another kernel.  It is like a reboot
2032           but it is independent of the system firmware.   And like a reboot
2033           you can start any kernel with it, not just Linux.
2034
2035           It is an ongoing process to be certain the hardware in a machine
2036           is properly shutdown, so do not be surprised if this code does not
2037           initially work for you.
2038
2039 config ATAGS_PROC
2040         bool "Export atags in procfs"
2041         depends on ATAGS && KEXEC
2042         default y
2043         help
2044           Should the atags used to boot the kernel be exported in an "atags"
2045           file in procfs. Useful with kexec.
2046
2047 config CRASH_DUMP
2048         bool "Build kdump crash kernel (EXPERIMENTAL)"
2049         help
2050           Generate crash dump after being started by kexec. This should
2051           be normally only set in special crash dump kernels which are
2052           loaded in the main kernel with kexec-tools into a specially
2053           reserved region and then later executed after a crash by
2054           kdump/kexec. The crash dump kernel must be compiled to a
2055           memory address not used by the main kernel
2056
2057           For more details see Documentation/kdump/kdump.txt
2058
2059 config AUTO_ZRELADDR
2060         bool "Auto calculation of the decompressed kernel image address"
2061         help
2062           ZRELADDR is the physical address where the decompressed kernel
2063           image will be placed. If AUTO_ZRELADDR is selected, the address
2064           will be determined at run-time by masking the current IP with
2065           0xf8000000. This assumes the zImage being placed in the first 128MB
2066           from start of memory.
2067
2068 config EFI_STUB
2069         bool
2070
2071 config EFI
2072         bool "UEFI runtime support"
2073         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2074         select UCS2_STRING
2075         select EFI_PARAMS_FROM_FDT
2076         select EFI_STUB
2077         select EFI_ARMSTUB
2078         select EFI_RUNTIME_WRAPPERS
2079         ---help---
2080           This option provides support for runtime services provided
2081           by UEFI firmware (such as non-volatile variables, realtime
2082           clock, and platform reset). A UEFI stub is also provided to
2083           allow the kernel to be booted as an EFI application. This
2084           is only useful for kernels that may run on systems that have
2085           UEFI firmware.
2086
2087 endmenu
2088
2089 menu "CPU Power Management"
2090
2091 source "drivers/cpufreq/Kconfig"
2092
2093 source "drivers/cpuidle/Kconfig"
2094
2095 endmenu
2096
2097 menu "Floating point emulation"
2098
2099 comment "At least one emulation must be selected"
2100
2101 config FPE_NWFPE
2102         bool "NWFPE math emulation"
2103         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2104         ---help---
2105           Say Y to include the NWFPE floating point emulator in the kernel.
2106           This is necessary to run most binaries. Linux does not currently
2107           support floating point hardware so you need to say Y here even if
2108           your machine has an FPA or floating point co-processor podule.
2109
2110           You may say N here if you are going to load the Acorn FPEmulator
2111           early in the bootup.
2112
2113 config FPE_NWFPE_XP
2114         bool "Support extended precision"
2115         depends on FPE_NWFPE
2116         help
2117           Say Y to include 80-bit support in the kernel floating-point
2118           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2119           Note that gcc does not generate 80-bit operations by default,
2120           so in most cases this option only enlarges the size of the
2121           floating point emulator without any good reason.
2122
2123           You almost surely want to say N here.
2124
2125 config FPE_FASTFPE
2126         bool "FastFPE math emulation (EXPERIMENTAL)"
2127         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2128         ---help---
2129           Say Y here to include the FAST floating point emulator in the kernel.
2130           This is an experimental much faster emulator which now also has full
2131           precision for the mantissa.  It does not support any exceptions.
2132           It is very simple, and approximately 3-6 times faster than NWFPE.
2133
2134           It should be sufficient for most programs.  It may be not suitable
2135           for scientific calculations, but you have to check this for yourself.
2136           If you do not feel you need a faster FP emulation you should better
2137           choose NWFPE.
2138
2139 config VFP
2140         bool "VFP-format floating point maths"
2141         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2142         help
2143           Say Y to include VFP support code in the kernel. This is needed
2144           if your hardware includes a VFP unit.
2145
2146           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2147           release notes and additional status information.
2148
2149           Say N if your target does not have VFP hardware.
2150
2151 config VFPv3
2152         bool
2153         depends on VFP
2154         default y if CPU_V7
2155
2156 config NEON
2157         bool "Advanced SIMD (NEON) Extension support"
2158         depends on VFPv3 && CPU_V7
2159         help
2160           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2161           Extension.
2162
2163 config KERNEL_MODE_NEON
2164         bool "Support for NEON in kernel mode"
2165         depends on NEON && AEABI
2166         help
2167           Say Y to include support for NEON in kernel mode.
2168
2169 endmenu
2170
2171 menu "Userspace binary formats"
2172
2173 source "fs/Kconfig.binfmt"
2174
2175 endmenu
2176
2177 menu "Power management options"
2178
2179 source "kernel/power/Kconfig"
2180
2181 config ARCH_SUSPEND_POSSIBLE
2182         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2183                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2184         def_bool y
2185
2186 config ARM_CPU_SUSPEND
2187         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2188         depends on ARCH_SUSPEND_POSSIBLE
2189
2190 config ARCH_HIBERNATION_POSSIBLE
2191         bool
2192         depends on MMU
2193         default y if ARCH_SUSPEND_POSSIBLE
2194
2195 endmenu
2196
2197 source "net/Kconfig"
2198
2199 source "drivers/Kconfig"
2200
2201 source "drivers/firmware/Kconfig"
2202
2203 source "fs/Kconfig"
2204
2205 source "arch/arm/Kconfig.debug"
2206
2207 source "security/Kconfig"
2208
2209 source "crypto/Kconfig"
2210 if CRYPTO
2211 source "arch/arm/crypto/Kconfig"
2212 endif
2213
2214 source "lib/Kconfig"
2215
2216 source "arch/arm/kvm/Kconfig"