arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_PCI_IOMAP
  25         select GENERIC_SCHED_CLOCK
  26         select GENERIC_SMP_IDLE_THREAD
  27         select GENERIC_STRNCPY_FROM_USER
  28         select GENERIC_STRNLEN_USER
  29         select HANDLE_DOMAIN_IRQ
  30         select HARDIRQS_SW_RESEND
  31         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  32         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  33         select HAVE_ARCH_KGDB
  34         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  35         select HAVE_ARCH_TRACEHOOK
  36         select HAVE_BPF_JIT
  37         select HAVE_CC_STACKPROTECTOR
  38         select HAVE_CONTEXT_TRACKING
  39         select HAVE_C_RECORDMCOUNT
  40         select HAVE_DEBUG_KMEMLEAK
  41         select HAVE_DMA_API_DEBUG
  42         select HAVE_DMA_ATTRS
  43         select HAVE_DMA_CONTIGUOUS if MMU
  44         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  45         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  46         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  47         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  48         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  49         select HAVE_GENERIC_DMA_COHERENT
  50         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  51         select HAVE_IDE if PCI || ISA || PCMCIA
  52         select HAVE_IRQ_TIME_ACCOUNTING
  53         select HAVE_KERNEL_GZIP
  54         select HAVE_KERNEL_LZ4
  55         select HAVE_KERNEL_LZMA
  56         select HAVE_KERNEL_LZO
  57         select HAVE_KERNEL_XZ
  58         select HAVE_KPROBES if !XIP_KERNEL
  59         select HAVE_KRETPROBES if (HAVE_KPROBES)
  60         select HAVE_MEMBLOCK
  61         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  62         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  63         select HAVE_PERF_EVENTS
  64         select HAVE_PERF_REGS
  65         select HAVE_PERF_USER_STACK_DUMP
  66         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  67         select HAVE_REGS_AND_STACK_ACCESS_API
  68         select HAVE_SYSCALL_TRACEPOINTS
  69         select HAVE_UID16
  70         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  71         select IRQ_FORCED_THREADING
  72         select MODULES_USE_ELF_REL
  73         select NO_BOOTMEM
  74         select OLD_SIGACTION
  75         select OLD_SIGSUSPEND3
  76         select PERF_USE_VMALLOC
  77         select RTC_LIB
  78         select SYS_SUPPORTS_APM_EMULATION
  79         # Above selects are sorted alphabetically; please add new ones
  80         # according to that.  Thanks.
  81         help
  82           The ARM series is a line of low-power-consumption RISC chip designs
  83           licensed by ARM Ltd and targeted at embedded applications and
  84           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  85           manufactured, but legacy ARM-based PC hardware remains popular in
  86           Europe.  There is an ARM Linux project with a web page at
  87           <http://www.arm.linux.org.uk/>.
  88
  89 config ARM_HAS_SG_CHAIN
  90         select ARCH_HAS_SG_CHAIN
  91         bool
  92
  93 config NEED_SG_DMA_LENGTH
  94         bool
  95
  96 config ARM_DMA_USE_IOMMU
  97         bool
  98         select ARM_HAS_SG_CHAIN
  99         select NEED_SG_DMA_LENGTH
 100
 101 if ARM_DMA_USE_IOMMU
 102
 103 config ARM_DMA_IOMMU_ALIGNMENT
 104         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 105         range 4 9
 106         default 8
 107         help
 108           DMA mapping framework by default aligns all buffers to the smallest
 109           PAGE_SIZE order which is greater than or equal to the requested buffer
 110           size. This works well for buffers up to a few hundreds kilobytes, but
 111           for larger buffers it just a waste of address space. Drivers which has
 112           relatively small addressing window (like 64Mib) might run out of
 113           virtual space with just a few allocations.
 114
 115           With this parameter you can specify the maximum PAGE_SIZE order for
 116           DMA IOMMU buffers. Larger buffers will be aligned only to this
 117           specified order. The order is expressed as a power of two multiplied
 118           by the PAGE_SIZE.
 119
 120 endif
 121
 122 config MIGHT_HAVE_PCI
 123         bool
 124
 125 config SYS_SUPPORTS_APM_EMULATION
 126         bool
 127
 128 config HAVE_TCM
 129         bool
 130         select GENERIC_ALLOCATOR
 131
 132 config HAVE_PROC_CPU
 133         bool
 134
 135 config NO_IOPORT_MAP
 136         bool
 137
 138 config EISA
 139         bool
 140         ---help---
 141           The Extended Industry Standard Architecture (EISA) bus was
 142           developed as an open alternative to the IBM MicroChannel bus.
 143
 144           The EISA bus provided some of the features of the IBM MicroChannel
 145           bus while maintaining backward compatibility with cards made for
 146           the older ISA bus.  The EISA bus saw limited use between 1988 and
 147           1995 when it was made obsolete by the PCI bus.
 148
 149           Say Y here if you are building a kernel for an EISA-based machine.
 150
 151           Otherwise, say N.
 152
 153 config SBUS
 154         bool
 155
 156 config STACKTRACE_SUPPORT
 157         bool
 158         default y
 159
 160 config HAVE_LATENCYTOP_SUPPORT
 161         bool
 162         depends on !SMP
 163         default y
 164
 165 config LOCKDEP_SUPPORT
 166         bool
 167         default y
 168
 169 config TRACE_IRQFLAGS_SUPPORT
 170         bool
 171         default y
 172
 173 config RWSEM_XCHGADD_ALGORITHM
 174         bool
 175         default y
 176
 177 config ARCH_HAS_ILOG2_U32
 178         bool
 179
 180 config ARCH_HAS_ILOG2_U64
 181         bool
 182
 183 config ARCH_HAS_BANDGAP
 184         bool
 185
 186 config GENERIC_HWEIGHT
 187         bool
 188         default y
 189
 190 config GENERIC_CALIBRATE_DELAY
 191         bool
 192         default y
 193
 194 config ARCH_MAY_HAVE_PC_FDC
 195         bool
 196
 197 config ZONE_DMA
 198         bool
 199
 200 config NEED_DMA_MAP_STATE
 201        def_bool y
 202
 203 config ARCH_SUPPORTS_UPROBES
 204         def_bool y
 205
 206 config ARCH_HAS_DMA_SET_COHERENT_MASK
 207         bool
 208
 209 config GENERIC_ISA_DMA
 210         bool
 211
 212 config FIQ
 213         bool
 214
 215 config NEED_RET_TO_USER
 216         bool
 217
 218 config ARCH_MTD_XIP
 219         bool
 220
 221 config VECTORS_BASE
 222         hex
 223         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 224         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 225         default 0x00000000
 226         help
 227           The base address of exception vectors.  This must be two pages
 228           in size.
 229
 230 config ARM_PATCH_PHYS_VIRT
 231         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 232         default y
 233         depends on !XIP_KERNEL && MMU
 234         depends on !ARCH_REALVIEW || !SPARSEMEM
 235         help
 236           Patch phys-to-virt and virt-to-phys translation functions at
 237           boot and module load time according to the position of the
 238           kernel in system memory.
 239
 240           This can only be used with non-XIP MMU kernels where the base
 241           of physical memory is at a 16MB boundary.
 242
 243           Only disable this option if you know that you do not require
 244           this feature (eg, building a kernel for a single machine) and
 245           you need to shrink the kernel to the minimal size.
 246
 247 config NEED_MACH_IO_H
 248         bool
 249         help
 250           Select this when mach/io.h is required to provide special
 251           definitions for this platform.  The need for mach/io.h should
 252           be avoided when possible.
 253
 254 config NEED_MACH_MEMORY_H
 255         bool
 256         help
 257           Select this when mach/memory.h is required to provide special
 258           definitions for this platform.  The need for mach/memory.h should
 259           be avoided when possible.
 260
 261 config PHYS_OFFSET
 262         hex "Physical address of main memory" if MMU
 263         depends on !ARM_PATCH_PHYS_VIRT
 264         default DRAM_BASE if !MMU
 265         default 0x00000000 if ARCH_EBSA110 || \
 266                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 267                         ARCH_FOOTBRIDGE || \
 268                         ARCH_INTEGRATOR || \
 269                         ARCH_IOP13XX || \
 270                         ARCH_KS8695 || \
 271                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 272         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 273         default 0x20000000 if ARCH_S5PV210
 274         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 275         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 276         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 277         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 278         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 279         help
 280           Please provide the physical address corresponding to the
 281           location of main memory in your system.
 282
 283 config GENERIC_BUG
 284         def_bool y
 285         depends on BUG
 286
 287 source "init/Kconfig"
 288
 289 source "kernel/Kconfig.freezer"
 290
 291 menu "System Type"
 292
 293 config MMU
 294         bool "MMU-based Paged Memory Management Support"
 295         default y
 296         help
 297           Select if you want MMU-based virtualised addressing space
 298           support by paged memory management. If unsure, say 'Y'.
 299
 300 #
 301 # The "ARM system type" choice list is ordered alphabetically by option
 302 # text.  Please add new entries in the option alphabetic order.
 303 #
 304 choice
 305         prompt "ARM system type"
 306         default ARCH_VERSATILE if !MMU
 307         default ARCH_MULTIPLATFORM if MMU
 308
 309 config ARCH_MULTIPLATFORM
 310         bool "Allow multiple platforms to be selected"
 311         depends on MMU
 312         select ARCH_WANT_OPTIONAL_GPIOLIB
 313         select ARM_HAS_SG_CHAIN
 314         select ARM_PATCH_PHYS_VIRT
 315         select AUTO_ZRELADDR
 316         select CLKSRC_OF
 317         select COMMON_CLK
 318         select GENERIC_CLOCKEVENTS
 319         select MIGHT_HAVE_PCI
 320         select MULTI_IRQ_HANDLER
 321         select SPARSE_IRQ
 322         select USE_OF
 323
 324 config ARCH_REALVIEW
 325         bool "ARM Ltd. RealView family"
 326         select ARCH_WANT_OPTIONAL_GPIOLIB
 327         select ARM_AMBA
 328         select ARM_TIMER_SP804
 329         select COMMON_CLK
 330         select COMMON_CLK_VERSATILE
 331         select GENERIC_CLOCKEVENTS
 332         select GPIO_PL061 if GPIOLIB
 333         select ICST
 334         select NEED_MACH_MEMORY_H
 335         select PLAT_VERSATILE
 336         select PLAT_VERSATILE_SCHED_CLOCK
 337         help
 338           This enables support for ARM Ltd RealView boards.
 339
 340 config ARCH_VERSATILE
 341         bool "ARM Ltd. Versatile family"
 342         select ARCH_WANT_OPTIONAL_GPIOLIB
 343         select ARM_AMBA
 344         select ARM_TIMER_SP804
 345         select ARM_VIC
 346         select CLKDEV_LOOKUP
 347         select GENERIC_CLOCKEVENTS
 348         select HAVE_MACH_CLKDEV
 349         select ICST
 350         select PLAT_VERSATILE
 351         select PLAT_VERSATILE_CLOCK
 352         select PLAT_VERSATILE_SCHED_CLOCK
 353         select VERSATILE_FPGA_IRQ
 354         help
 355           This enables support for ARM Ltd Versatile board.
 356
 357 config ARCH_AT91
 358         bool "Atmel AT91"
 359         select ARCH_REQUIRE_GPIOLIB
 360         select CLKDEV_LOOKUP
 361         select IRQ_DOMAIN
 362         select NEED_MACH_IO_H if PCCARD
 363         select PINCTRL
 364         select PINCTRL_AT91
 365         select USE_OF
 366         help
 367           This enables support for systems based on Atmel
 368           AT91RM9200, AT91SAM9 and SAMA5 processors.
 369
 370 config ARCH_CLPS711X
 371         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 372         select ARCH_REQUIRE_GPIOLIB
 373         select AUTO_ZRELADDR
 374         select CLKSRC_MMIO
 375         select COMMON_CLK
 376         select CPU_ARM720T
 377         select GENERIC_CLOCKEVENTS
 378         select MFD_SYSCON
 379         select SOC_BUS
 380         help
 381           Support for Cirrus Logic 711x/721x/731x based boards.
 382
 383 config ARCH_GEMINI
 384         bool "Cortina Systems Gemini"
 385         select ARCH_REQUIRE_GPIOLIB
 386         select CLKSRC_MMIO
 387         select CPU_FA526
 388         select GENERIC_CLOCKEVENTS
 389         help
 390           Support for the Cortina Systems Gemini family SoCs
 391
 392 config ARCH_EBSA110
 393         bool "EBSA-110"
 394         select ARCH_USES_GETTIMEOFFSET
 395         select CPU_SA110
 396         select ISA
 397         select NEED_MACH_IO_H
 398         select NEED_MACH_MEMORY_H
 399         select NO_IOPORT_MAP
 400         help
 401           This is an evaluation board for the StrongARM processor available
 402           from Digital. It has limited hardware on-board, including an
 403           Ethernet interface, two PCMCIA sockets, two serial ports and a
 404           parallel port.
 405
 406 config ARCH_EFM32
 407         bool "Energy Micro efm32"
 408         depends on !MMU
 409         select ARCH_REQUIRE_GPIOLIB
 410         select ARM_NVIC
 411         select AUTO_ZRELADDR
 412         select CLKSRC_OF
 413         select COMMON_CLK
 414         select CPU_V7M
 415         select GENERIC_CLOCKEVENTS
 416         select NO_DMA
 417         select NO_IOPORT_MAP
 418         select SPARSE_IRQ
 419         select USE_OF
 420         help
 421           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 422           processors.
 423
 424 config ARCH_EP93XX
 425         bool "EP93xx-based"
 426         select ARCH_HAS_HOLES_MEMORYMODEL
 427         select ARCH_REQUIRE_GPIOLIB
 428         select ARCH_USES_GETTIMEOFFSET
 429         select ARM_AMBA
 430         select ARM_VIC
 431         select CLKDEV_LOOKUP
 432         select CPU_ARM920T
 433         help
 434           This enables support for the Cirrus EP93xx series of CPUs.
 435
 436 config ARCH_FOOTBRIDGE
 437         bool "FootBridge"
 438         select CPU_SA110
 439         select FOOTBRIDGE
 440         select GENERIC_CLOCKEVENTS
 441         select HAVE_IDE
 442         select NEED_MACH_IO_H if !MMU
 443         select NEED_MACH_MEMORY_H
 444         help
 445           Support for systems based on the DC21285 companion chip
 446           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 447
 448 config ARCH_NETX
 449         bool "Hilscher NetX based"
 450         select ARM_VIC
 451         select CLKSRC_MMIO
 452         select CPU_ARM926T
 453         select GENERIC_CLOCKEVENTS
 454         help
 455           This enables support for systems based on the Hilscher NetX Soc
 456
 457 config ARCH_IOP13XX
 458         bool "IOP13xx-based"
 459         depends on MMU
 460         select CPU_XSC3
 461         select NEED_MACH_MEMORY_H
 462         select NEED_RET_TO_USER
 463         select PCI
 464         select PLAT_IOP
 465         select VMSPLIT_1G
 466         select SPARSE_IRQ
 467         help
 468           Support for Intel's IOP13XX (XScale) family of processors.
 469
 470 config ARCH_IOP32X
 471         bool "IOP32x-based"
 472         depends on MMU
 473         select ARCH_REQUIRE_GPIOLIB
 474         select CPU_XSCALE
 475         select GPIO_IOP
 476         select NEED_RET_TO_USER
 477         select PCI
 478         select PLAT_IOP
 479         help
 480           Support for Intel's 80219 and IOP32X (XScale) family of
 481           processors.
 482
 483 config ARCH_IOP33X
 484         bool "IOP33x-based"
 485         depends on MMU
 486         select ARCH_REQUIRE_GPIOLIB
 487         select CPU_XSCALE
 488         select GPIO_IOP
 489         select NEED_RET_TO_USER
 490         select PCI
 491         select PLAT_IOP
 492         help
 493           Support for Intel's IOP33X (XScale) family of processors.
 494
 495 config ARCH_IXP4XX
 496         bool "IXP4xx-based"
 497         depends on MMU
 498         select ARCH_HAS_DMA_SET_COHERENT_MASK
 499         select ARCH_REQUIRE_GPIOLIB
 500         select ARCH_SUPPORTS_BIG_ENDIAN
 501         select CLKSRC_MMIO
 502         select CPU_XSCALE
 503         select DMABOUNCE if PCI
 504         select GENERIC_CLOCKEVENTS
 505         select MIGHT_HAVE_PCI
 506         select NEED_MACH_IO_H
 507         select USB_EHCI_BIG_ENDIAN_DESC
 508         select USB_EHCI_BIG_ENDIAN_MMIO
 509         help
 510           Support for Intel's IXP4XX (XScale) family of processors.
 511
 512 config ARCH_DOVE
 513         bool "Marvell Dove"
 514         select ARCH_REQUIRE_GPIOLIB
 515         select CPU_PJ4
 516         select GENERIC_CLOCKEVENTS
 517         select MIGHT_HAVE_PCI
 518         select MVEBU_MBUS
 519         select PINCTRL
 520         select PINCTRL_DOVE
 521         select PLAT_ORION_LEGACY
 522         help
 523           Support for the Marvell Dove SoC 88AP510
 524
 525 config ARCH_MV78XX0
 526         bool "Marvell MV78xx0"
 527         select ARCH_REQUIRE_GPIOLIB
 528         select CPU_FEROCEON
 529         select GENERIC_CLOCKEVENTS
 530         select MVEBU_MBUS
 531         select PCI
 532         select PLAT_ORION_LEGACY
 533         help
 534           Support for the following Marvell MV78xx0 series SoCs:
 535           MV781x0, MV782x0.
 536
 537 config ARCH_ORION5X
 538         bool "Marvell Orion"
 539         depends on MMU
 540         select ARCH_REQUIRE_GPIOLIB
 541         select CPU_FEROCEON
 542         select GENERIC_CLOCKEVENTS
 543         select MVEBU_MBUS
 544         select PCI
 545         select PLAT_ORION_LEGACY
 546         help
 547           Support for the following Marvell Orion 5x series SoCs:
 548           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 549           Orion-2 (5281), Orion-1-90 (6183).
 550
 551 config ARCH_MMP
 552         bool "Marvell PXA168/910/MMP2"
 553         depends on MMU
 554         select ARCH_REQUIRE_GPIOLIB
 555         select CLKDEV_LOOKUP
 556         select GENERIC_ALLOCATOR
 557         select GENERIC_CLOCKEVENTS
 558         select GPIO_PXA
 559         select IRQ_DOMAIN
 560         select MULTI_IRQ_HANDLER
 561         select PINCTRL
 562         select PLAT_PXA
 563         select SPARSE_IRQ
 564         help
 565           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 566
 567 config ARCH_KS8695
 568         bool "Micrel/Kendin KS8695"
 569         select ARCH_REQUIRE_GPIOLIB
 570         select CLKSRC_MMIO
 571         select CPU_ARM922T
 572         select GENERIC_CLOCKEVENTS
 573         select NEED_MACH_MEMORY_H
 574         help
 575           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 576           System-on-Chip devices.
 577
 578 config ARCH_W90X900
 579         bool "Nuvoton W90X900 CPU"
 580         select ARCH_REQUIRE_GPIOLIB
 581         select CLKDEV_LOOKUP
 582         select CLKSRC_MMIO
 583         select CPU_ARM926T
 584         select GENERIC_CLOCKEVENTS
 585         help
 586           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 587           At present, the w90x900 has been renamed nuc900, regarding
 588           the ARM series product line, you can login the following
 589           link address to know more.
 590
 591           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 592                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 593
 594 config ARCH_LPC32XX
 595         bool "NXP LPC32XX"
 596         select ARCH_REQUIRE_GPIOLIB
 597         select ARM_AMBA
 598         select CLKDEV_LOOKUP
 599         select CLKSRC_MMIO
 600         select CPU_ARM926T
 601         select GENERIC_CLOCKEVENTS
 602         select HAVE_IDE
 603         select USE_OF
 604         help
 605           Support for the NXP LPC32XX family of processors
 606
 607 config ARCH_PXA
 608         bool "PXA2xx/PXA3xx-based"
 609         depends on MMU
 610         select ARCH_MTD_XIP
 611         select ARCH_REQUIRE_GPIOLIB
 612         select ARM_CPU_SUSPEND if PM
 613         select AUTO_ZRELADDR
 614         select CLKDEV_LOOKUP
 615         select CLKSRC_MMIO
 616         select CLKSRC_OF
 617         select GENERIC_CLOCKEVENTS
 618         select GPIO_PXA
 619         select HAVE_IDE
 620         select MULTI_IRQ_HANDLER
 621         select PLAT_PXA
 622         select SPARSE_IRQ
 623         help
 624           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 625
 626 config ARCH_MSM
 627         bool "Qualcomm MSM (non-multiplatform)"
 628         select ARCH_REQUIRE_GPIOLIB
 629         select COMMON_CLK
 630         select GENERIC_CLOCKEVENTS
 631         help
 632           Support for Qualcomm MSM/QSD based systems.  This runs on the
 633           apps processor of the MSM/QSD and depends on a shared memory
 634           interface to the modem processor which runs the baseband
 635           stack and controls some vital subsystems
 636           (clock and power control, etc).
 637
 638 config ARCH_SHMOBILE_LEGACY
 639         bool "Renesas ARM SoCs (non-multiplatform)"
 640         select ARCH_SHMOBILE
 641         select ARM_PATCH_PHYS_VIRT if MMU
 642         select CLKDEV_LOOKUP
 643         select CPU_V7
 644         select GENERIC_CLOCKEVENTS
 645         select HAVE_ARM_SCU if SMP
 646         select HAVE_ARM_TWD if SMP
 647         select HAVE_MACH_CLKDEV
 648         select HAVE_SMP
 649         select MIGHT_HAVE_CACHE_L2X0
 650         select MULTI_IRQ_HANDLER
 651         select NO_IOPORT_MAP
 652         select PINCTRL
 653         select PM_GENERIC_DOMAINS if PM
 654         select SH_CLK_CPG
 655         select SPARSE_IRQ
 656         help
 657           Support for Renesas ARM SoC platforms using a non-multiplatform
 658           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 659           and RZ families.
 660
 661 config ARCH_RPC
 662         bool "RiscPC"
 663         select ARCH_ACORN
 664         select ARCH_MAY_HAVE_PC_FDC
 665         select ARCH_SPARSEMEM_ENABLE
 666         select ARCH_USES_GETTIMEOFFSET
 667         select CPU_SA110
 668         select FIQ
 669         select HAVE_IDE
 670         select HAVE_PATA_PLATFORM
 671         select ISA_DMA_API
 672         select NEED_MACH_IO_H
 673         select NEED_MACH_MEMORY_H
 674         select NO_IOPORT_MAP
 675         select VIRT_TO_BUS
 676         help
 677           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 678           CD-ROM interface, serial and parallel port, and the floppy drive.
 679
 680 config ARCH_SA1100
 681         bool "SA1100-based"
 682         select ARCH_MTD_XIP
 683         select ARCH_REQUIRE_GPIOLIB
 684         select ARCH_SPARSEMEM_ENABLE
 685         select CLKDEV_LOOKUP
 686         select CLKSRC_MMIO
 687         select CPU_FREQ
 688         select CPU_SA1100
 689         select GENERIC_CLOCKEVENTS
 690         select HAVE_IDE
 691         select ISA
 692         select NEED_MACH_MEMORY_H
 693         select SPARSE_IRQ
 694         help
 695           Support for StrongARM 11x0 based boards.
 696
 697 config ARCH_S3C24XX
 698         bool "Samsung S3C24XX SoCs"
 699         select ARCH_REQUIRE_GPIOLIB
 700         select ATAGS
 701         select CLKDEV_LOOKUP
 702         select CLKSRC_SAMSUNG_PWM
 703         select GENERIC_CLOCKEVENTS
 704         select GPIO_SAMSUNG
 705         select HAVE_S3C2410_I2C if I2C
 706         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 707         select HAVE_S3C_RTC if RTC_CLASS
 708         select MULTI_IRQ_HANDLER
 709         select NEED_MACH_IO_H
 710         select SAMSUNG_ATAGS
 711         help
 712           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 713           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 714           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 715           Samsung SMDK2410 development board (and derivatives).
 716
 717 config ARCH_S3C64XX
 718         bool "Samsung S3C64XX"
 719         select ARCH_REQUIRE_GPIOLIB
 720         select ARM_AMBA
 721         select ARM_VIC
 722         select ATAGS
 723         select CLKDEV_LOOKUP
 724         select CLKSRC_SAMSUNG_PWM
 725         select COMMON_CLK_SAMSUNG
 726         select CPU_V6K
 727         select GENERIC_CLOCKEVENTS
 728         select GPIO_SAMSUNG
 729         select HAVE_S3C2410_I2C if I2C
 730         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 731         select HAVE_TCM
 732         select NO_IOPORT_MAP
 733         select PLAT_SAMSUNG
 734         select PM_GENERIC_DOMAINS if PM
 735         select S3C_DEV_NAND
 736         select S3C_GPIO_TRACK
 737         select SAMSUNG_ATAGS
 738         select SAMSUNG_WAKEMASK
 739         select SAMSUNG_WDT_RESET
 740         help
 741           Samsung S3C64XX series based systems
 742
 743 config ARCH_DAVINCI
 744         bool "TI DaVinci"
 745         select ARCH_HAS_HOLES_MEMORYMODEL
 746         select ARCH_REQUIRE_GPIOLIB
 747         select CLKDEV_LOOKUP
 748         select GENERIC_ALLOCATOR
 749         select GENERIC_CLOCKEVENTS
 750         select GENERIC_IRQ_CHIP
 751         select HAVE_IDE
 752         select TI_PRIV_EDMA
 753         select USE_OF
 754         select ZONE_DMA
 755         help
 756           Support for TI's DaVinci platform.
 757
 758 config ARCH_OMAP1
 759         bool "TI OMAP1"
 760         depends on MMU
 761         select ARCH_HAS_HOLES_MEMORYMODEL
 762         select ARCH_OMAP
 763         select ARCH_REQUIRE_GPIOLIB
 764         select CLKDEV_LOOKUP
 765         select CLKSRC_MMIO
 766         select GENERIC_CLOCKEVENTS
 767         select GENERIC_IRQ_CHIP
 768         select HAVE_IDE
 769         select IRQ_DOMAIN
 770         select NEED_MACH_IO_H if PCCARD
 771         select NEED_MACH_MEMORY_H
 772         help
 773           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 774
 775 endchoice
 776
 777 menu "Multiple platform selection"
 778         depends on ARCH_MULTIPLATFORM
 779
 780 comment "CPU Core family selection"
 781
 782 config ARCH_MULTI_V4
 783         bool "ARMv4 based platforms (FA526)"
 784         depends on !ARCH_MULTI_V6_V7
 785         select ARCH_MULTI_V4_V5
 786         select CPU_FA526
 787
 788 config ARCH_MULTI_V4T
 789         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 790         depends on !ARCH_MULTI_V6_V7
 791         select ARCH_MULTI_V4_V5
 792         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 793                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 794                 CPU_ARM925T || CPU_ARM940T)
 795
 796 config ARCH_MULTI_V5
 797         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 798         depends on !ARCH_MULTI_V6_V7
 799         select ARCH_MULTI_V4_V5
 800         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 801                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 802                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 803
 804 config ARCH_MULTI_V4_V5
 805         bool
 806
 807 config ARCH_MULTI_V6
 808         bool "ARMv6 based platforms (ARM11)"
 809         select ARCH_MULTI_V6_V7
 810         select CPU_V6K
 811
 812 config ARCH_MULTI_V7
 813         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 814         default y
 815         select ARCH_MULTI_V6_V7
 816         select CPU_V7
 817         select HAVE_SMP
 818
 819 config ARCH_MULTI_V6_V7
 820         bool
 821         select MIGHT_HAVE_CACHE_L2X0
 822
 823 config ARCH_MULTI_CPU_AUTO
 824         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 825         select ARCH_MULTI_V5
 826
 827 endmenu
 828
 829 config ARCH_VIRT
 830         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 831         select ARM_AMBA
 832         select ARM_GIC
 833         select ARM_PSCI
 834         select HAVE_ARM_ARCH_TIMER
 835
 836 #
 837 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 838 # Kconfigs may be included either alphabetically (according to the
 839 # plat- suffix) or along side the corresponding mach-* source.
 840 #
 841 source "arch/arm/mach-mvebu/Kconfig"
 842
 843 source "arch/arm/mach-asm9260/Kconfig"
 844
 845 source "arch/arm/mach-at91/Kconfig"
 846
 847 source "arch/arm/mach-axxia/Kconfig"
 848
 849 source "arch/arm/mach-bcm/Kconfig"
 850
 851 source "arch/arm/mach-berlin/Kconfig"
 852
 853 source "arch/arm/mach-clps711x/Kconfig"
 854
 855 source "arch/arm/mach-cns3xxx/Kconfig"
 856
 857 source "arch/arm/mach-davinci/Kconfig"
 858
 859 source "arch/arm/mach-dove/Kconfig"
 860
 861 source "arch/arm/mach-ep93xx/Kconfig"
 862
 863 source "arch/arm/mach-footbridge/Kconfig"
 864
 865 source "arch/arm/mach-gemini/Kconfig"
 866
 867 source "arch/arm/mach-highbank/Kconfig"
 868
 869 source "arch/arm/mach-hisi/Kconfig"
 870
 871 source "arch/arm/mach-integrator/Kconfig"
 872
 873 source "arch/arm/mach-iop32x/Kconfig"
 874
 875 source "arch/arm/mach-iop33x/Kconfig"
 876
 877 source "arch/arm/mach-iop13xx/Kconfig"
 878
 879 source "arch/arm/mach-ixp4xx/Kconfig"
 880
 881 source "arch/arm/mach-keystone/Kconfig"
 882
 883 source "arch/arm/mach-ks8695/Kconfig"
 884
 885 source "arch/arm/mach-meson/Kconfig"
 886
 887 source "arch/arm/mach-msm/Kconfig"
 888
 889 source "arch/arm/mach-moxart/Kconfig"
 890
 891 source "arch/arm/mach-mv78xx0/Kconfig"
 892
 893 source "arch/arm/mach-imx/Kconfig"
 894
 895 source "arch/arm/mach-mediatek/Kconfig"
 896
 897 source "arch/arm/mach-mxs/Kconfig"
 898
 899 source "arch/arm/mach-netx/Kconfig"
 900
 901 source "arch/arm/mach-nomadik/Kconfig"
 902
 903 source "arch/arm/mach-nspire/Kconfig"
 904
 905 source "arch/arm/plat-omap/Kconfig"
 906
 907 source "arch/arm/mach-omap1/Kconfig"
 908
 909 source "arch/arm/mach-omap2/Kconfig"
 910
 911 source "arch/arm/mach-orion5x/Kconfig"
 912
 913 source "arch/arm/mach-picoxcell/Kconfig"
 914
 915 source "arch/arm/mach-pxa/Kconfig"
 916 source "arch/arm/plat-pxa/Kconfig"
 917
 918 source "arch/arm/mach-mmp/Kconfig"
 919
 920 source "arch/arm/mach-qcom/Kconfig"
 921
 922 source "arch/arm/mach-realview/Kconfig"
 923
 924 source "arch/arm/mach-rockchip/Kconfig"
 925
 926 source "arch/arm/mach-sa1100/Kconfig"
 927
 928 source "arch/arm/mach-socfpga/Kconfig"
 929
 930 source "arch/arm/mach-spear/Kconfig"
 931
 932 source "arch/arm/mach-sti/Kconfig"
 933
 934 source "arch/arm/mach-s3c24xx/Kconfig"
 935
 936 source "arch/arm/mach-s3c64xx/Kconfig"
 937
 938 source "arch/arm/mach-s5pv210/Kconfig"
 939
 940 source "arch/arm/mach-exynos/Kconfig"
 941 source "arch/arm/plat-samsung/Kconfig"
 942
 943 source "arch/arm/mach-shmobile/Kconfig"
 944
 945 source "arch/arm/mach-sunxi/Kconfig"
 946
 947 source "arch/arm/mach-prima2/Kconfig"
 948
 949 source "arch/arm/mach-tegra/Kconfig"
 950
 951 source "arch/arm/mach-u300/Kconfig"
 952
 953 source "arch/arm/mach-ux500/Kconfig"
 954
 955 source "arch/arm/mach-versatile/Kconfig"
 956
 957 source "arch/arm/mach-vexpress/Kconfig"
 958 source "arch/arm/plat-versatile/Kconfig"
 959
 960 source "arch/arm/mach-vt8500/Kconfig"
 961
 962 source "arch/arm/mach-w90x900/Kconfig"
 963
 964 source "arch/arm/mach-zynq/Kconfig"
 965
 966 # Definitions to make life easier
 967 config ARCH_ACORN
 968         bool
 969
 970 config PLAT_IOP
 971         bool
 972         select GENERIC_CLOCKEVENTS
 973
 974 config PLAT_ORION
 975         bool
 976         select CLKSRC_MMIO
 977         select COMMON_CLK
 978         select GENERIC_IRQ_CHIP
 979         select IRQ_DOMAIN
 980
 981 config PLAT_ORION_LEGACY
 982         bool
 983         select PLAT_ORION
 984
 985 config PLAT_PXA
 986         bool
 987
 988 config PLAT_VERSATILE
 989         bool
 990
 991 config ARM_TIMER_SP804
 992         bool
 993         select CLKSRC_MMIO
 994         select CLKSRC_OF if OF
 995
 996 source "arch/arm/firmware/Kconfig"
 997
 998 source arch/arm/mm/Kconfig
 999
1000 config IWMMXT
1001         bool "Enable iWMMXt support"
1002         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1003         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1004         help
1005           Enable support for iWMMXt context switching at run time if
1006           running on a CPU that supports it.
1007
1008 config MULTI_IRQ_HANDLER
1009         bool
1010         help
1011           Allow each machine to specify it's own IRQ handler at run time.
1012
1013 if !MMU
1014 source "arch/arm/Kconfig-nommu"
1015 endif
1016
1017 config PJ4B_ERRATA_4742
1018         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1019         depends on CPU_PJ4B && MACH_ARMADA_370
1020         default y
1021         help
1022           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1023           Event (WFE) IDLE states, a specific timing sensitivity exists between
1024           the retiring WFI/WFE instructions and the newly issued subsequent
1025           instructions.  This sensitivity can result in a CPU hang scenario.
1026           Workaround:
1027           The software must insert either a Data Synchronization Barrier (DSB)
1028           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1029           instruction
1030
1031 config ARM_ERRATA_326103
1032         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1033         depends on CPU_V6
1034         help
1035           Executing a SWP instruction to read-only memory does not set bit 11
1036           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1037           treat the access as a read, preventing a COW from occurring and
1038           causing the faulting task to livelock.
1039
1040 config ARM_ERRATA_411920
1041         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1042         depends on CPU_V6 || CPU_V6K
1043         help
1044           Invalidation of the Instruction Cache operation can
1045           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1046           It does not affect the MPCore. This option enables the ARM Ltd.
1047           recommended workaround.
1048
1049 config ARM_ERRATA_430973
1050         bool "ARM errata: Stale prediction on replaced interworking branch"
1051         depends on CPU_V7
1052         help
1053           This option enables the workaround for the 430973 Cortex-A8
1054           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1055           interworking branch is replaced with another code sequence at the
1056           same virtual address, whether due to self-modifying code or virtual
1057           to physical address re-mapping, Cortex-A8 does not recover from the
1058           stale interworking branch prediction. This results in Cortex-A8
1059           executing the new code sequence in the incorrect ARM or Thumb state.
1060           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1061           and also flushes the branch target cache at every context switch.
1062           Note that setting specific bits in the ACTLR register may not be
1063           available in non-secure mode.
1064
1065 config ARM_ERRATA_458693
1066         bool "ARM errata: Processor deadlock when a false hazard is created"
1067         depends on CPU_V7
1068         depends on !ARCH_MULTIPLATFORM
1069         help
1070           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1071           erratum. For very specific sequences of memory operations, it is
1072           possible for a hazard condition intended for a cache line to instead
1073           be incorrectly associated with a different cache line. This false
1074           hazard might then cause a processor deadlock. The workaround enables
1075           the L1 caching of the NEON accesses and disables the PLD instruction
1076           in the ACTLR register. Note that setting specific bits in the ACTLR
1077           register may not be available in non-secure mode.
1078
1079 config ARM_ERRATA_460075
1080         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1081         depends on CPU_V7
1082         depends on !ARCH_MULTIPLATFORM
1083         help
1084           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1085           erratum. Any asynchronous access to the L2 cache may encounter a
1086           situation in which recent store transactions to the L2 cache are lost
1087           and overwritten with stale memory contents from external memory. The
1088           workaround disables the write-allocate mode for the L2 cache via the
1089           ACTLR register. Note that setting specific bits in the ACTLR register
1090           may not be available in non-secure mode.
1091
1092 config ARM_ERRATA_742230
1093         bool "ARM errata: DMB operation may be faulty"
1094         depends on CPU_V7 && SMP
1095         depends on !ARCH_MULTIPLATFORM
1096         help
1097           This option enables the workaround for the 742230 Cortex-A9
1098           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1099           between two write operations may not ensure the correct visibility
1100           ordering of the two writes. This workaround sets a specific bit in
1101           the diagnostic register of the Cortex-A9 which causes the DMB
1102           instruction to behave as a DSB, ensuring the correct behaviour of
1103           the two writes.
1104
1105 config ARM_ERRATA_742231
1106         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1107         depends on CPU_V7 && SMP
1108         depends on !ARCH_MULTIPLATFORM
1109         help
1110           This option enables the workaround for the 742231 Cortex-A9
1111           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1112           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1113           accessing some data located in the same cache line, may get corrupted
1114           data due to bad handling of the address hazard when the line gets
1115           replaced from one of the CPUs at the same time as another CPU is
1116           accessing it. This workaround sets specific bits in the diagnostic
1117           register of the Cortex-A9 which reduces the linefill issuing
1118           capabilities of the processor.
1119
1120 config ARM_ERRATA_643719
1121         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1122         depends on CPU_V7 && SMP
1123         help
1124           This option enables the workaround for the 643719 Cortex-A9 (prior to
1125           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1126           register returns zero when it should return one. The workaround
1127           corrects this value, ensuring cache maintenance operations which use
1128           it behave as intended and avoiding data corruption.
1129
1130 config ARM_ERRATA_720789
1131         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1132         depends on CPU_V7
1133         help
1134           This option enables the workaround for the 720789 Cortex-A9 (prior to
1135           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1136           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1137           As a consequence of this erratum, some TLB entries which should be
1138           invalidated are not, resulting in an incoherency in the system page
1139           tables. The workaround changes the TLB flushing routines to invalidate
1140           entries regardless of the ASID.
1141
1142 config ARM_ERRATA_743622
1143         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1144         depends on CPU_V7
1145         depends on !ARCH_MULTIPLATFORM
1146         help
1147           This option enables the workaround for the 743622 Cortex-A9
1148           (r2p*) erratum. Under very rare conditions, a faulty
1149           optimisation in the Cortex-A9 Store Buffer may lead to data
1150           corruption. This workaround sets a specific bit in the diagnostic
1151           register of the Cortex-A9 which disables the Store Buffer
1152           optimisation, preventing the defect from occurring. This has no
1153           visible impact on the overall performance or power consumption of the
1154           processor.
1155
1156 config ARM_ERRATA_751472
1157         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1158         depends on CPU_V7
1159         depends on !ARCH_MULTIPLATFORM
1160         help
1161           This option enables the workaround for the 751472 Cortex-A9 (prior
1162           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1163           completion of a following broadcasted operation if the second
1164           operation is received by a CPU before the ICIALLUIS has completed,
1165           potentially leading to corrupted entries in the cache or TLB.
1166
1167 config ARM_ERRATA_754322
1168         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1169         depends on CPU_V7
1170         help
1171           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1172           r3p*) erratum. A speculative memory access may cause a page table walk
1173           which starts prior to an ASID switch but completes afterwards. This
1174           can populate the micro-TLB with a stale entry which may be hit with
1175           the new ASID. This workaround places two dsb instructions in the mm
1176           switching code so that no page table walks can cross the ASID switch.
1177
1178 config ARM_ERRATA_754327
1179         bool "ARM errata: no automatic Store Buffer drain"
1180         depends on CPU_V7 && SMP
1181         help
1182           This option enables the workaround for the 754327 Cortex-A9 (prior to
1183           r2p0) erratum. The Store Buffer does not have any automatic draining
1184           mechanism and therefore a livelock may occur if an external agent
1185           continuously polls a memory location waiting to observe an update.
1186           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1187           written polling loops from denying visibility of updates to memory.
1188
1189 config ARM_ERRATA_364296
1190         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1191         depends on CPU_V6
1192         help
1193           This options enables the workaround for the 364296 ARM1136
1194           r0p2 erratum (possible cache data corruption with
1195           hit-under-miss enabled). It sets the undocumented bit 31 in
1196           the auxiliary control register and the FI bit in the control
1197           register, thus disabling hit-under-miss without putting the
1198           processor into full low interrupt latency mode. ARM11MPCore
1199           is not affected.
1200
1201 config ARM_ERRATA_764369
1202         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1203         depends on CPU_V7 && SMP
1204         help
1205           This option enables the workaround for erratum 764369
1206           affecting Cortex-A9 MPCore with two or more processors (all
1207           current revisions). Under certain timing circumstances, a data
1208           cache line maintenance operation by MVA targeting an Inner
1209           Shareable memory region may fail to proceed up to either the
1210           Point of Coherency or to the Point of Unification of the
1211           system. This workaround adds a DSB instruction before the
1212           relevant cache maintenance functions and sets a specific bit
1213           in the diagnostic control register of the SCU.
1214
1215 config ARM_ERRATA_775420
1216        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1217        depends on CPU_V7
1218        help
1219          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1220          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1221          operation aborts with MMU exception, it might cause the processor
1222          to deadlock. This workaround puts DSB before executing ISB if
1223          an abort may occur on cache maintenance.
1224
1225 config ARM_ERRATA_798181
1226         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1227         depends on CPU_V7 && SMP
1228         help
1229           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1230           adequately shooting down all use of the old entries. This
1231           option enables the Linux kernel workaround for this erratum
1232           which sends an IPI to the CPUs that are running the same ASID
1233           as the one being invalidated.
1234
1235 config ARM_ERRATA_773022
1236         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1237         depends on CPU_V7
1238         help
1239           This option enables the workaround for the 773022 Cortex-A15
1240           (up to r0p4) erratum. In certain rare sequences of code, the
1241           loop buffer may deliver incorrect instructions. This
1242           workaround disables the loop buffer to avoid the erratum.
1243
1244 endmenu
1245
1246 source "arch/arm/common/Kconfig"
1247
1248 menu "Bus support"
1249
1250 config ISA
1251         bool
1252         help
1253           Find out whether you have ISA slots on your motherboard.  ISA is the
1254           name of a bus system, i.e. the way the CPU talks to the other stuff
1255           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1256           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1257           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1258
1259 # Select ISA DMA controller support
1260 config ISA_DMA
1261         bool
1262         select ISA_DMA_API
1263
1264 # Select ISA DMA interface
1265 config ISA_DMA_API
1266         bool
1267
1268 config PCI
1269         bool "PCI support" if MIGHT_HAVE_PCI
1270         help
1271           Find out whether you have a PCI motherboard. PCI is the name of a
1272           bus system, i.e. the way the CPU talks to the other stuff inside
1273           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1274           VESA. If you have PCI, say Y, otherwise N.
1275
1276 config PCI_DOMAINS
1277         bool
1278         depends on PCI
1279
1280 config PCI_NANOENGINE
1281         bool "BSE nanoEngine PCI support"
1282         depends on SA1100_NANOENGINE
1283         help
1284           Enable PCI on the BSE nanoEngine board.
1285
1286 config PCI_SYSCALL
1287         def_bool PCI
1288
1289 config PCI_HOST_ITE8152
1290         bool
1291         depends on PCI && MACH_ARMCORE
1292         default y
1293         select DMABOUNCE
1294
1295 source "drivers/pci/Kconfig"
1296 source "drivers/pci/pcie/Kconfig"
1297
1298 source "drivers/pcmcia/Kconfig"
1299
1300 endmenu
1301
1302 menu "Kernel Features"
1303
1304 config HAVE_SMP
1305         bool
1306         help
1307           This option should be selected by machines which have an SMP-
1308           capable CPU.
1309
1310           The only effect of this option is to make the SMP-related
1311           options available to the user for configuration.
1312
1313 config SMP
1314         bool "Symmetric Multi-Processing"
1315         depends on CPU_V6K || CPU_V7
1316         depends on GENERIC_CLOCKEVENTS
1317         depends on HAVE_SMP
1318         depends on MMU || ARM_MPU
1319         help
1320           This enables support for systems with more than one CPU. If you have
1321           a system with only one CPU, say N. If you have a system with more
1322           than one CPU, say Y.
1323
1324           If you say N here, the kernel will run on uni- and multiprocessor
1325           machines, but will use only one CPU of a multiprocessor machine. If
1326           you say Y here, the kernel will run on many, but not all,
1327           uniprocessor machines. On a uniprocessor machine, the kernel
1328           will run faster if you say N here.
1329
1330           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1331           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1332           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1333
1334           If you don't know what to do here, say N.
1335
1336 config SMP_ON_UP
1337         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1338         depends on SMP && !XIP_KERNEL && MMU
1339         default y
1340         help
1341           SMP kernels contain instructions which fail on non-SMP processors.
1342           Enabling this option allows the kernel to modify itself to make
1343           these instructions safe.  Disabling it allows about 1K of space
1344           savings.
1345
1346           If you don't know what to do here, say Y.
1347
1348 config ARM_CPU_TOPOLOGY
1349         bool "Support cpu topology definition"
1350         depends on SMP && CPU_V7
1351         default y
1352         help
1353           Support ARM cpu topology definition. The MPIDR register defines
1354           affinity between processors which is then used to describe the cpu
1355           topology of an ARM System.
1356
1357 config SCHED_MC
1358         bool "Multi-core scheduler support"
1359         depends on ARM_CPU_TOPOLOGY
1360         help
1361           Multi-core scheduler support improves the CPU scheduler's decision
1362           making when dealing with multi-core CPU chips at a cost of slightly
1363           increased overhead in some places. If unsure say N here.
1364
1365 config SCHED_SMT
1366         bool "SMT scheduler support"
1367         depends on ARM_CPU_TOPOLOGY
1368         help
1369           Improves the CPU scheduler's decision making when dealing with
1370           MultiThreading at a cost of slightly increased overhead in some
1371           places. If unsure say N here.
1372
1373 config HAVE_ARM_SCU
1374         bool
1375         help
1376           This option enables support for the ARM system coherency unit
1377
1378 config HAVE_ARM_ARCH_TIMER
1379         bool "Architected timer support"
1380         depends on CPU_V7
1381         select ARM_ARCH_TIMER
1382         select GENERIC_CLOCKEVENTS
1383         help
1384           This option enables support for the ARM architected timer
1385
1386 config HAVE_ARM_TWD
1387         bool
1388         depends on SMP
1389         select CLKSRC_OF if OF
1390         help
1391           This options enables support for the ARM timer and watchdog unit
1392
1393 config MCPM
1394         bool "Multi-Cluster Power Management"
1395         depends on CPU_V7 && SMP
1396         help
1397           This option provides the common power management infrastructure
1398           for (multi-)cluster based systems, such as big.LITTLE based
1399           systems.
1400
1401 config MCPM_QUAD_CLUSTER
1402         bool
1403         depends on MCPM
1404         help
1405           To avoid wasting resources unnecessarily, MCPM only supports up
1406           to 2 clusters by default.
1407           Platforms with 3 or 4 clusters that use MCPM must select this
1408           option to allow the additional clusters to be managed.
1409
1410 config BIG_LITTLE
1411         bool "big.LITTLE support (Experimental)"
1412         depends on CPU_V7 && SMP
1413         select MCPM
1414         help
1415           This option enables support selections for the big.LITTLE
1416           system architecture.
1417
1418 config BL_SWITCHER
1419         bool "big.LITTLE switcher support"
1420         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1421         select ARM_CPU_SUSPEND
1422         select CPU_PM
1423         help
1424           The big.LITTLE "switcher" provides the core functionality to
1425           transparently handle transition between a cluster of A15's
1426           and a cluster of A7's in a big.LITTLE system.
1427
1428 config BL_SWITCHER_DUMMY_IF
1429         tristate "Simple big.LITTLE switcher user interface"
1430         depends on BL_SWITCHER && DEBUG_KERNEL
1431         help
1432           This is a simple and dummy char dev interface to control
1433           the big.LITTLE switcher core code.  It is meant for
1434           debugging purposes only.
1435
1436 choice
1437         prompt "Memory split"
1438         depends on MMU
1439         default VMSPLIT_3G
1440         help
1441           Select the desired split between kernel and user memory.
1442
1443           If you are not absolutely sure what you are doing, leave this
1444           option alone!
1445
1446         config VMSPLIT_3G
1447                 bool "3G/1G user/kernel split"
1448         config VMSPLIT_2G
1449                 bool "2G/2G user/kernel split"
1450         config VMSPLIT_1G
1451                 bool "1G/3G user/kernel split"
1452 endchoice
1453
1454 config PAGE_OFFSET
1455         hex
1456         default PHYS_OFFSET if !MMU
1457         default 0x40000000 if VMSPLIT_1G
1458         default 0x80000000 if VMSPLIT_2G
1459         default 0xC0000000
1460
1461 config NR_CPUS
1462         int "Maximum number of CPUs (2-32)"
1463         range 2 32
1464         depends on SMP
1465         default "4"
1466
1467 config HOTPLUG_CPU
1468         bool "Support for hot-pluggable CPUs"
1469         depends on SMP
1470         help
1471           Say Y here to experiment with turning CPUs off and on.  CPUs
1472           can be controlled through /sys/devices/system/cpu.
1473
1474 config ARM_PSCI
1475         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1476         depends on CPU_V7
1477         help
1478           Say Y here if you want Linux to communicate with system firmware
1479           implementing the PSCI specification for CPU-centric power
1480           management operations described in ARM document number ARM DEN
1481           0022A ("Power State Coordination Interface System Software on
1482           ARM processors").
1483
1484 # The GPIO number here must be sorted by descending number. In case of
1485 # a multiplatform kernel, we just want the highest value required by the
1486 # selected platforms.
1487 config ARCH_NR_GPIO
1488         int
1489         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1490         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1491                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1492         default 416 if ARCH_SUNXI
1493         default 392 if ARCH_U8500
1494         default 352 if ARCH_VT8500
1495         default 288 if ARCH_ROCKCHIP
1496         default 264 if MACH_H4700
1497         default 0
1498         help
1499           Maximum number of GPIOs in the system.
1500
1501           If unsure, leave the default value.
1502
1503 source kernel/Kconfig.preempt
1504
1505 config HZ_FIXED
1506         int
1507         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1508                 ARCH_S5PV210 || ARCH_EXYNOS4
1509         default AT91_TIMER_HZ if ARCH_AT91
1510         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1511         default 0
1512
1513 choice
1514         depends on HZ_FIXED = 0
1515         prompt "Timer frequency"
1516
1517 config HZ_100
1518         bool "100 Hz"
1519
1520 config HZ_200
1521         bool "200 Hz"
1522
1523 config HZ_250
1524         bool "250 Hz"
1525
1526 config HZ_300
1527         bool "300 Hz"
1528
1529 config HZ_500
1530         bool "500 Hz"
1531
1532 config HZ_1000
1533         bool "1000 Hz"
1534
1535 endchoice
1536
1537 config HZ
1538         int
1539         default HZ_FIXED if HZ_FIXED != 0
1540         default 100 if HZ_100
1541         default 200 if HZ_200
1542         default 250 if HZ_250
1543         default 300 if HZ_300
1544         default 500 if HZ_500
1545         default 1000
1546
1547 config SCHED_HRTICK
1548         def_bool HIGH_RES_TIMERS
1549
1550 config THUMB2_KERNEL
1551         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1552         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1553         default y if CPU_THUMBONLY
1554         select AEABI
1555         select ARM_ASM_UNIFIED
1556         select ARM_UNWIND
1557         help
1558           By enabling this option, the kernel will be compiled in
1559           Thumb-2 mode. A compiler/assembler that understand the unified
1560           ARM-Thumb syntax is needed.
1561
1562           If unsure, say N.
1563
1564 config THUMB2_AVOID_R_ARM_THM_JUMP11
1565         bool "Work around buggy Thumb-2 short branch relocations in gas"
1566         depends on THUMB2_KERNEL && MODULES
1567         default y
1568         help
1569           Various binutils versions can resolve Thumb-2 branches to
1570           locally-defined, preemptible global symbols as short-range "b.n"
1571           branch instructions.
1572
1573           This is a problem, because there's no guarantee the final
1574           destination of the symbol, or any candidate locations for a
1575           trampoline, are within range of the branch.  For this reason, the
1576           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1577           relocation in modules at all, and it makes little sense to add
1578           support.
1579
1580           The symptom is that the kernel fails with an "unsupported
1581           relocation" error when loading some modules.
1582
1583           Until fixed tools are available, passing
1584           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1585           code which hits this problem, at the cost of a bit of extra runtime
1586           stack usage in some cases.
1587
1588           The problem is described in more detail at:
1589               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1590
1591           Only Thumb-2 kernels are affected.
1592
1593           Unless you are sure your tools don't have this problem, say Y.
1594
1595 config ARM_ASM_UNIFIED
1596         bool
1597
1598 config AEABI
1599         bool "Use the ARM EABI to compile the kernel"
1600         help
1601           This option allows for the kernel to be compiled using the latest
1602           ARM ABI (aka EABI).  This is only useful if you are using a user
1603           space environment that is also compiled with EABI.
1604
1605           Since there are major incompatibilities between the legacy ABI and
1606           EABI, especially with regard to structure member alignment, this
1607           option also changes the kernel syscall calling convention to
1608           disambiguate both ABIs and allow for backward compatibility support
1609           (selected with CONFIG_OABI_COMPAT).
1610
1611           To use this you need GCC version 4.0.0 or later.
1612
1613 config OABI_COMPAT
1614         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1615         depends on AEABI && !THUMB2_KERNEL
1616         help
1617           This option preserves the old syscall interface along with the
1618           new (ARM EABI) one. It also provides a compatibility layer to
1619           intercept syscalls that have structure arguments which layout
1620           in memory differs between the legacy ABI and the new ARM EABI
1621           (only for non "thumb" binaries). This option adds a tiny
1622           overhead to all syscalls and produces a slightly larger kernel.
1623
1624           The seccomp filter system will not be available when this is
1625           selected, since there is no way yet to sensibly distinguish
1626           between calling conventions during filtering.
1627
1628           If you know you'll be using only pure EABI user space then you
1629           can say N here. If this option is not selected and you attempt
1630           to execute a legacy ABI binary then the result will be
1631           UNPREDICTABLE (in fact it can be predicted that it won't work
1632           at all). If in doubt say N.
1633
1634 config ARCH_HAS_HOLES_MEMORYMODEL
1635         bool
1636
1637 config ARCH_SPARSEMEM_ENABLE
1638         bool
1639
1640 config ARCH_SPARSEMEM_DEFAULT
1641         def_bool ARCH_SPARSEMEM_ENABLE
1642
1643 config ARCH_SELECT_MEMORY_MODEL
1644         def_bool ARCH_SPARSEMEM_ENABLE
1645
1646 config HAVE_ARCH_PFN_VALID
1647         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1648
1649 config HAVE_GENERIC_RCU_GUP
1650         def_bool y
1651         depends on ARM_LPAE
1652
1653 config HIGHMEM
1654         bool "High Memory Support"
1655         depends on MMU
1656         help
1657           The address space of ARM processors is only 4 Gigabytes large
1658           and it has to accommodate user address space, kernel address
1659           space as well as some memory mapped IO. That means that, if you
1660           have a large amount of physical memory and/or IO, not all of the
1661           memory can be "permanently mapped" by the kernel. The physical
1662           memory that is not permanently mapped is called "high memory".
1663
1664           Depending on the selected kernel/user memory split, minimum
1665           vmalloc space and actual amount of RAM, you may not need this
1666           option which should result in a slightly faster kernel.
1667
1668           If unsure, say n.
1669
1670 config HIGHPTE
1671         bool "Allocate 2nd-level pagetables from highmem"
1672         depends on HIGHMEM
1673
1674 config HW_PERF_EVENTS
1675         bool "Enable hardware performance counter support for perf events"
1676         depends on PERF_EVENTS
1677         default y
1678         help
1679           Enable hardware performance counter support for perf events. If
1680           disabled, perf events will use software events only.
1681
1682 config SYS_SUPPORTS_HUGETLBFS
1683        def_bool y
1684        depends on ARM_LPAE
1685
1686 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1687        def_bool y
1688        depends on ARM_LPAE
1689
1690 config ARCH_WANT_GENERAL_HUGETLB
1691         def_bool y
1692
1693 source "mm/Kconfig"
1694
1695 config FORCE_MAX_ZONEORDER
1696         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1697         range 11 64 if ARCH_SHMOBILE_LEGACY
1698         default "12" if SOC_AM33XX
1699         default "9" if SA1111 || ARCH_EFM32
1700         default "11"
1701         help
1702           The kernel memory allocator divides physically contiguous memory
1703           blocks into "zones", where each zone is a power of two number of
1704           pages.  This option selects the largest power of two that the kernel
1705           keeps in the memory allocator.  If you need to allocate very large
1706           blocks of physically contiguous memory, then you may need to
1707           increase this value.
1708
1709           This config option is actually maximum order plus one. For example,
1710           a value of 11 means that the largest free memory block is 2^10 pages.
1711
1712 config ALIGNMENT_TRAP
1713         bool
1714         depends on CPU_CP15_MMU
1715         default y if !ARCH_EBSA110
1716         select HAVE_PROC_CPU if PROC_FS
1717         help
1718           ARM processors cannot fetch/store information which is not
1719           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1720           address divisible by 4. On 32-bit ARM processors, these non-aligned
1721           fetch/store instructions will be emulated in software if you say
1722           here, which has a severe performance impact. This is necessary for
1723           correct operation of some network protocols. With an IP-only
1724           configuration it is safe to say N, otherwise say Y.
1725
1726 config UACCESS_WITH_MEMCPY
1727         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1728         depends on MMU
1729         default y if CPU_FEROCEON
1730         help
1731           Implement faster copy_to_user and clear_user methods for CPU
1732           cores where a 8-word STM instruction give significantly higher
1733           memory write throughput than a sequence of individual 32bit stores.
1734
1735           A possible side effect is a slight increase in scheduling latency
1736           between threads sharing the same address space if they invoke
1737           such copy operations with large buffers.
1738
1739           However, if the CPU data cache is using a write-allocate mode,
1740           this option is unlikely to provide any performance gain.
1741
1742 config SECCOMP
1743         bool
1744         prompt "Enable seccomp to safely compute untrusted bytecode"
1745         ---help---
1746           This kernel feature is useful for number crunching applications
1747           that may need to compute untrusted bytecode during their
1748           execution. By using pipes or other transports made available to
1749           the process as file descriptors supporting the read/write
1750           syscalls, it's possible to isolate those applications in
1751           their own address space using seccomp. Once seccomp is
1752           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1753           and the task is only allowed to execute a few safe syscalls
1754           defined by each seccomp mode.
1755
1756 config SWIOTLB
1757         def_bool y
1758
1759 config IOMMU_HELPER
1760         def_bool SWIOTLB
1761
1762 config XEN_DOM0
1763         def_bool y
1764         depends on XEN
1765
1766 config XEN
1767         bool "Xen guest support on ARM"
1768         depends on ARM && AEABI && OF
1769         depends on CPU_V7 && !CPU_V6
1770         depends on !GENERIC_ATOMIC64
1771         depends on MMU
1772         select ARCH_DMA_ADDR_T_64BIT
1773         select ARM_PSCI
1774         select SWIOTLB_XEN
1775         help
1776           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1777
1778 endmenu
1779
1780 menu "Boot options"
1781
1782 config USE_OF
1783         bool "Flattened Device Tree support"
1784         select IRQ_DOMAIN
1785         select OF
1786         select OF_EARLY_FLATTREE
1787         select OF_RESERVED_MEM
1788         help
1789           Include support for flattened device tree machine descriptions.
1790
1791 config ATAGS
1792         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1793         default y
1794         help
1795           This is the traditional way of passing data to the kernel at boot
1796           time. If you are solely relying on the flattened device tree (or
1797           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1798           to remove ATAGS support from your kernel binary.  If unsure,
1799           leave this to y.
1800
1801 config DEPRECATED_PARAM_STRUCT
1802         bool "Provide old way to pass kernel parameters"
1803         depends on ATAGS
1804         help
1805           This was deprecated in 2001 and announced to live on for 5 years.
1806           Some old boot loaders still use this way.
1807
1808 # Compressed boot loader in ROM.  Yes, we really want to ask about
1809 # TEXT and BSS so we preserve their values in the config files.
1810 config ZBOOT_ROM_TEXT
1811         hex "Compressed ROM boot loader base address"
1812         default "0"
1813         help
1814           The physical address at which the ROM-able zImage is to be
1815           placed in the target.  Platforms which normally make use of
1816           ROM-able zImage formats normally set this to a suitable
1817           value in their defconfig file.
1818
1819           If ZBOOT_ROM is not enabled, this has no effect.
1820
1821 config ZBOOT_ROM_BSS
1822         hex "Compressed ROM boot loader BSS address"
1823         default "0"
1824         help
1825           The base address of an area of read/write memory in the target
1826           for the ROM-able zImage which must be available while the
1827           decompressor is running. It must be large enough to hold the
1828           entire decompressed kernel plus an additional 128 KiB.
1829           Platforms which normally make use of ROM-able zImage formats
1830           normally set this to a suitable value in their defconfig file.
1831
1832           If ZBOOT_ROM is not enabled, this has no effect.
1833
1834 config ZBOOT_ROM
1835         bool "Compressed boot loader in ROM/flash"
1836         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1837         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1838         help
1839           Say Y here if you intend to execute your compressed kernel image
1840           (zImage) directly from ROM or flash.  If unsure, say N.
1841
1842 choice
1843         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1844         depends on ZBOOT_ROM && ARCH_SH7372
1845         default ZBOOT_ROM_NONE
1846         help
1847           Include experimental SD/MMC loading code in the ROM-able zImage.
1848           With this enabled it is possible to write the ROM-able zImage
1849           kernel image to an MMC or SD card and boot the kernel straight
1850           from the reset vector. At reset the processor Mask ROM will load
1851           the first part of the ROM-able zImage which in turn loads the
1852           rest the kernel image to RAM.
1853
1854 config ZBOOT_ROM_NONE
1855         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1856         help
1857           Do not load image from SD or MMC
1858
1859 config ZBOOT_ROM_MMCIF
1860         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1861         help
1862           Load image from MMCIF hardware block.
1863
1864 config ZBOOT_ROM_SH_MOBILE_SDHI
1865         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1866         help
1867           Load image from SDHI hardware block
1868
1869 endchoice
1870
1871 config ARM_APPENDED_DTB
1872         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1873         depends on OF
1874         help
1875           With this option, the boot code will look for a device tree binary
1876           (DTB) appended to zImage
1877           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1878
1879           This is meant as a backward compatibility convenience for those
1880           systems with a bootloader that can't be upgraded to accommodate
1881           the documented boot protocol using a device tree.
1882
1883           Beware that there is very little in terms of protection against
1884           this option being confused by leftover garbage in memory that might
1885           look like a DTB header after a reboot if no actual DTB is appended
1886           to zImage.  Do not leave this option active in a production kernel
1887           if you don't intend to always append a DTB.  Proper passing of the
1888           location into r2 of a bootloader provided DTB is always preferable
1889           to this option.
1890
1891 config ARM_ATAG_DTB_COMPAT
1892         bool "Supplement the appended DTB with traditional ATAG information"
1893         depends on ARM_APPENDED_DTB
1894         help
1895           Some old bootloaders can't be updated to a DTB capable one, yet
1896           they provide ATAGs with memory configuration, the ramdisk address,
1897           the kernel cmdline string, etc.  Such information is dynamically
1898           provided by the bootloader and can't always be stored in a static
1899           DTB.  To allow a device tree enabled kernel to be used with such
1900           bootloaders, this option allows zImage to extract the information
1901           from the ATAG list and store it at run time into the appended DTB.
1902
1903 choice
1904         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1905         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1906
1907 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1908         bool "Use bootloader kernel arguments if available"
1909         help
1910           Uses the command-line options passed by the boot loader instead of
1911           the device tree bootargs property. If the boot loader doesn't provide
1912           any, the device tree bootargs property will be used.
1913
1914 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1915         bool "Extend with bootloader kernel arguments"
1916         help
1917           The command-line arguments provided by the boot loader will be
1918           appended to the the device tree bootargs property.
1919
1920 endchoice
1921
1922 config CMDLINE
1923         string "Default kernel command string"
1924         default ""
1925         help
1926           On some architectures (EBSA110 and CATS), there is currently no way
1927           for the boot loader to pass arguments to the kernel. For these
1928           architectures, you should supply some command-line options at build
1929           time by entering them here. As a minimum, you should specify the
1930           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1931
1932 choice
1933         prompt "Kernel command line type" if CMDLINE != ""
1934         default CMDLINE_FROM_BOOTLOADER
1935         depends on ATAGS
1936
1937 config CMDLINE_FROM_BOOTLOADER
1938         bool "Use bootloader kernel arguments if available"
1939         help
1940           Uses the command-line options passed by the boot loader. If
1941           the boot loader doesn't provide any, the default kernel command
1942           string provided in CMDLINE will be used.
1943
1944 config CMDLINE_EXTEND
1945         bool "Extend bootloader kernel arguments"
1946         help
1947           The command-line arguments provided by the boot loader will be
1948           appended to the default kernel command string.
1949
1950 config CMDLINE_FORCE
1951         bool "Always use the default kernel command string"
1952         help
1953           Always use the default kernel command string, even if the boot
1954           loader passes other arguments to the kernel.
1955           This is useful if you cannot or don't want to change the
1956           command-line options your boot loader passes to the kernel.
1957 endchoice
1958
1959 config XIP_KERNEL
1960         bool "Kernel Execute-In-Place from ROM"
1961         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1962         help
1963           Execute-In-Place allows the kernel to run from non-volatile storage
1964           directly addressable by the CPU, such as NOR flash. This saves RAM
1965           space since the text section of the kernel is not loaded from flash
1966           to RAM.  Read-write sections, such as the data section and stack,
1967           are still copied to RAM.  The XIP kernel is not compressed since
1968           it has to run directly from flash, so it will take more space to
1969           store it.  The flash address used to link the kernel object files,
1970           and for storing it, is configuration dependent. Therefore, if you
1971           say Y here, you must know the proper physical address where to
1972           store the kernel image depending on your own flash memory usage.
1973
1974           Also note that the make target becomes "make xipImage" rather than
1975           "make zImage" or "make Image".  The final kernel binary to put in
1976           ROM memory will be arch/arm/boot/xipImage.
1977
1978           If unsure, say N.
1979
1980 config XIP_PHYS_ADDR
1981         hex "XIP Kernel Physical Location"
1982         depends on XIP_KERNEL
1983         default "0x00080000"
1984         help
1985           This is the physical address in your flash memory the kernel will
1986           be linked for and stored to.  This address is dependent on your
1987           own flash usage.
1988
1989 config KEXEC
1990         bool "Kexec system call (EXPERIMENTAL)"
1991         depends on (!SMP || PM_SLEEP_SMP)
1992         help
1993           kexec is a system call that implements the ability to shutdown your
1994           current kernel, and to start another kernel.  It is like a reboot
1995           but it is independent of the system firmware.   And like a reboot
1996           you can start any kernel with it, not just Linux.
1997
1998           It is an ongoing process to be certain the hardware in a machine
1999           is properly shutdown, so do not be surprised if this code does not
2000           initially work for you.
2001
2002 config ATAGS_PROC
2003         bool "Export atags in procfs"
2004         depends on ATAGS && KEXEC
2005         default y
2006         help
2007           Should the atags used to boot the kernel be exported in an "atags"
2008           file in procfs. Useful with kexec.
2009
2010 config CRASH_DUMP
2011         bool "Build kdump crash kernel (EXPERIMENTAL)"
2012         help
2013           Generate crash dump after being started by kexec. This should
2014           be normally only set in special crash dump kernels which are
2015           loaded in the main kernel with kexec-tools into a specially
2016           reserved region and then later executed after a crash by
2017           kdump/kexec. The crash dump kernel must be compiled to a
2018           memory address not used by the main kernel
2019
2020           For more details see Documentation/kdump/kdump.txt
2021
2022 config AUTO_ZRELADDR
2023         bool "Auto calculation of the decompressed kernel image address"
2024         help
2025           ZRELADDR is the physical address where the decompressed kernel
2026           image will be placed. If AUTO_ZRELADDR is selected, the address
2027           will be determined at run-time by masking the current IP with
2028           0xf8000000. This assumes the zImage being placed in the first 128MB
2029           from start of memory.
2030
2031 endmenu
2032
2033 menu "CPU Power Management"
2034
2035 source "drivers/cpufreq/Kconfig"
2036
2037 source "drivers/cpuidle/Kconfig"
2038
2039 endmenu
2040
2041 menu "Floating point emulation"
2042
2043 comment "At least one emulation must be selected"
2044
2045 config FPE_NWFPE
2046         bool "NWFPE math emulation"
2047         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2048         ---help---
2049           Say Y to include the NWFPE floating point emulator in the kernel.
2050           This is necessary to run most binaries. Linux does not currently
2051           support floating point hardware so you need to say Y here even if
2052           your machine has an FPA or floating point co-processor podule.
2053
2054           You may say N here if you are going to load the Acorn FPEmulator
2055           early in the bootup.
2056
2057 config FPE_NWFPE_XP
2058         bool "Support extended precision"
2059         depends on FPE_NWFPE
2060         help
2061           Say Y to include 80-bit support in the kernel floating-point
2062           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2063           Note that gcc does not generate 80-bit operations by default,
2064           so in most cases this option only enlarges the size of the
2065           floating point emulator without any good reason.
2066
2067           You almost surely want to say N here.
2068
2069 config FPE_FASTFPE
2070         bool "FastFPE math emulation (EXPERIMENTAL)"
2071         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2072         ---help---
2073           Say Y here to include the FAST floating point emulator in the kernel.
2074           This is an experimental much faster emulator which now also has full
2075           precision for the mantissa.  It does not support any exceptions.
2076           It is very simple, and approximately 3-6 times faster than NWFPE.
2077
2078           It should be sufficient for most programs.  It may be not suitable
2079           for scientific calculations, but you have to check this for yourself.
2080           If you do not feel you need a faster FP emulation you should better
2081           choose NWFPE.
2082
2083 config VFP
2084         bool "VFP-format floating point maths"
2085         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2086         help
2087           Say Y to include VFP support code in the kernel. This is needed
2088           if your hardware includes a VFP unit.
2089
2090           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2091           release notes and additional status information.
2092
2093           Say N if your target does not have VFP hardware.
2094
2095 config VFPv3
2096         bool
2097         depends on VFP
2098         default y if CPU_V7
2099
2100 config NEON
2101         bool "Advanced SIMD (NEON) Extension support"
2102         depends on VFPv3 && CPU_V7
2103         help
2104           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2105           Extension.
2106
2107 config KERNEL_MODE_NEON
2108         bool "Support for NEON in kernel mode"
2109         depends on NEON && AEABI
2110         help
2111           Say Y to include support for NEON in kernel mode.
2112
2113 endmenu
2114
2115 menu "Userspace binary formats"
2116
2117 source "fs/Kconfig.binfmt"
2118
2119 config ARTHUR
2120         tristate "RISC OS personality"
2121         depends on !AEABI
2122         help
2123           Say Y here to include the kernel code necessary if you want to run
2124           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2125           experimental; if this sounds frightening, say N and sleep in peace.
2126           You can also say M here to compile this support as a module (which
2127           will be called arthur).
2128
2129 endmenu
2130
2131 menu "Power management options"
2132
2133 source "kernel/power/Kconfig"
2134
2135 config ARCH_SUSPEND_POSSIBLE
2136         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2137                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2138         def_bool y
2139
2140 config ARM_CPU_SUSPEND
2141         def_bool PM_SLEEP
2142
2143 config ARCH_HIBERNATION_POSSIBLE
2144         bool
2145         depends on MMU
2146         default y if ARCH_SUSPEND_POSSIBLE
2147
2148 endmenu
2149
2150 source "net/Kconfig"
2151
2152 source "drivers/Kconfig"
2153
2154 source "fs/Kconfig"
2155
2156 source "arch/arm/Kconfig.debug"
2157
2158 source "security/Kconfig"
2159
2160 source "crypto/Kconfig"
2161
2162 source "lib/Kconfig"
2163
2164 source "arch/arm/kvm/Kconfig"