arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_IRQ_SHOW_LEVEL
  25         select GENERIC_PCI_IOMAP
  26         select GENERIC_SCHED_CLOCK
  27         select GENERIC_SMP_IDLE_THREAD
  28         select GENERIC_STRNCPY_FROM_USER
  29         select GENERIC_STRNLEN_USER
  30         select HANDLE_DOMAIN_IRQ
  31         select HARDIRQS_SW_RESEND
  32         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  33         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  34         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  35         select HAVE_ARCH_KGDB
  36         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_TRACEHOOK
  38         select HAVE_BPF_JIT
  39         select HAVE_CC_STACKPROTECTOR
  40         select HAVE_CONTEXT_TRACKING
  41         select HAVE_C_RECORDMCOUNT
  42         select HAVE_DEBUG_KMEMLEAK
  43         select HAVE_DMA_API_DEBUG
  44         select HAVE_DMA_ATTRS
  45         select HAVE_DMA_CONTIGUOUS if MMU
  46         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  47         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  48         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  49         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  50         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  51         select HAVE_GENERIC_DMA_COHERENT
  52         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  53         select HAVE_IDE if PCI || ISA || PCMCIA
  54         select HAVE_IRQ_TIME_ACCOUNTING
  55         select HAVE_KERNEL_GZIP
  56         select HAVE_KERNEL_LZ4
  57         select HAVE_KERNEL_LZMA
  58         select HAVE_KERNEL_LZO
  59         select HAVE_KERNEL_XZ
  60         select HAVE_KPROBES if !XIP_KERNEL
  61         select HAVE_KRETPROBES if (HAVE_KPROBES)
  62         select HAVE_MEMBLOCK
  63         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  64         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  65         select HAVE_OPTPROBES if !THUMB2_KERNEL
  66         select HAVE_PERF_EVENTS
  67         select HAVE_PERF_REGS
  68         select HAVE_PERF_USER_STACK_DUMP
  69         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  70         select HAVE_REGS_AND_STACK_ACCESS_API
  71         select HAVE_SYSCALL_TRACEPOINTS
  72         select HAVE_UID16
  73         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  74         select IRQ_FORCED_THREADING
  75         select MODULES_USE_ELF_REL
  76         select NO_BOOTMEM
  77         select OLD_SIGACTION
  78         select OLD_SIGSUSPEND3
  79         select PERF_USE_VMALLOC
  80         select RTC_LIB
  81         select SYS_SUPPORTS_APM_EMULATION
  82         # Above selects are sorted alphabetically; please add new ones
  83         # according to that.  Thanks.
  84         help
  85           The ARM series is a line of low-power-consumption RISC chip designs
  86           licensed by ARM Ltd and targeted at embedded applications and
  87           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  88           manufactured, but legacy ARM-based PC hardware remains popular in
  89           Europe.  There is an ARM Linux project with a web page at
  90           <http://www.arm.linux.org.uk/>.
  91
  92 config ARM_HAS_SG_CHAIN
  93         select ARCH_HAS_SG_CHAIN
  94         bool
  95
  96 config NEED_SG_DMA_LENGTH
  97         bool
  98
  99 config ARM_DMA_USE_IOMMU
 100         bool
 101         select ARM_HAS_SG_CHAIN
 102         select NEED_SG_DMA_LENGTH
 103
 104 if ARM_DMA_USE_IOMMU
 105
 106 config ARM_DMA_IOMMU_ALIGNMENT
 107         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 108         range 4 9
 109         default 8
 110         help
 111           DMA mapping framework by default aligns all buffers to the smallest
 112           PAGE_SIZE order which is greater than or equal to the requested buffer
 113           size. This works well for buffers up to a few hundreds kilobytes, but
 114           for larger buffers it just a waste of address space. Drivers which has
 115           relatively small addressing window (like 64Mib) might run out of
 116           virtual space with just a few allocations.
 117
 118           With this parameter you can specify the maximum PAGE_SIZE order for
 119           DMA IOMMU buffers. Larger buffers will be aligned only to this
 120           specified order. The order is expressed as a power of two multiplied
 121           by the PAGE_SIZE.
 122
 123 endif
 124
 125 config MIGHT_HAVE_PCI
 126         bool
 127
 128 config SYS_SUPPORTS_APM_EMULATION
 129         bool
 130
 131 config HAVE_TCM
 132         bool
 133         select GENERIC_ALLOCATOR
 134
 135 config HAVE_PROC_CPU
 136         bool
 137
 138 config NO_IOPORT_MAP
 139         bool
 140
 141 config EISA
 142         bool
 143         ---help---
 144           The Extended Industry Standard Architecture (EISA) bus was
 145           developed as an open alternative to the IBM MicroChannel bus.
 146
 147           The EISA bus provided some of the features of the IBM MicroChannel
 148           bus while maintaining backward compatibility with cards made for
 149           the older ISA bus.  The EISA bus saw limited use between 1988 and
 150           1995 when it was made obsolete by the PCI bus.
 151
 152           Say Y here if you are building a kernel for an EISA-based machine.
 153
 154           Otherwise, say N.
 155
 156 config SBUS
 157         bool
 158
 159 config STACKTRACE_SUPPORT
 160         bool
 161         default y
 162
 163 config HAVE_LATENCYTOP_SUPPORT
 164         bool
 165         depends on !SMP
 166         default y
 167
 168 config LOCKDEP_SUPPORT
 169         bool
 170         default y
 171
 172 config TRACE_IRQFLAGS_SUPPORT
 173         bool
 174         default y
 175
 176 config RWSEM_XCHGADD_ALGORITHM
 177         bool
 178         default y
 179
 180 config ARCH_HAS_ILOG2_U32
 181         bool
 182
 183 config ARCH_HAS_ILOG2_U64
 184         bool
 185
 186 config ARCH_HAS_BANDGAP
 187         bool
 188
 189 config GENERIC_HWEIGHT
 190         bool
 191         default y
 192
 193 config GENERIC_CALIBRATE_DELAY
 194         bool
 195         default y
 196
 197 config ARCH_MAY_HAVE_PC_FDC
 198         bool
 199
 200 config ZONE_DMA
 201         bool
 202
 203 config NEED_DMA_MAP_STATE
 204        def_bool y
 205
 206 config ARCH_SUPPORTS_UPROBES
 207         def_bool y
 208
 209 config ARCH_HAS_DMA_SET_COHERENT_MASK
 210         bool
 211
 212 config GENERIC_ISA_DMA
 213         bool
 214
 215 config FIQ
 216         bool
 217
 218 config NEED_RET_TO_USER
 219         bool
 220
 221 config ARCH_MTD_XIP
 222         bool
 223
 224 config VECTORS_BASE
 225         hex
 226         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 227         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 228         default 0x00000000
 229         help
 230           The base address of exception vectors.  This must be two pages
 231           in size.
 232
 233 config ARM_PATCH_PHYS_VIRT
 234         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 235         default y
 236         depends on !XIP_KERNEL && MMU
 237         depends on !ARCH_REALVIEW || !SPARSEMEM
 238         help
 239           Patch phys-to-virt and virt-to-phys translation functions at
 240           boot and module load time according to the position of the
 241           kernel in system memory.
 242
 243           This can only be used with non-XIP MMU kernels where the base
 244           of physical memory is at a 16MB boundary.
 245
 246           Only disable this option if you know that you do not require
 247           this feature (eg, building a kernel for a single machine) and
 248           you need to shrink the kernel to the minimal size.
 249
 250 config NEED_MACH_IO_H
 251         bool
 252         help
 253           Select this when mach/io.h is required to provide special
 254           definitions for this platform.  The need for mach/io.h should
 255           be avoided when possible.
 256
 257 config NEED_MACH_MEMORY_H
 258         bool
 259         help
 260           Select this when mach/memory.h is required to provide special
 261           definitions for this platform.  The need for mach/memory.h should
 262           be avoided when possible.
 263
 264 config PHYS_OFFSET
 265         hex "Physical address of main memory" if MMU
 266         depends on !ARM_PATCH_PHYS_VIRT
 267         default DRAM_BASE if !MMU
 268         default 0x00000000 if ARCH_EBSA110 || \
 269                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 270                         ARCH_FOOTBRIDGE || \
 271                         ARCH_INTEGRATOR || \
 272                         ARCH_IOP13XX || \
 273                         ARCH_KS8695 || \
 274                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 275         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 276         default 0x20000000 if ARCH_S5PV210
 277         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 278         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 279         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 280         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 281         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 282         help
 283           Please provide the physical address corresponding to the
 284           location of main memory in your system.
 285
 286 config GENERIC_BUG
 287         def_bool y
 288         depends on BUG
 289
 290 config PGTABLE_LEVELS
 291         int
 292         default 3 if ARM_LPAE
 293         default 2
 294
 295 source "init/Kconfig"
 296
 297 source "kernel/Kconfig.freezer"
 298
 299 menu "System Type"
 300
 301 config MMU
 302         bool "MMU-based Paged Memory Management Support"
 303         default y
 304         help
 305           Select if you want MMU-based virtualised addressing space
 306           support by paged memory management. If unsure, say 'Y'.
 307
 308 #
 309 # The "ARM system type" choice list is ordered alphabetically by option
 310 # text.  Please add new entries in the option alphabetic order.
 311 #
 312 choice
 313         prompt "ARM system type"
 314         default ARCH_VERSATILE if !MMU
 315         default ARCH_MULTIPLATFORM if MMU
 316
 317 config ARCH_MULTIPLATFORM
 318         bool "Allow multiple platforms to be selected"
 319         depends on MMU
 320         select ARCH_WANT_OPTIONAL_GPIOLIB
 321         select ARM_HAS_SG_CHAIN
 322         select ARM_PATCH_PHYS_VIRT
 323         select AUTO_ZRELADDR
 324         select CLKSRC_OF
 325         select COMMON_CLK
 326         select GENERIC_CLOCKEVENTS
 327         select MIGHT_HAVE_PCI
 328         select MULTI_IRQ_HANDLER
 329         select SPARSE_IRQ
 330         select USE_OF
 331
 332 config ARCH_REALVIEW
 333         bool "ARM Ltd. RealView family"
 334         select ARCH_WANT_OPTIONAL_GPIOLIB
 335         select ARM_AMBA
 336         select ARM_TIMER_SP804
 337         select COMMON_CLK
 338         select COMMON_CLK_VERSATILE
 339         select GENERIC_CLOCKEVENTS
 340         select GPIO_PL061 if GPIOLIB
 341         select ICST
 342         select NEED_MACH_MEMORY_H
 343         select PLAT_VERSATILE
 344         select PLAT_VERSATILE_SCHED_CLOCK
 345         help
 346           This enables support for ARM Ltd RealView boards.
 347
 348 config ARCH_VERSATILE
 349         bool "ARM Ltd. Versatile family"
 350         select ARCH_WANT_OPTIONAL_GPIOLIB
 351         select ARM_AMBA
 352         select ARM_TIMER_SP804
 353         select ARM_VIC
 354         select CLKDEV_LOOKUP
 355         select GENERIC_CLOCKEVENTS
 356         select HAVE_MACH_CLKDEV
 357         select ICST
 358         select PLAT_VERSATILE
 359         select PLAT_VERSATILE_CLOCK
 360         select PLAT_VERSATILE_SCHED_CLOCK
 361         select VERSATILE_FPGA_IRQ
 362         help
 363           This enables support for ARM Ltd Versatile board.
 364
 365 config ARCH_AT91
 366         bool "Atmel AT91"
 367         select ARCH_REQUIRE_GPIOLIB
 368         select CLKDEV_LOOKUP
 369         select IRQ_DOMAIN
 370         select PINCTRL
 371         select PINCTRL_AT91
 372         select SOC_BUS
 373         select USE_OF
 374         help
 375           This enables support for systems based on Atmel
 376           AT91RM9200, AT91SAM9 and SAMA5 processors.
 377
 378 config ARCH_CLPS711X
 379         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 380         select ARCH_REQUIRE_GPIOLIB
 381         select AUTO_ZRELADDR
 382         select CLKSRC_MMIO
 383         select COMMON_CLK
 384         select CPU_ARM720T
 385         select GENERIC_CLOCKEVENTS
 386         select MFD_SYSCON
 387         select SOC_BUS
 388         help
 389           Support for Cirrus Logic 711x/721x/731x based boards.
 390
 391 config ARCH_GEMINI
 392         bool "Cortina Systems Gemini"
 393         select ARCH_REQUIRE_GPIOLIB
 394         select CLKSRC_MMIO
 395         select CPU_FA526
 396         select GENERIC_CLOCKEVENTS
 397         help
 398           Support for the Cortina Systems Gemini family SoCs
 399
 400 config ARCH_EBSA110
 401         bool "EBSA-110"
 402         select ARCH_USES_GETTIMEOFFSET
 403         select CPU_SA110
 404         select ISA
 405         select NEED_MACH_IO_H
 406         select NEED_MACH_MEMORY_H
 407         select NO_IOPORT_MAP
 408         help
 409           This is an evaluation board for the StrongARM processor available
 410           from Digital. It has limited hardware on-board, including an
 411           Ethernet interface, two PCMCIA sockets, two serial ports and a
 412           parallel port.
 413
 414 config ARCH_EFM32
 415         bool "Energy Micro efm32"
 416         depends on !MMU
 417         select ARCH_REQUIRE_GPIOLIB
 418         select ARM_NVIC
 419         select AUTO_ZRELADDR
 420         select CLKSRC_OF
 421         select COMMON_CLK
 422         select CPU_V7M
 423         select GENERIC_CLOCKEVENTS
 424         select NO_DMA
 425         select NO_IOPORT_MAP
 426         select SPARSE_IRQ
 427         select USE_OF
 428         help
 429           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 430           processors.
 431
 432 config ARCH_EP93XX
 433         bool "EP93xx-based"
 434         select ARCH_HAS_HOLES_MEMORYMODEL
 435         select ARCH_REQUIRE_GPIOLIB
 436         select ARCH_USES_GETTIMEOFFSET
 437         select ARM_AMBA
 438         select ARM_VIC
 439         select CLKDEV_LOOKUP
 440         select CPU_ARM920T
 441         help
 442           This enables support for the Cirrus EP93xx series of CPUs.
 443
 444 config ARCH_FOOTBRIDGE
 445         bool "FootBridge"
 446         select CPU_SA110
 447         select FOOTBRIDGE
 448         select GENERIC_CLOCKEVENTS
 449         select HAVE_IDE
 450         select NEED_MACH_IO_H if !MMU
 451         select NEED_MACH_MEMORY_H
 452         help
 453           Support for systems based on the DC21285 companion chip
 454           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 455
 456 config ARCH_NETX
 457         bool "Hilscher NetX based"
 458         select ARM_VIC
 459         select CLKSRC_MMIO
 460         select CPU_ARM926T
 461         select GENERIC_CLOCKEVENTS
 462         help
 463           This enables support for systems based on the Hilscher NetX Soc
 464
 465 config ARCH_IOP13XX
 466         bool "IOP13xx-based"
 467         depends on MMU
 468         select CPU_XSC3
 469         select NEED_MACH_MEMORY_H
 470         select NEED_RET_TO_USER
 471         select PCI
 472         select PLAT_IOP
 473         select VMSPLIT_1G
 474         select SPARSE_IRQ
 475         help
 476           Support for Intel's IOP13XX (XScale) family of processors.
 477
 478 config ARCH_IOP32X
 479         bool "IOP32x-based"
 480         depends on MMU
 481         select ARCH_REQUIRE_GPIOLIB
 482         select CPU_XSCALE
 483         select GPIO_IOP
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         help
 488           Support for Intel's 80219 and IOP32X (XScale) family of
 489           processors.
 490
 491 config ARCH_IOP33X
 492         bool "IOP33x-based"
 493         depends on MMU
 494         select ARCH_REQUIRE_GPIOLIB
 495         select CPU_XSCALE
 496         select GPIO_IOP
 497         select NEED_RET_TO_USER
 498         select PCI
 499         select PLAT_IOP
 500         help
 501           Support for Intel's IOP33X (XScale) family of processors.
 502
 503 config ARCH_IXP4XX
 504         bool "IXP4xx-based"
 505         depends on MMU
 506         select ARCH_HAS_DMA_SET_COHERENT_MASK
 507         select ARCH_REQUIRE_GPIOLIB
 508         select ARCH_SUPPORTS_BIG_ENDIAN
 509         select CLKSRC_MMIO
 510         select CPU_XSCALE
 511         select DMABOUNCE if PCI
 512         select GENERIC_CLOCKEVENTS
 513         select MIGHT_HAVE_PCI
 514         select NEED_MACH_IO_H
 515         select USB_EHCI_BIG_ENDIAN_DESC
 516         select USB_EHCI_BIG_ENDIAN_MMIO
 517         help
 518           Support for Intel's IXP4XX (XScale) family of processors.
 519
 520 config ARCH_DOVE
 521         bool "Marvell Dove"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_PJ4
 524         select GENERIC_CLOCKEVENTS
 525         select MIGHT_HAVE_PCI
 526         select MVEBU_MBUS
 527         select PINCTRL
 528         select PINCTRL_DOVE
 529         select PLAT_ORION_LEGACY
 530         help
 531           Support for the Marvell Dove SoC 88AP510
 532
 533 config ARCH_MV78XX0
 534         bool "Marvell MV78xx0"
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select MVEBU_MBUS
 539         select PCI
 540         select PLAT_ORION_LEGACY
 541         help
 542           Support for the following Marvell MV78xx0 series SoCs:
 543           MV781x0, MV782x0.
 544
 545 config ARCH_ORION5X
 546         bool "Marvell Orion"
 547         depends on MMU
 548         select ARCH_REQUIRE_GPIOLIB
 549         select CPU_FEROCEON
 550         select GENERIC_CLOCKEVENTS
 551         select MVEBU_MBUS
 552         select PCI
 553         select PLAT_ORION_LEGACY
 554         help
 555           Support for the following Marvell Orion 5x series SoCs:
 556           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 557           Orion-2 (5281), Orion-1-90 (6183).
 558
 559 config ARCH_MMP
 560         bool "Marvell PXA168/910/MMP2"
 561         depends on MMU
 562         select ARCH_REQUIRE_GPIOLIB
 563         select CLKDEV_LOOKUP
 564         select GENERIC_ALLOCATOR
 565         select GENERIC_CLOCKEVENTS
 566         select GPIO_PXA
 567         select IRQ_DOMAIN
 568         select MULTI_IRQ_HANDLER
 569         select PINCTRL
 570         select PLAT_PXA
 571         select SPARSE_IRQ
 572         help
 573           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 574
 575 config ARCH_KS8695
 576         bool "Micrel/Kendin KS8695"
 577         select ARCH_REQUIRE_GPIOLIB
 578         select CLKSRC_MMIO
 579         select CPU_ARM922T
 580         select GENERIC_CLOCKEVENTS
 581         select NEED_MACH_MEMORY_H
 582         help
 583           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 584           System-on-Chip devices.
 585
 586 config ARCH_W90X900
 587         bool "Nuvoton W90X900 CPU"
 588         select ARCH_REQUIRE_GPIOLIB
 589         select CLKDEV_LOOKUP
 590         select CLKSRC_MMIO
 591         select CPU_ARM926T
 592         select GENERIC_CLOCKEVENTS
 593         help
 594           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 595           At present, the w90x900 has been renamed nuc900, regarding
 596           the ARM series product line, you can login the following
 597           link address to know more.
 598
 599           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 600                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 601
 602 config ARCH_LPC32XX
 603         bool "NXP LPC32XX"
 604         select ARCH_REQUIRE_GPIOLIB
 605         select ARM_AMBA
 606         select CLKDEV_LOOKUP
 607         select CLKSRC_MMIO
 608         select CPU_ARM926T
 609         select GENERIC_CLOCKEVENTS
 610         select HAVE_IDE
 611         select USE_OF
 612         help
 613           Support for the NXP LPC32XX family of processors
 614
 615 config ARCH_PXA
 616         bool "PXA2xx/PXA3xx-based"
 617         depends on MMU
 618         select ARCH_MTD_XIP
 619         select ARCH_REQUIRE_GPIOLIB
 620         select ARM_CPU_SUSPEND if PM
 621         select AUTO_ZRELADDR
 622         select CLKDEV_LOOKUP
 623         select CLKSRC_MMIO
 624         select CLKSRC_OF
 625         select GENERIC_CLOCKEVENTS
 626         select GPIO_PXA
 627         select HAVE_IDE
 628         select IRQ_DOMAIN
 629         select MULTI_IRQ_HANDLER
 630         select PLAT_PXA
 631         select SPARSE_IRQ
 632         help
 633           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 634
 635 config ARCH_SHMOBILE_LEGACY
 636         bool "Renesas ARM SoCs (non-multiplatform)"
 637         select ARCH_SHMOBILE
 638         select ARM_PATCH_PHYS_VIRT if MMU
 639         select CLKDEV_LOOKUP
 640         select CPU_V7
 641         select GENERIC_CLOCKEVENTS
 642         select HAVE_ARM_SCU if SMP
 643         select HAVE_ARM_TWD if SMP
 644         select HAVE_MACH_CLKDEV
 645         select HAVE_SMP
 646         select MIGHT_HAVE_CACHE_L2X0
 647         select MULTI_IRQ_HANDLER
 648         select NO_IOPORT_MAP
 649         select PINCTRL
 650         select PM_GENERIC_DOMAINS if PM
 651         select SH_CLK_CPG
 652         select SPARSE_IRQ
 653         help
 654           Support for Renesas ARM SoC platforms using a non-multiplatform
 655           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 656           and RZ families.
 657
 658 config ARCH_RPC
 659         bool "RiscPC"
 660         select ARCH_ACORN
 661         select ARCH_MAY_HAVE_PC_FDC
 662         select ARCH_SPARSEMEM_ENABLE
 663         select ARCH_USES_GETTIMEOFFSET
 664         select CPU_SA110
 665         select FIQ
 666         select HAVE_IDE
 667         select HAVE_PATA_PLATFORM
 668         select ISA_DMA_API
 669         select NEED_MACH_IO_H
 670         select NEED_MACH_MEMORY_H
 671         select NO_IOPORT_MAP
 672         select VIRT_TO_BUS
 673         help
 674           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 675           CD-ROM interface, serial and parallel port, and the floppy drive.
 676
 677 config ARCH_SA1100
 678         bool "SA1100-based"
 679         select ARCH_MTD_XIP
 680         select ARCH_REQUIRE_GPIOLIB
 681         select ARCH_SPARSEMEM_ENABLE
 682         select CLKDEV_LOOKUP
 683         select CLKSRC_MMIO
 684         select CPU_FREQ
 685         select CPU_SA1100
 686         select GENERIC_CLOCKEVENTS
 687         select HAVE_IDE
 688         select IRQ_DOMAIN
 689         select ISA
 690         select MULTI_IRQ_HANDLER
 691         select NEED_MACH_MEMORY_H
 692         select SPARSE_IRQ
 693         help
 694           Support for StrongARM 11x0 based boards.
 695
 696 config ARCH_S3C24XX
 697         bool "Samsung S3C24XX SoCs"
 698         select ARCH_REQUIRE_GPIOLIB
 699         select ATAGS
 700         select CLKDEV_LOOKUP
 701         select CLKSRC_SAMSUNG_PWM
 702         select GENERIC_CLOCKEVENTS
 703         select GPIO_SAMSUNG
 704         select HAVE_S3C2410_I2C if I2C
 705         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 706         select HAVE_S3C_RTC if RTC_CLASS
 707         select MULTI_IRQ_HANDLER
 708         select NEED_MACH_IO_H
 709         select SAMSUNG_ATAGS
 710         help
 711           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 712           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 713           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 714           Samsung SMDK2410 development board (and derivatives).
 715
 716 config ARCH_S3C64XX
 717         bool "Samsung S3C64XX"
 718         select ARCH_REQUIRE_GPIOLIB
 719         select ARM_AMBA
 720         select ARM_VIC
 721         select ATAGS
 722         select CLKDEV_LOOKUP
 723         select CLKSRC_SAMSUNG_PWM
 724         select COMMON_CLK_SAMSUNG
 725         select CPU_V6K
 726         select GENERIC_CLOCKEVENTS
 727         select GPIO_SAMSUNG
 728         select HAVE_S3C2410_I2C if I2C
 729         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 730         select HAVE_TCM
 731         select NO_IOPORT_MAP
 732         select PLAT_SAMSUNG
 733         select PM_GENERIC_DOMAINS if PM
 734         select S3C_DEV_NAND
 735         select S3C_GPIO_TRACK
 736         select SAMSUNG_ATAGS
 737         select SAMSUNG_WAKEMASK
 738         select SAMSUNG_WDT_RESET
 739         help
 740           Samsung S3C64XX series based systems
 741
 742 config ARCH_DAVINCI
 743         bool "TI DaVinci"
 744         select ARCH_HAS_HOLES_MEMORYMODEL
 745         select ARCH_REQUIRE_GPIOLIB
 746         select CLKDEV_LOOKUP
 747         select GENERIC_ALLOCATOR
 748         select GENERIC_CLOCKEVENTS
 749         select GENERIC_IRQ_CHIP
 750         select HAVE_IDE
 751         select TI_PRIV_EDMA
 752         select USE_OF
 753         select ZONE_DMA
 754         help
 755           Support for TI's DaVinci platform.
 756
 757 config ARCH_OMAP1
 758         bool "TI OMAP1"
 759         depends on MMU
 760         select ARCH_HAS_HOLES_MEMORYMODEL
 761         select ARCH_OMAP
 762         select ARCH_REQUIRE_GPIOLIB
 763         select CLKDEV_LOOKUP
 764         select CLKSRC_MMIO
 765         select GENERIC_CLOCKEVENTS
 766         select GENERIC_IRQ_CHIP
 767         select HAVE_IDE
 768         select IRQ_DOMAIN
 769         select NEED_MACH_IO_H if PCCARD
 770         select NEED_MACH_MEMORY_H
 771         help
 772           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 773
 774 endchoice
 775
 776 menu "Multiple platform selection"
 777         depends on ARCH_MULTIPLATFORM
 778
 779 comment "CPU Core family selection"
 780
 781 config ARCH_MULTI_V4
 782         bool "ARMv4 based platforms (FA526)"
 783         depends on !ARCH_MULTI_V6_V7
 784         select ARCH_MULTI_V4_V5
 785         select CPU_FA526
 786
 787 config ARCH_MULTI_V4T
 788         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 789         depends on !ARCH_MULTI_V6_V7
 790         select ARCH_MULTI_V4_V5
 791         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 792                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 793                 CPU_ARM925T || CPU_ARM940T)
 794
 795 config ARCH_MULTI_V5
 796         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 797         depends on !ARCH_MULTI_V6_V7
 798         select ARCH_MULTI_V4_V5
 799         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 800                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 801                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 802
 803 config ARCH_MULTI_V4_V5
 804         bool
 805
 806 config ARCH_MULTI_V6
 807         bool "ARMv6 based platforms (ARM11)"
 808         select ARCH_MULTI_V6_V7
 809         select CPU_V6K
 810
 811 config ARCH_MULTI_V7
 812         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 813         default y
 814         select ARCH_MULTI_V6_V7
 815         select CPU_V7
 816         select HAVE_SMP
 817
 818 config ARCH_MULTI_V6_V7
 819         bool
 820         select MIGHT_HAVE_CACHE_L2X0
 821
 822 config ARCH_MULTI_CPU_AUTO
 823         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 824         select ARCH_MULTI_V5
 825
 826 endmenu
 827
 828 config ARCH_VIRT
 829         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 830         select ARM_AMBA
 831         select ARM_GIC
 832         select ARM_PSCI
 833         select HAVE_ARM_ARCH_TIMER
 834
 835 #
 836 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 837 # Kconfigs may be included either alphabetically (according to the
 838 # plat- suffix) or along side the corresponding mach-* source.
 839 #
 840 source "arch/arm/mach-mvebu/Kconfig"
 841
 842 source "arch/arm/mach-alpine/Kconfig"
 843
 844 source "arch/arm/mach-asm9260/Kconfig"
 845
 846 source "arch/arm/mach-at91/Kconfig"
 847
 848 source "arch/arm/mach-axxia/Kconfig"
 849
 850 source "arch/arm/mach-bcm/Kconfig"
 851
 852 source "arch/arm/mach-berlin/Kconfig"
 853
 854 source "arch/arm/mach-clps711x/Kconfig"
 855
 856 source "arch/arm/mach-cns3xxx/Kconfig"
 857
 858 source "arch/arm/mach-davinci/Kconfig"
 859
 860 source "arch/arm/mach-digicolor/Kconfig"
 861
 862 source "arch/arm/mach-dove/Kconfig"
 863
 864 source "arch/arm/mach-ep93xx/Kconfig"
 865
 866 source "arch/arm/mach-footbridge/Kconfig"
 867
 868 source "arch/arm/mach-gemini/Kconfig"
 869
 870 source "arch/arm/mach-highbank/Kconfig"
 871
 872 source "arch/arm/mach-hisi/Kconfig"
 873
 874 source "arch/arm/mach-integrator/Kconfig"
 875
 876 source "arch/arm/mach-iop32x/Kconfig"
 877
 878 source "arch/arm/mach-iop33x/Kconfig"
 879
 880 source "arch/arm/mach-iop13xx/Kconfig"
 881
 882 source "arch/arm/mach-ixp4xx/Kconfig"
 883
 884 source "arch/arm/mach-keystone/Kconfig"
 885
 886 source "arch/arm/mach-ks8695/Kconfig"
 887
 888 source "arch/arm/mach-meson/Kconfig"
 889
 890 source "arch/arm/mach-moxart/Kconfig"
 891
 892 source "arch/arm/mach-mv78xx0/Kconfig"
 893
 894 source "arch/arm/mach-imx/Kconfig"
 895
 896 source "arch/arm/mach-mediatek/Kconfig"
 897
 898 source "arch/arm/mach-mxs/Kconfig"
 899
 900 source "arch/arm/mach-netx/Kconfig"
 901
 902 source "arch/arm/mach-nomadik/Kconfig"
 903
 904 source "arch/arm/mach-nspire/Kconfig"
 905
 906 source "arch/arm/plat-omap/Kconfig"
 907
 908 source "arch/arm/mach-omap1/Kconfig"
 909
 910 source "arch/arm/mach-omap2/Kconfig"
 911
 912 source "arch/arm/mach-orion5x/Kconfig"
 913
 914 source "arch/arm/mach-picoxcell/Kconfig"
 915
 916 source "arch/arm/mach-pxa/Kconfig"
 917 source "arch/arm/plat-pxa/Kconfig"
 918
 919 source "arch/arm/mach-mmp/Kconfig"
 920
 921 source "arch/arm/mach-qcom/Kconfig"
 922
 923 source "arch/arm/mach-realview/Kconfig"
 924
 925 source "arch/arm/mach-rockchip/Kconfig"
 926
 927 source "arch/arm/mach-sa1100/Kconfig"
 928
 929 source "arch/arm/mach-socfpga/Kconfig"
 930
 931 source "arch/arm/mach-spear/Kconfig"
 932
 933 source "arch/arm/mach-sti/Kconfig"
 934
 935 source "arch/arm/mach-s3c24xx/Kconfig"
 936
 937 source "arch/arm/mach-s3c64xx/Kconfig"
 938
 939 source "arch/arm/mach-s5pv210/Kconfig"
 940
 941 source "arch/arm/mach-exynos/Kconfig"
 942 source "arch/arm/plat-samsung/Kconfig"
 943
 944 source "arch/arm/mach-shmobile/Kconfig"
 945
 946 source "arch/arm/mach-sunxi/Kconfig"
 947
 948 source "arch/arm/mach-prima2/Kconfig"
 949
 950 source "arch/arm/mach-tegra/Kconfig"
 951
 952 source "arch/arm/mach-u300/Kconfig"
 953
 954 source "arch/arm/mach-ux500/Kconfig"
 955
 956 source "arch/arm/mach-versatile/Kconfig"
 957
 958 source "arch/arm/mach-vexpress/Kconfig"
 959 source "arch/arm/plat-versatile/Kconfig"
 960
 961 source "arch/arm/mach-vt8500/Kconfig"
 962
 963 source "arch/arm/mach-w90x900/Kconfig"
 964
 965 source "arch/arm/mach-zynq/Kconfig"
 966
 967 # Definitions to make life easier
 968 config ARCH_ACORN
 969         bool
 970
 971 config PLAT_IOP
 972         bool
 973         select GENERIC_CLOCKEVENTS
 974
 975 config PLAT_ORION
 976         bool
 977         select CLKSRC_MMIO
 978         select COMMON_CLK
 979         select GENERIC_IRQ_CHIP
 980         select IRQ_DOMAIN
 981
 982 config PLAT_ORION_LEGACY
 983         bool
 984         select PLAT_ORION
 985
 986 config PLAT_PXA
 987         bool
 988
 989 config PLAT_VERSATILE
 990         bool
 991
 992 config ARM_TIMER_SP804
 993         bool
 994         select CLKSRC_MMIO
 995         select CLKSRC_OF if OF
 996
 997 source "arch/arm/firmware/Kconfig"
 998
 999 source arch/arm/mm/Kconfig
1000
1001 config IWMMXT
1002         bool "Enable iWMMXt support"
1003         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1004         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1005         help
1006           Enable support for iWMMXt context switching at run time if
1007           running on a CPU that supports it.
1008
1009 config MULTI_IRQ_HANDLER
1010         bool
1011         help
1012           Allow each machine to specify it's own IRQ handler at run time.
1013
1014 if !MMU
1015 source "arch/arm/Kconfig-nommu"
1016 endif
1017
1018 config PJ4B_ERRATA_4742
1019         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1020         depends on CPU_PJ4B && MACH_ARMADA_370
1021         default y
1022         help
1023           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1024           Event (WFE) IDLE states, a specific timing sensitivity exists between
1025           the retiring WFI/WFE instructions and the newly issued subsequent
1026           instructions.  This sensitivity can result in a CPU hang scenario.
1027           Workaround:
1028           The software must insert either a Data Synchronization Barrier (DSB)
1029           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1030           instruction
1031
1032 config ARM_ERRATA_326103
1033         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1034         depends on CPU_V6
1035         help
1036           Executing a SWP instruction to read-only memory does not set bit 11
1037           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1038           treat the access as a read, preventing a COW from occurring and
1039           causing the faulting task to livelock.
1040
1041 config ARM_ERRATA_411920
1042         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1043         depends on CPU_V6 || CPU_V6K
1044         help
1045           Invalidation of the Instruction Cache operation can
1046           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1047           It does not affect the MPCore. This option enables the ARM Ltd.
1048           recommended workaround.
1049
1050 config ARM_ERRATA_430973
1051         bool "ARM errata: Stale prediction on replaced interworking branch"
1052         depends on CPU_V7
1053         help
1054           This option enables the workaround for the 430973 Cortex-A8
1055           r1p* erratum. If a code sequence containing an ARM/Thumb
1056           interworking branch is replaced with another code sequence at the
1057           same virtual address, whether due to self-modifying code or virtual
1058           to physical address re-mapping, Cortex-A8 does not recover from the
1059           stale interworking branch prediction. This results in Cortex-A8
1060           executing the new code sequence in the incorrect ARM or Thumb state.
1061           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1062           and also flushes the branch target cache at every context switch.
1063           Note that setting specific bits in the ACTLR register may not be
1064           available in non-secure mode.
1065
1066 config ARM_ERRATA_458693
1067         bool "ARM errata: Processor deadlock when a false hazard is created"
1068         depends on CPU_V7
1069         depends on !ARCH_MULTIPLATFORM
1070         help
1071           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1072           erratum. For very specific sequences of memory operations, it is
1073           possible for a hazard condition intended for a cache line to instead
1074           be incorrectly associated with a different cache line. This false
1075           hazard might then cause a processor deadlock. The workaround enables
1076           the L1 caching of the NEON accesses and disables the PLD instruction
1077           in the ACTLR register. Note that setting specific bits in the ACTLR
1078           register may not be available in non-secure mode.
1079
1080 config ARM_ERRATA_460075
1081         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1082         depends on CPU_V7
1083         depends on !ARCH_MULTIPLATFORM
1084         help
1085           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1086           erratum. Any asynchronous access to the L2 cache may encounter a
1087           situation in which recent store transactions to the L2 cache are lost
1088           and overwritten with stale memory contents from external memory. The
1089           workaround disables the write-allocate mode for the L2 cache via the
1090           ACTLR register. Note that setting specific bits in the ACTLR register
1091           may not be available in non-secure mode.
1092
1093 config ARM_ERRATA_742230
1094         bool "ARM errata: DMB operation may be faulty"
1095         depends on CPU_V7 && SMP
1096         depends on !ARCH_MULTIPLATFORM
1097         help
1098           This option enables the workaround for the 742230 Cortex-A9
1099           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1100           between two write operations may not ensure the correct visibility
1101           ordering of the two writes. This workaround sets a specific bit in
1102           the diagnostic register of the Cortex-A9 which causes the DMB
1103           instruction to behave as a DSB, ensuring the correct behaviour of
1104           the two writes.
1105
1106 config ARM_ERRATA_742231
1107         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1108         depends on CPU_V7 && SMP
1109         depends on !ARCH_MULTIPLATFORM
1110         help
1111           This option enables the workaround for the 742231 Cortex-A9
1112           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1113           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1114           accessing some data located in the same cache line, may get corrupted
1115           data due to bad handling of the address hazard when the line gets
1116           replaced from one of the CPUs at the same time as another CPU is
1117           accessing it. This workaround sets specific bits in the diagnostic
1118           register of the Cortex-A9 which reduces the linefill issuing
1119           capabilities of the processor.
1120
1121 config ARM_ERRATA_643719
1122         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1123         depends on CPU_V7 && SMP
1124         default y
1125         help
1126           This option enables the workaround for the 643719 Cortex-A9 (prior to
1127           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1128           register returns zero when it should return one. The workaround
1129           corrects this value, ensuring cache maintenance operations which use
1130           it behave as intended and avoiding data corruption.
1131
1132 config ARM_ERRATA_720789
1133         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1134         depends on CPU_V7
1135         help
1136           This option enables the workaround for the 720789 Cortex-A9 (prior to
1137           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1138           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1139           As a consequence of this erratum, some TLB entries which should be
1140           invalidated are not, resulting in an incoherency in the system page
1141           tables. The workaround changes the TLB flushing routines to invalidate
1142           entries regardless of the ASID.
1143
1144 config ARM_ERRATA_743622
1145         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1146         depends on CPU_V7
1147         depends on !ARCH_MULTIPLATFORM
1148         help
1149           This option enables the workaround for the 743622 Cortex-A9
1150           (r2p*) erratum. Under very rare conditions, a faulty
1151           optimisation in the Cortex-A9 Store Buffer may lead to data
1152           corruption. This workaround sets a specific bit in the diagnostic
1153           register of the Cortex-A9 which disables the Store Buffer
1154           optimisation, preventing the defect from occurring. This has no
1155           visible impact on the overall performance or power consumption of the
1156           processor.
1157
1158 config ARM_ERRATA_751472
1159         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1160         depends on CPU_V7
1161         depends on !ARCH_MULTIPLATFORM
1162         help
1163           This option enables the workaround for the 751472 Cortex-A9 (prior
1164           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1165           completion of a following broadcasted operation if the second
1166           operation is received by a CPU before the ICIALLUIS has completed,
1167           potentially leading to corrupted entries in the cache or TLB.
1168
1169 config ARM_ERRATA_754322
1170         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1171         depends on CPU_V7
1172         help
1173           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1174           r3p*) erratum. A speculative memory access may cause a page table walk
1175           which starts prior to an ASID switch but completes afterwards. This
1176           can populate the micro-TLB with a stale entry which may be hit with
1177           the new ASID. This workaround places two dsb instructions in the mm
1178           switching code so that no page table walks can cross the ASID switch.
1179
1180 config ARM_ERRATA_754327
1181         bool "ARM errata: no automatic Store Buffer drain"
1182         depends on CPU_V7 && SMP
1183         help
1184           This option enables the workaround for the 754327 Cortex-A9 (prior to
1185           r2p0) erratum. The Store Buffer does not have any automatic draining
1186           mechanism and therefore a livelock may occur if an external agent
1187           continuously polls a memory location waiting to observe an update.
1188           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1189           written polling loops from denying visibility of updates to memory.
1190
1191 config ARM_ERRATA_364296
1192         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1193         depends on CPU_V6
1194         help
1195           This options enables the workaround for the 364296 ARM1136
1196           r0p2 erratum (possible cache data corruption with
1197           hit-under-miss enabled). It sets the undocumented bit 31 in
1198           the auxiliary control register and the FI bit in the control
1199           register, thus disabling hit-under-miss without putting the
1200           processor into full low interrupt latency mode. ARM11MPCore
1201           is not affected.
1202
1203 config ARM_ERRATA_764369
1204         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1205         depends on CPU_V7 && SMP
1206         help
1207           This option enables the workaround for erratum 764369
1208           affecting Cortex-A9 MPCore with two or more processors (all
1209           current revisions). Under certain timing circumstances, a data
1210           cache line maintenance operation by MVA targeting an Inner
1211           Shareable memory region may fail to proceed up to either the
1212           Point of Coherency or to the Point of Unification of the
1213           system. This workaround adds a DSB instruction before the
1214           relevant cache maintenance functions and sets a specific bit
1215           in the diagnostic control register of the SCU.
1216
1217 config ARM_ERRATA_775420
1218        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1219        depends on CPU_V7
1220        help
1221          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1222          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1223          operation aborts with MMU exception, it might cause the processor
1224          to deadlock. This workaround puts DSB before executing ISB if
1225          an abort may occur on cache maintenance.
1226
1227 config ARM_ERRATA_798181
1228         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1229         depends on CPU_V7 && SMP
1230         help
1231           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1232           adequately shooting down all use of the old entries. This
1233           option enables the Linux kernel workaround for this erratum
1234           which sends an IPI to the CPUs that are running the same ASID
1235           as the one being invalidated.
1236
1237 config ARM_ERRATA_773022
1238         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1239         depends on CPU_V7
1240         help
1241           This option enables the workaround for the 773022 Cortex-A15
1242           (up to r0p4) erratum. In certain rare sequences of code, the
1243           loop buffer may deliver incorrect instructions. This
1244           workaround disables the loop buffer to avoid the erratum.
1245
1246 endmenu
1247
1248 source "arch/arm/common/Kconfig"
1249
1250 menu "Bus support"
1251
1252 config ISA
1253         bool
1254         help
1255           Find out whether you have ISA slots on your motherboard.  ISA is the
1256           name of a bus system, i.e. the way the CPU talks to the other stuff
1257           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1258           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1259           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1260
1261 # Select ISA DMA controller support
1262 config ISA_DMA
1263         bool
1264         select ISA_DMA_API
1265
1266 # Select ISA DMA interface
1267 config ISA_DMA_API
1268         bool
1269
1270 config PCI
1271         bool "PCI support" if MIGHT_HAVE_PCI
1272         help
1273           Find out whether you have a PCI motherboard. PCI is the name of a
1274           bus system, i.e. the way the CPU talks to the other stuff inside
1275           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1276           VESA. If you have PCI, say Y, otherwise N.
1277
1278 config PCI_DOMAINS
1279         bool
1280         depends on PCI
1281
1282 config PCI_DOMAINS_GENERIC
1283         def_bool PCI_DOMAINS
1284
1285 config PCI_NANOENGINE
1286         bool "BSE nanoEngine PCI support"
1287         depends on SA1100_NANOENGINE
1288         help
1289           Enable PCI on the BSE nanoEngine board.
1290
1291 config PCI_SYSCALL
1292         def_bool PCI
1293
1294 config PCI_HOST_ITE8152
1295         bool
1296         depends on PCI && MACH_ARMCORE
1297         default y
1298         select DMABOUNCE
1299
1300 source "drivers/pci/Kconfig"
1301 source "drivers/pci/pcie/Kconfig"
1302
1303 source "drivers/pcmcia/Kconfig"
1304
1305 endmenu
1306
1307 menu "Kernel Features"
1308
1309 config HAVE_SMP
1310         bool
1311         help
1312           This option should be selected by machines which have an SMP-
1313           capable CPU.
1314
1315           The only effect of this option is to make the SMP-related
1316           options available to the user for configuration.
1317
1318 config SMP
1319         bool "Symmetric Multi-Processing"
1320         depends on CPU_V6K || CPU_V7
1321         depends on GENERIC_CLOCKEVENTS
1322         depends on HAVE_SMP
1323         depends on MMU || ARM_MPU
1324         help
1325           This enables support for systems with more than one CPU. If you have
1326           a system with only one CPU, say N. If you have a system with more
1327           than one CPU, say Y.
1328
1329           If you say N here, the kernel will run on uni- and multiprocessor
1330           machines, but will use only one CPU of a multiprocessor machine. If
1331           you say Y here, the kernel will run on many, but not all,
1332           uniprocessor machines. On a uniprocessor machine, the kernel
1333           will run faster if you say N here.
1334
1335           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1336           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1337           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1338
1339           If you don't know what to do here, say N.
1340
1341 config SMP_ON_UP
1342         bool "Allow booting SMP kernel on uniprocessor systems"
1343         depends on SMP && !XIP_KERNEL && MMU
1344         default y
1345         help
1346           SMP kernels contain instructions which fail on non-SMP processors.
1347           Enabling this option allows the kernel to modify itself to make
1348           these instructions safe.  Disabling it allows about 1K of space
1349           savings.
1350
1351           If you don't know what to do here, say Y.
1352
1353 config ARM_CPU_TOPOLOGY
1354         bool "Support cpu topology definition"
1355         depends on SMP && CPU_V7
1356         default y
1357         help
1358           Support ARM cpu topology definition. The MPIDR register defines
1359           affinity between processors which is then used to describe the cpu
1360           topology of an ARM System.
1361
1362 config SCHED_MC
1363         bool "Multi-core scheduler support"
1364         depends on ARM_CPU_TOPOLOGY
1365         help
1366           Multi-core scheduler support improves the CPU scheduler's decision
1367           making when dealing with multi-core CPU chips at a cost of slightly
1368           increased overhead in some places. If unsure say N here.
1369
1370 config SCHED_SMT
1371         bool "SMT scheduler support"
1372         depends on ARM_CPU_TOPOLOGY
1373         help
1374           Improves the CPU scheduler's decision making when dealing with
1375           MultiThreading at a cost of slightly increased overhead in some
1376           places. If unsure say N here.
1377
1378 config HAVE_ARM_SCU
1379         bool
1380         help
1381           This option enables support for the ARM system coherency unit
1382
1383 config HAVE_ARM_ARCH_TIMER
1384         bool "Architected timer support"
1385         depends on CPU_V7
1386         select ARM_ARCH_TIMER
1387         select GENERIC_CLOCKEVENTS
1388         help
1389           This option enables support for the ARM architected timer
1390
1391 config HAVE_ARM_TWD
1392         bool
1393         depends on SMP
1394         select CLKSRC_OF if OF
1395         help
1396           This options enables support for the ARM timer and watchdog unit
1397
1398 config MCPM
1399         bool "Multi-Cluster Power Management"
1400         depends on CPU_V7 && SMP
1401         help
1402           This option provides the common power management infrastructure
1403           for (multi-)cluster based systems, such as big.LITTLE based
1404           systems.
1405
1406 config MCPM_QUAD_CLUSTER
1407         bool
1408         depends on MCPM
1409         help
1410           To avoid wasting resources unnecessarily, MCPM only supports up
1411           to 2 clusters by default.
1412           Platforms with 3 or 4 clusters that use MCPM must select this
1413           option to allow the additional clusters to be managed.
1414
1415 config BIG_LITTLE
1416         bool "big.LITTLE support (Experimental)"
1417         depends on CPU_V7 && SMP
1418         select MCPM
1419         help
1420           This option enables support selections for the big.LITTLE
1421           system architecture.
1422
1423 config BL_SWITCHER
1424         bool "big.LITTLE switcher support"
1425         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1426         select ARM_CPU_SUSPEND
1427         select CPU_PM
1428         help
1429           The big.LITTLE "switcher" provides the core functionality to
1430           transparently handle transition between a cluster of A15's
1431           and a cluster of A7's in a big.LITTLE system.
1432
1433 config BL_SWITCHER_DUMMY_IF
1434         tristate "Simple big.LITTLE switcher user interface"
1435         depends on BL_SWITCHER && DEBUG_KERNEL
1436         help
1437           This is a simple and dummy char dev interface to control
1438           the big.LITTLE switcher core code.  It is meant for
1439           debugging purposes only.
1440
1441 choice
1442         prompt "Memory split"
1443         depends on MMU
1444         default VMSPLIT_3G
1445         help
1446           Select the desired split between kernel and user memory.
1447
1448           If you are not absolutely sure what you are doing, leave this
1449           option alone!
1450
1451         config VMSPLIT_3G
1452                 bool "3G/1G user/kernel split"
1453         config VMSPLIT_2G
1454                 bool "2G/2G user/kernel split"
1455         config VMSPLIT_1G
1456                 bool "1G/3G user/kernel split"
1457 endchoice
1458
1459 config PAGE_OFFSET
1460         hex
1461         default PHYS_OFFSET if !MMU
1462         default 0x40000000 if VMSPLIT_1G
1463         default 0x80000000 if VMSPLIT_2G
1464         default 0xC0000000
1465
1466 config NR_CPUS
1467         int "Maximum number of CPUs (2-32)"
1468         range 2 32
1469         depends on SMP
1470         default "4"
1471
1472 config HOTPLUG_CPU
1473         bool "Support for hot-pluggable CPUs"
1474         depends on SMP
1475         help
1476           Say Y here to experiment with turning CPUs off and on.  CPUs
1477           can be controlled through /sys/devices/system/cpu.
1478
1479 config ARM_PSCI
1480         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1481         depends on CPU_V7
1482         help
1483           Say Y here if you want Linux to communicate with system firmware
1484           implementing the PSCI specification for CPU-centric power
1485           management operations described in ARM document number ARM DEN
1486           0022A ("Power State Coordination Interface System Software on
1487           ARM processors").
1488
1489 # The GPIO number here must be sorted by descending number. In case of
1490 # a multiplatform kernel, we just want the highest value required by the
1491 # selected platforms.
1492 config ARCH_NR_GPIO
1493         int
1494         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1495         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1496                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1497         default 416 if ARCH_SUNXI
1498         default 392 if ARCH_U8500
1499         default 352 if ARCH_VT8500
1500         default 288 if ARCH_ROCKCHIP
1501         default 264 if MACH_H4700
1502         default 0
1503         help
1504           Maximum number of GPIOs in the system.
1505
1506           If unsure, leave the default value.
1507
1508 source kernel/Kconfig.preempt
1509
1510 config HZ_FIXED
1511         int
1512         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1513                 ARCH_S5PV210 || ARCH_EXYNOS4
1514         default AT91_TIMER_HZ if ARCH_AT91
1515         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1516         default 0
1517
1518 choice
1519         depends on HZ_FIXED = 0
1520         prompt "Timer frequency"
1521
1522 config HZ_100
1523         bool "100 Hz"
1524
1525 config HZ_200
1526         bool "200 Hz"
1527
1528 config HZ_250
1529         bool "250 Hz"
1530
1531 config HZ_300
1532         bool "300 Hz"
1533
1534 config HZ_500
1535         bool "500 Hz"
1536
1537 config HZ_1000
1538         bool "1000 Hz"
1539
1540 endchoice
1541
1542 config HZ
1543         int
1544         default HZ_FIXED if HZ_FIXED != 0
1545         default 100 if HZ_100
1546         default 200 if HZ_200
1547         default 250 if HZ_250
1548         default 300 if HZ_300
1549         default 500 if HZ_500
1550         default 1000
1551
1552 config SCHED_HRTICK
1553         def_bool HIGH_RES_TIMERS
1554
1555 config THUMB2_KERNEL
1556         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1557         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1558         default y if CPU_THUMBONLY
1559         select AEABI
1560         select ARM_ASM_UNIFIED
1561         select ARM_UNWIND
1562         help
1563           By enabling this option, the kernel will be compiled in
1564           Thumb-2 mode. A compiler/assembler that understand the unified
1565           ARM-Thumb syntax is needed.
1566
1567           If unsure, say N.
1568
1569 config THUMB2_AVOID_R_ARM_THM_JUMP11
1570         bool "Work around buggy Thumb-2 short branch relocations in gas"
1571         depends on THUMB2_KERNEL && MODULES
1572         default y
1573         help
1574           Various binutils versions can resolve Thumb-2 branches to
1575           locally-defined, preemptible global symbols as short-range "b.n"
1576           branch instructions.
1577
1578           This is a problem, because there's no guarantee the final
1579           destination of the symbol, or any candidate locations for a
1580           trampoline, are within range of the branch.  For this reason, the
1581           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1582           relocation in modules at all, and it makes little sense to add
1583           support.
1584
1585           The symptom is that the kernel fails with an "unsupported
1586           relocation" error when loading some modules.
1587
1588           Until fixed tools are available, passing
1589           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1590           code which hits this problem, at the cost of a bit of extra runtime
1591           stack usage in some cases.
1592
1593           The problem is described in more detail at:
1594               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1595
1596           Only Thumb-2 kernels are affected.
1597
1598           Unless you are sure your tools don't have this problem, say Y.
1599
1600 config ARM_ASM_UNIFIED
1601         bool
1602
1603 config AEABI
1604         bool "Use the ARM EABI to compile the kernel"
1605         help
1606           This option allows for the kernel to be compiled using the latest
1607           ARM ABI (aka EABI).  This is only useful if you are using a user
1608           space environment that is also compiled with EABI.
1609
1610           Since there are major incompatibilities between the legacy ABI and
1611           EABI, especially with regard to structure member alignment, this
1612           option also changes the kernel syscall calling convention to
1613           disambiguate both ABIs and allow for backward compatibility support
1614           (selected with CONFIG_OABI_COMPAT).
1615
1616           To use this you need GCC version 4.0.0 or later.
1617
1618 config OABI_COMPAT
1619         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1620         depends on AEABI && !THUMB2_KERNEL
1621         help
1622           This option preserves the old syscall interface along with the
1623           new (ARM EABI) one. It also provides a compatibility layer to
1624           intercept syscalls that have structure arguments which layout
1625           in memory differs between the legacy ABI and the new ARM EABI
1626           (only for non "thumb" binaries). This option adds a tiny
1627           overhead to all syscalls and produces a slightly larger kernel.
1628
1629           The seccomp filter system will not be available when this is
1630           selected, since there is no way yet to sensibly distinguish
1631           between calling conventions during filtering.
1632
1633           If you know you'll be using only pure EABI user space then you
1634           can say N here. If this option is not selected and you attempt
1635           to execute a legacy ABI binary then the result will be
1636           UNPREDICTABLE (in fact it can be predicted that it won't work
1637           at all). If in doubt say N.
1638
1639 config ARCH_HAS_HOLES_MEMORYMODEL
1640         bool
1641
1642 config ARCH_SPARSEMEM_ENABLE
1643         bool
1644
1645 config ARCH_SPARSEMEM_DEFAULT
1646         def_bool ARCH_SPARSEMEM_ENABLE
1647
1648 config ARCH_SELECT_MEMORY_MODEL
1649         def_bool ARCH_SPARSEMEM_ENABLE
1650
1651 config HAVE_ARCH_PFN_VALID
1652         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1653
1654 config HAVE_GENERIC_RCU_GUP
1655         def_bool y
1656         depends on ARM_LPAE
1657
1658 config HIGHMEM
1659         bool "High Memory Support"
1660         depends on MMU
1661         help
1662           The address space of ARM processors is only 4 Gigabytes large
1663           and it has to accommodate user address space, kernel address
1664           space as well as some memory mapped IO. That means that, if you
1665           have a large amount of physical memory and/or IO, not all of the
1666           memory can be "permanently mapped" by the kernel. The physical
1667           memory that is not permanently mapped is called "high memory".
1668
1669           Depending on the selected kernel/user memory split, minimum
1670           vmalloc space and actual amount of RAM, you may not need this
1671           option which should result in a slightly faster kernel.
1672
1673           If unsure, say n.
1674
1675 config HIGHPTE
1676         bool "Allocate 2nd-level pagetables from highmem"
1677         depends on HIGHMEM
1678
1679 config HW_PERF_EVENTS
1680         bool "Enable hardware performance counter support for perf events"
1681         depends on PERF_EVENTS
1682         default y
1683         help
1684           Enable hardware performance counter support for perf events. If
1685           disabled, perf events will use software events only.
1686
1687 config SYS_SUPPORTS_HUGETLBFS
1688        def_bool y
1689        depends on ARM_LPAE
1690
1691 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1692        def_bool y
1693        depends on ARM_LPAE
1694
1695 config ARCH_WANT_GENERAL_HUGETLB
1696         def_bool y
1697
1698 source "mm/Kconfig"
1699
1700 config FORCE_MAX_ZONEORDER
1701         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1702         range 11 64 if ARCH_SHMOBILE_LEGACY
1703         default "12" if SOC_AM33XX
1704         default "9" if SA1111 || ARCH_EFM32
1705         default "11"
1706         help
1707           The kernel memory allocator divides physically contiguous memory
1708           blocks into "zones", where each zone is a power of two number of
1709           pages.  This option selects the largest power of two that the kernel
1710           keeps in the memory allocator.  If you need to allocate very large
1711           blocks of physically contiguous memory, then you may need to
1712           increase this value.
1713
1714           This config option is actually maximum order plus one. For example,
1715           a value of 11 means that the largest free memory block is 2^10 pages.
1716
1717 config ALIGNMENT_TRAP
1718         bool
1719         depends on CPU_CP15_MMU
1720         default y if !ARCH_EBSA110
1721         select HAVE_PROC_CPU if PROC_FS
1722         help
1723           ARM processors cannot fetch/store information which is not
1724           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1725           address divisible by 4. On 32-bit ARM processors, these non-aligned
1726           fetch/store instructions will be emulated in software if you say
1727           here, which has a severe performance impact. This is necessary for
1728           correct operation of some network protocols. With an IP-only
1729           configuration it is safe to say N, otherwise say Y.
1730
1731 config UACCESS_WITH_MEMCPY
1732         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1733         depends on MMU
1734         default y if CPU_FEROCEON
1735         help
1736           Implement faster copy_to_user and clear_user methods for CPU
1737           cores where a 8-word STM instruction give significantly higher
1738           memory write throughput than a sequence of individual 32bit stores.
1739
1740           A possible side effect is a slight increase in scheduling latency
1741           between threads sharing the same address space if they invoke
1742           such copy operations with large buffers.
1743
1744           However, if the CPU data cache is using a write-allocate mode,
1745           this option is unlikely to provide any performance gain.
1746
1747 config SECCOMP
1748         bool
1749         prompt "Enable seccomp to safely compute untrusted bytecode"
1750         ---help---
1751           This kernel feature is useful for number crunching applications
1752           that may need to compute untrusted bytecode during their
1753           execution. By using pipes or other transports made available to
1754           the process as file descriptors supporting the read/write
1755           syscalls, it's possible to isolate those applications in
1756           their own address space using seccomp. Once seccomp is
1757           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1758           and the task is only allowed to execute a few safe syscalls
1759           defined by each seccomp mode.
1760
1761 config SWIOTLB
1762         def_bool y
1763
1764 config IOMMU_HELPER
1765         def_bool SWIOTLB
1766
1767 config XEN_DOM0
1768         def_bool y
1769         depends on XEN
1770
1771 config XEN
1772         bool "Xen guest support on ARM"
1773         depends on ARM && AEABI && OF
1774         depends on CPU_V7 && !CPU_V6
1775         depends on !GENERIC_ATOMIC64
1776         depends on MMU
1777         select ARCH_DMA_ADDR_T_64BIT
1778         select ARM_PSCI
1779         select SWIOTLB_XEN
1780         help
1781           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1782
1783 endmenu
1784
1785 menu "Boot options"
1786
1787 config USE_OF
1788         bool "Flattened Device Tree support"
1789         select IRQ_DOMAIN
1790         select OF
1791         select OF_EARLY_FLATTREE
1792         select OF_RESERVED_MEM
1793         help
1794           Include support for flattened device tree machine descriptions.
1795
1796 config ATAGS
1797         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1798         default y
1799         help
1800           This is the traditional way of passing data to the kernel at boot
1801           time. If you are solely relying on the flattened device tree (or
1802           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1803           to remove ATAGS support from your kernel binary.  If unsure,
1804           leave this to y.
1805
1806 config DEPRECATED_PARAM_STRUCT
1807         bool "Provide old way to pass kernel parameters"
1808         depends on ATAGS
1809         help
1810           This was deprecated in 2001 and announced to live on for 5 years.
1811           Some old boot loaders still use this way.
1812
1813 # Compressed boot loader in ROM.  Yes, we really want to ask about
1814 # TEXT and BSS so we preserve their values in the config files.
1815 config ZBOOT_ROM_TEXT
1816         hex "Compressed ROM boot loader base address"
1817         default "0"
1818         help
1819           The physical address at which the ROM-able zImage is to be
1820           placed in the target.  Platforms which normally make use of
1821           ROM-able zImage formats normally set this to a suitable
1822           value in their defconfig file.
1823
1824           If ZBOOT_ROM is not enabled, this has no effect.
1825
1826 config ZBOOT_ROM_BSS
1827         hex "Compressed ROM boot loader BSS address"
1828         default "0"
1829         help
1830           The base address of an area of read/write memory in the target
1831           for the ROM-able zImage which must be available while the
1832           decompressor is running. It must be large enough to hold the
1833           entire decompressed kernel plus an additional 128 KiB.
1834           Platforms which normally make use of ROM-able zImage formats
1835           normally set this to a suitable value in their defconfig file.
1836
1837           If ZBOOT_ROM is not enabled, this has no effect.
1838
1839 config ZBOOT_ROM
1840         bool "Compressed boot loader in ROM/flash"
1841         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1842         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1843         help
1844           Say Y here if you intend to execute your compressed kernel image
1845           (zImage) directly from ROM or flash.  If unsure, say N.
1846
1847 choice
1848         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1849         depends on ZBOOT_ROM && ARCH_SH7372
1850         default ZBOOT_ROM_NONE
1851         help
1852           Include experimental SD/MMC loading code in the ROM-able zImage.
1853           With this enabled it is possible to write the ROM-able zImage
1854           kernel image to an MMC or SD card and boot the kernel straight
1855           from the reset vector. At reset the processor Mask ROM will load
1856           the first part of the ROM-able zImage which in turn loads the
1857           rest the kernel image to RAM.
1858
1859 config ZBOOT_ROM_NONE
1860         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1861         help
1862           Do not load image from SD or MMC
1863
1864 config ZBOOT_ROM_MMCIF
1865         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1866         help
1867           Load image from MMCIF hardware block.
1868
1869 config ZBOOT_ROM_SH_MOBILE_SDHI
1870         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1871         help
1872           Load image from SDHI hardware block
1873
1874 endchoice
1875
1876 config ARM_APPENDED_DTB
1877         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1878         depends on OF
1879         help
1880           With this option, the boot code will look for a device tree binary
1881           (DTB) appended to zImage
1882           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1883
1884           This is meant as a backward compatibility convenience for those
1885           systems with a bootloader that can't be upgraded to accommodate
1886           the documented boot protocol using a device tree.
1887
1888           Beware that there is very little in terms of protection against
1889           this option being confused by leftover garbage in memory that might
1890           look like a DTB header after a reboot if no actual DTB is appended
1891           to zImage.  Do not leave this option active in a production kernel
1892           if you don't intend to always append a DTB.  Proper passing of the
1893           location into r2 of a bootloader provided DTB is always preferable
1894           to this option.
1895
1896 config ARM_ATAG_DTB_COMPAT
1897         bool "Supplement the appended DTB with traditional ATAG information"
1898         depends on ARM_APPENDED_DTB
1899         help
1900           Some old bootloaders can't be updated to a DTB capable one, yet
1901           they provide ATAGs with memory configuration, the ramdisk address,
1902           the kernel cmdline string, etc.  Such information is dynamically
1903           provided by the bootloader and can't always be stored in a static
1904           DTB.  To allow a device tree enabled kernel to be used with such
1905           bootloaders, this option allows zImage to extract the information
1906           from the ATAG list and store it at run time into the appended DTB.
1907
1908 choice
1909         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1910         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1911
1912 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1913         bool "Use bootloader kernel arguments if available"
1914         help
1915           Uses the command-line options passed by the boot loader instead of
1916           the device tree bootargs property. If the boot loader doesn't provide
1917           any, the device tree bootargs property will be used.
1918
1919 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1920         bool "Extend with bootloader kernel arguments"
1921         help
1922           The command-line arguments provided by the boot loader will be
1923           appended to the the device tree bootargs property.
1924
1925 endchoice
1926
1927 config CMDLINE
1928         string "Default kernel command string"
1929         default ""
1930         help
1931           On some architectures (EBSA110 and CATS), there is currently no way
1932           for the boot loader to pass arguments to the kernel. For these
1933           architectures, you should supply some command-line options at build
1934           time by entering them here. As a minimum, you should specify the
1935           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1936
1937 choice
1938         prompt "Kernel command line type" if CMDLINE != ""
1939         default CMDLINE_FROM_BOOTLOADER
1940         depends on ATAGS
1941
1942 config CMDLINE_FROM_BOOTLOADER
1943         bool "Use bootloader kernel arguments if available"
1944         help
1945           Uses the command-line options passed by the boot loader. If
1946           the boot loader doesn't provide any, the default kernel command
1947           string provided in CMDLINE will be used.
1948
1949 config CMDLINE_EXTEND
1950         bool "Extend bootloader kernel arguments"
1951         help
1952           The command-line arguments provided by the boot loader will be
1953           appended to the default kernel command string.
1954
1955 config CMDLINE_FORCE
1956         bool "Always use the default kernel command string"
1957         help
1958           Always use the default kernel command string, even if the boot
1959           loader passes other arguments to the kernel.
1960           This is useful if you cannot or don't want to change the
1961           command-line options your boot loader passes to the kernel.
1962 endchoice
1963
1964 config XIP_KERNEL
1965         bool "Kernel Execute-In-Place from ROM"
1966         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1967         help
1968           Execute-In-Place allows the kernel to run from non-volatile storage
1969           directly addressable by the CPU, such as NOR flash. This saves RAM
1970           space since the text section of the kernel is not loaded from flash
1971           to RAM.  Read-write sections, such as the data section and stack,
1972           are still copied to RAM.  The XIP kernel is not compressed since
1973           it has to run directly from flash, so it will take more space to
1974           store it.  The flash address used to link the kernel object files,
1975           and for storing it, is configuration dependent. Therefore, if you
1976           say Y here, you must know the proper physical address where to
1977           store the kernel image depending on your own flash memory usage.
1978
1979           Also note that the make target becomes "make xipImage" rather than
1980           "make zImage" or "make Image".  The final kernel binary to put in
1981           ROM memory will be arch/arm/boot/xipImage.
1982
1983           If unsure, say N.
1984
1985 config XIP_PHYS_ADDR
1986         hex "XIP Kernel Physical Location"
1987         depends on XIP_KERNEL
1988         default "0x00080000"
1989         help
1990           This is the physical address in your flash memory the kernel will
1991           be linked for and stored to.  This address is dependent on your
1992           own flash usage.
1993
1994 config KEXEC
1995         bool "Kexec system call (EXPERIMENTAL)"
1996         depends on (!SMP || PM_SLEEP_SMP)
1997         help
1998           kexec is a system call that implements the ability to shutdown your
1999           current kernel, and to start another kernel.  It is like a reboot
2000           but it is independent of the system firmware.   And like a reboot
2001           you can start any kernel with it, not just Linux.
2002
2003           It is an ongoing process to be certain the hardware in a machine
2004           is properly shutdown, so do not be surprised if this code does not
2005           initially work for you.
2006
2007 config ATAGS_PROC
2008         bool "Export atags in procfs"
2009         depends on ATAGS && KEXEC
2010         default y
2011         help
2012           Should the atags used to boot the kernel be exported in an "atags"
2013           file in procfs. Useful with kexec.
2014
2015 config CRASH_DUMP
2016         bool "Build kdump crash kernel (EXPERIMENTAL)"
2017         help
2018           Generate crash dump after being started by kexec. This should
2019           be normally only set in special crash dump kernels which are
2020           loaded in the main kernel with kexec-tools into a specially
2021           reserved region and then later executed after a crash by
2022           kdump/kexec. The crash dump kernel must be compiled to a
2023           memory address not used by the main kernel
2024
2025           For more details see Documentation/kdump/kdump.txt
2026
2027 config AUTO_ZRELADDR
2028         bool "Auto calculation of the decompressed kernel image address"
2029         help
2030           ZRELADDR is the physical address where the decompressed kernel
2031           image will be placed. If AUTO_ZRELADDR is selected, the address
2032           will be determined at run-time by masking the current IP with
2033           0xf8000000. This assumes the zImage being placed in the first 128MB
2034           from start of memory.
2035
2036 endmenu
2037
2038 menu "CPU Power Management"
2039
2040 source "drivers/cpufreq/Kconfig"
2041
2042 source "drivers/cpuidle/Kconfig"
2043
2044 endmenu
2045
2046 menu "Floating point emulation"
2047
2048 comment "At least one emulation must be selected"
2049
2050 config FPE_NWFPE
2051         bool "NWFPE math emulation"
2052         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2053         ---help---
2054           Say Y to include the NWFPE floating point emulator in the kernel.
2055           This is necessary to run most binaries. Linux does not currently
2056           support floating point hardware so you need to say Y here even if
2057           your machine has an FPA or floating point co-processor podule.
2058
2059           You may say N here if you are going to load the Acorn FPEmulator
2060           early in the bootup.
2061
2062 config FPE_NWFPE_XP
2063         bool "Support extended precision"
2064         depends on FPE_NWFPE
2065         help
2066           Say Y to include 80-bit support in the kernel floating-point
2067           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2068           Note that gcc does not generate 80-bit operations by default,
2069           so in most cases this option only enlarges the size of the
2070           floating point emulator without any good reason.
2071
2072           You almost surely want to say N here.
2073
2074 config FPE_FASTFPE
2075         bool "FastFPE math emulation (EXPERIMENTAL)"
2076         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2077         ---help---
2078           Say Y here to include the FAST floating point emulator in the kernel.
2079           This is an experimental much faster emulator which now also has full
2080           precision for the mantissa.  It does not support any exceptions.
2081           It is very simple, and approximately 3-6 times faster than NWFPE.
2082
2083           It should be sufficient for most programs.  It may be not suitable
2084           for scientific calculations, but you have to check this for yourself.
2085           If you do not feel you need a faster FP emulation you should better
2086           choose NWFPE.
2087
2088 config VFP
2089         bool "VFP-format floating point maths"
2090         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2091         help
2092           Say Y to include VFP support code in the kernel. This is needed
2093           if your hardware includes a VFP unit.
2094
2095           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2096           release notes and additional status information.
2097
2098           Say N if your target does not have VFP hardware.
2099
2100 config VFPv3
2101         bool
2102         depends on VFP
2103         default y if CPU_V7
2104
2105 config NEON
2106         bool "Advanced SIMD (NEON) Extension support"
2107         depends on VFPv3 && CPU_V7
2108         help
2109           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2110           Extension.
2111
2112 config KERNEL_MODE_NEON
2113         bool "Support for NEON in kernel mode"
2114         depends on NEON && AEABI
2115         help
2116           Say Y to include support for NEON in kernel mode.
2117
2118 endmenu
2119
2120 menu "Userspace binary formats"
2121
2122 source "fs/Kconfig.binfmt"
2123
2124 endmenu
2125
2126 menu "Power management options"
2127
2128 source "kernel/power/Kconfig"
2129
2130 config ARCH_SUSPEND_POSSIBLE
2131         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2132                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2133         def_bool y
2134
2135 config ARM_CPU_SUSPEND
2136         def_bool PM_SLEEP
2137
2138 config ARCH_HIBERNATION_POSSIBLE
2139         bool
2140         depends on MMU
2141         default y if ARCH_SUSPEND_POSSIBLE
2142
2143 endmenu
2144
2145 source "net/Kconfig"
2146
2147 source "drivers/Kconfig"
2148
2149 source "drivers/firmware/Kconfig"
2150
2151 source "fs/Kconfig"
2152
2153 source "arch/arm/Kconfig.debug"
2154
2155 source "security/Kconfig"
2156
2157 source "crypto/Kconfig"
2158 if CRYPTO
2159 source "arch/arm/crypto/Kconfig"
2160 endif
2161
2162 source "lib/Kconfig"
2163
2164 source "arch/arm/kvm/Kconfig"