4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_IO_H
208 Select this when mach/io.h is required to provide special
209 definitions for this platform. The need for mach/io.h should
210 be avoided when possible.
212 config NEED_MACH_MEMORY_H
215 Select this when mach/memory.h is required to provide special
216 definitions for this platform. The need for mach/memory.h should
217 be avoided when possible.
220 hex "Physical address of main memory" if MMU
221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
222 default DRAM_BASE if !MMU
224 Please provide the physical address corresponding to the
225 location of main memory in your system.
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
238 bool "MMU-based Paged Memory Management Support"
241 Select if you want MMU-based virtualised addressing space
242 support by paged memory management. If unsure, say 'Y'.
245 # The "ARM system type" choice list is ordered alphabetically by option
246 # text. Please add new entries in the option alphabetic order.
249 prompt "ARM system type"
250 default ARCH_VERSATILE
253 bool "Altera SOCFPGA family"
254 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select DW_APB_TIMER_OF
263 select GENERIC_CLOCKEVENTS
264 select GPIO_PL061 if GPIOLIB
269 This enables support for Altera SOCFPGA Cyclone V platform
271 config ARCH_INTEGRATOR
272 bool "ARM Ltd. Integrator family"
274 select ARCH_HAS_CPUFREQ
276 select COMMON_CLK_VERSATILE
279 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_FPGA_IRQ
282 select NEED_MACH_MEMORY_H
284 select MULTI_IRQ_HANDLER
286 Support for ARM's Integrator platform.
289 bool "ARM Ltd. RealView family"
292 select COMMON_CLK_VERSATILE
294 select GENERIC_CLOCKEVENTS
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select PLAT_VERSATILE
297 select PLAT_VERSATILE_CLCD
298 select ARM_TIMER_SP804
299 select GPIO_PL061 if GPIOLIB
300 select NEED_MACH_MEMORY_H
302 This enables support for ARM Ltd RealView boards.
304 config ARCH_VERSATILE
305 bool "ARM Ltd. Versatile family"
309 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select PLAT_VERSATILE
314 select PLAT_VERSATILE_CLOCK
315 select PLAT_VERSATILE_CLCD
316 select PLAT_VERSATILE_FPGA_IRQ
317 select ARM_TIMER_SP804
319 This enables support for ARM Ltd Versatile board.
322 bool "ARM Ltd. Versatile Express family"
323 select ARCH_WANT_OPTIONAL_GPIOLIB
325 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
330 select HAVE_PATA_PLATFORM
333 select PLAT_VERSATILE
334 select PLAT_VERSATILE_CLCD
335 select REGULATOR_FIXED_VOLTAGE if REGULATOR
337 This enables support for the ARM Ltd Versatile Express boards.
341 select ARCH_REQUIRE_GPIOLIB
345 select NEED_MACH_IO_H if PCCARD
347 This enables support for systems based on Atmel
348 AT91RM9200 and AT91SAM9* processors.
351 bool "Broadcom BCM2835 family"
352 select ARCH_WANT_OPTIONAL_GPIOLIB
354 select ARM_ERRATA_411920
355 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
360 select MULTI_IRQ_HANDLER
364 This enables support for the Broadcom BCM2835 SoC. This SoC is
365 use in the Raspberry Pi, and Roku 2 devices.
368 bool "Broadcom BCMRING"
372 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select ARCH_WANT_OPTIONAL_GPIOLIB
377 Support for Broadcom's BCMRing platform.
380 bool "Calxeda Highbank-based"
381 select ARCH_WANT_OPTIONAL_GPIOLIB
384 select ARM_TIMER_SP804
389 select GENERIC_CLOCKEVENTS
395 Support for the Calxeda Highbank SoC based boards.
398 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
400 select ARCH_USES_GETTIMEOFFSET
401 select NEED_MACH_MEMORY_H
403 Support for Cirrus Logic 711x/721x/731x based boards.
406 bool "Cavium Networks CNS3XXX family"
408 select GENERIC_CLOCKEVENTS
410 select MIGHT_HAVE_CACHE_L2X0
411 select MIGHT_HAVE_PCI
412 select PCI_DOMAINS if PCI
414 Support for Cavium Networks CNS3XXX platform.
417 bool "Cortina Systems Gemini"
419 select ARCH_REQUIRE_GPIOLIB
420 select ARCH_USES_GETTIMEOFFSET
422 Support for the Cortina Systems Gemini family SoCs
427 select ARCH_REQUIRE_GPIOLIB
428 select GENERIC_CLOCKEVENTS
430 select GENERIC_IRQ_CHIP
431 select MIGHT_HAVE_CACHE_L2X0
436 Support for CSR SiRFprimaII/Marco/Polo platforms
443 select ARCH_USES_GETTIMEOFFSET
444 select NEED_MACH_IO_H
445 select NEED_MACH_MEMORY_H
447 This is an evaluation board for the StrongARM processor available
448 from Digital. It has limited hardware on-board, including an
449 Ethernet interface, two PCMCIA sockets, two serial ports and a
458 select ARCH_REQUIRE_GPIOLIB
459 select ARCH_HAS_HOLES_MEMORYMODEL
460 select ARCH_USES_GETTIMEOFFSET
461 select NEED_MACH_MEMORY_H
463 This enables support for the Cirrus EP93xx series of CPUs.
465 config ARCH_FOOTBRIDGE
469 select GENERIC_CLOCKEVENTS
471 select NEED_MACH_IO_H if !MMU
472 select NEED_MACH_MEMORY_H
474 Support for systems based on the DC21285 companion chip
475 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
478 bool "Freescale MXC/iMX-based"
479 select GENERIC_CLOCKEVENTS
480 select ARCH_REQUIRE_GPIOLIB
483 select GENERIC_IRQ_CHIP
484 select MULTI_IRQ_HANDLER
488 Support for Freescale MXC/iMX-based family of processors
491 bool "Freescale MXS-based"
492 select GENERIC_CLOCKEVENTS
493 select ARCH_REQUIRE_GPIOLIB
497 select HAVE_CLK_PREPARE
501 Support for Freescale MXS-based family of processors
504 bool "Hilscher NetX based"
508 select GENERIC_CLOCKEVENTS
510 This enables support for systems based on the Hilscher NetX Soc
513 bool "Hynix HMS720x-based"
516 select ARCH_USES_GETTIMEOFFSET
518 This enables support for systems based on the Hynix HMS720x
526 select ARCH_SUPPORTS_MSI
528 select NEED_MACH_MEMORY_H
529 select NEED_RET_TO_USER
531 Support for Intel's IOP13XX (XScale) family of processors.
537 select NEED_RET_TO_USER
540 select ARCH_REQUIRE_GPIOLIB
542 Support for Intel's 80219 and IOP32X (XScale) family of
549 select NEED_RET_TO_USER
552 select ARCH_REQUIRE_GPIOLIB
554 Support for Intel's IOP33X (XScale) family of processors.
559 select ARCH_HAS_DMA_SET_COHERENT_MASK
562 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
564 select MIGHT_HAVE_PCI
565 select NEED_MACH_IO_H
566 select DMABOUNCE if PCI
568 Support for Intel's IXP4XX (XScale) family of processors.
571 bool "Marvell SOCs with Device Tree support"
572 select GENERIC_CLOCKEVENTS
573 select MULTI_IRQ_HANDLER
576 select GENERIC_IRQ_CHIP
580 Support for the Marvell SoC Family with device tree support
586 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
590 Support for the Marvell Dove SoC 88AP510
593 bool "Marvell Kirkwood"
596 select ARCH_REQUIRE_GPIOLIB
597 select GENERIC_CLOCKEVENTS
600 Support for the following Marvell Kirkwood series SoCs:
601 88F6180, 88F6192 and 88F6281.
607 select ARCH_REQUIRE_GPIOLIB
610 select USB_ARCH_HAS_OHCI
612 select GENERIC_CLOCKEVENTS
616 Support for the NXP LPC32XX family of processors
619 bool "Marvell MV78xx0"
622 select ARCH_REQUIRE_GPIOLIB
623 select GENERIC_CLOCKEVENTS
626 Support for the following Marvell MV78xx0 series SoCs:
634 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
638 Support for the following Marvell Orion 5x series SoCs:
639 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
640 Orion-2 (5281), Orion-1-90 (6183).
643 bool "Marvell PXA168/910/MMP2"
645 select ARCH_REQUIRE_GPIOLIB
647 select GENERIC_CLOCKEVENTS
652 select GENERIC_ALLOCATOR
654 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
657 bool "Micrel/Kendin KS8695"
659 select ARCH_REQUIRE_GPIOLIB
660 select NEED_MACH_MEMORY_H
662 select GENERIC_CLOCKEVENTS
664 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
665 System-on-Chip devices.
668 bool "Nuvoton W90X900 CPU"
670 select ARCH_REQUIRE_GPIOLIB
673 select GENERIC_CLOCKEVENTS
675 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
676 At present, the w90x900 has been renamed nuc900, regarding
677 the ARM series product line, you can login the following
678 link address to know more.
680 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
681 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
687 select GENERIC_CLOCKEVENTS
691 select MIGHT_HAVE_CACHE_L2X0
692 select ARCH_HAS_CPUFREQ
696 This enables support for NVIDIA Tegra based systems (Tegra APX,
697 Tegra 6xx and Tegra 2 series).
699 config ARCH_PICOXCELL
700 bool "Picochip picoXcell"
701 select ARCH_REQUIRE_GPIOLIB
702 select ARM_PATCH_PHYS_VIRT
706 select DW_APB_TIMER_OF
707 select GENERIC_CLOCKEVENTS
714 This enables support for systems based on the Picochip picoXcell
715 family of Femtocell devices. The picoxcell support requires device tree
719 bool "PXA2xx/PXA3xx-based"
722 select ARCH_HAS_CPUFREQ
725 select ARCH_REQUIRE_GPIOLIB
726 select GENERIC_CLOCKEVENTS
731 select MULTI_IRQ_HANDLER
732 select ARM_CPU_SUSPEND if PM
735 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
740 select GENERIC_CLOCKEVENTS
741 select ARCH_REQUIRE_GPIOLIB
744 Support for Qualcomm MSM/QSD based systems. This runs on the
745 apps processor of the MSM/QSD and depends on a shared memory
746 interface to the modem processor which runs the baseband
747 stack and controls some vital subsystems
748 (clock and power control, etc).
751 bool "Renesas SH-Mobile / R-Mobile"
754 select HAVE_MACH_CLKDEV
756 select GENERIC_CLOCKEVENTS
757 select MIGHT_HAVE_CACHE_L2X0
760 select MULTI_IRQ_HANDLER
761 select PM_GENERIC_DOMAINS if PM
762 select NEED_MACH_MEMORY_H
764 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
770 select ARCH_MAY_HAVE_PC_FDC
771 select HAVE_PATA_PLATFORM
774 select ARCH_SPARSEMEM_ENABLE
775 select ARCH_USES_GETTIMEOFFSET
777 select NEED_MACH_IO_H
778 select NEED_MACH_MEMORY_H
780 On the Acorn Risc-PC, Linux can support the internal IDE disk and
781 CD-ROM interface, serial and parallel port, and the floppy drive.
788 select ARCH_SPARSEMEM_ENABLE
790 select ARCH_HAS_CPUFREQ
792 select GENERIC_CLOCKEVENTS
794 select ARCH_REQUIRE_GPIOLIB
796 select NEED_MACH_MEMORY_H
799 Support for StrongARM 11x0 based boards.
802 bool "Samsung S3C24XX SoCs"
804 select ARCH_HAS_CPUFREQ
807 select ARCH_USES_GETTIMEOFFSET
808 select HAVE_S3C2410_I2C if I2C
809 select HAVE_S3C_RTC if RTC_CLASS
810 select HAVE_S3C2410_WATCHDOG if WATCHDOG
811 select NEED_MACH_IO_H
813 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
814 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
815 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
816 Samsung SMDK2410 development board (and derivatives).
819 bool "Samsung S3C64XX"
827 select ARCH_USES_GETTIMEOFFSET
828 select ARCH_HAS_CPUFREQ
829 select ARCH_REQUIRE_GPIOLIB
830 select SAMSUNG_CLKSRC
831 select SAMSUNG_IRQ_VIC_TIMER
832 select S3C_GPIO_TRACK
834 select USB_ARCH_HAS_OHCI
835 select SAMSUNG_GPIOLIB_4BIT
836 select HAVE_S3C2410_I2C if I2C
837 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 Samsung S3C64XX series based systems
842 bool "Samsung S5P6440 S5P6450"
848 select HAVE_S3C2410_WATCHDOG if WATCHDOG
849 select GENERIC_CLOCKEVENTS
850 select HAVE_S3C2410_I2C if I2C
851 select HAVE_S3C_RTC if RTC_CLASS
853 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
857 bool "Samsung S5PC100"
862 select ARCH_USES_GETTIMEOFFSET
863 select HAVE_S3C2410_I2C if I2C
864 select HAVE_S3C_RTC if RTC_CLASS
865 select HAVE_S3C2410_WATCHDOG if WATCHDOG
867 Samsung S5PC100 series based systems
870 bool "Samsung S5PV210/S5PC110"
872 select ARCH_SPARSEMEM_ENABLE
873 select ARCH_HAS_HOLES_MEMORYMODEL
878 select ARCH_HAS_CPUFREQ
879 select GENERIC_CLOCKEVENTS
880 select HAVE_S3C2410_I2C if I2C
881 select HAVE_S3C_RTC if RTC_CLASS
882 select HAVE_S3C2410_WATCHDOG if WATCHDOG
883 select NEED_MACH_MEMORY_H
885 Samsung S5PV210/S5PC110 series based systems
888 bool "SAMSUNG EXYNOS"
890 select ARCH_SPARSEMEM_ENABLE
891 select ARCH_HAS_HOLES_MEMORYMODEL
895 select ARCH_HAS_CPUFREQ
896 select GENERIC_CLOCKEVENTS
897 select HAVE_S3C_RTC if RTC_CLASS
898 select HAVE_S3C2410_I2C if I2C
899 select HAVE_S3C2410_WATCHDOG if WATCHDOG
900 select NEED_MACH_MEMORY_H
902 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
911 select ARCH_USES_GETTIMEOFFSET
912 select NEED_MACH_MEMORY_H
914 Support for the StrongARM based Digital DNARD machine, also known
915 as "Shark" (<http://www.shark-linux.de/shark.html>).
918 bool "ST-Ericsson U300 Series"
924 select ARM_PATCH_PHYS_VIRT
926 select GENERIC_CLOCKEVENTS
930 select ARCH_REQUIRE_GPIOLIB
933 Support for ST-Ericsson U300 series mobile platforms.
936 bool "ST-Ericsson U8500 Series"
940 select GENERIC_CLOCKEVENTS
942 select ARCH_REQUIRE_GPIOLIB
943 select ARCH_HAS_CPUFREQ
945 select MIGHT_HAVE_CACHE_L2X0
947 Support for ST-Ericsson's Ux500 architecture
950 bool "STMicroelectronics Nomadik"
955 select GENERIC_CLOCKEVENTS
957 select MIGHT_HAVE_CACHE_L2X0
958 select ARCH_REQUIRE_GPIOLIB
960 Support for the Nomadik platform by ST-Ericsson
964 select GENERIC_CLOCKEVENTS
965 select ARCH_REQUIRE_GPIOLIB
969 select GENERIC_ALLOCATOR
970 select GENERIC_IRQ_CHIP
971 select ARCH_HAS_HOLES_MEMORYMODEL
973 Support for TI's DaVinci platform.
979 select ARCH_REQUIRE_GPIOLIB
980 select ARCH_HAS_CPUFREQ
982 select GENERIC_CLOCKEVENTS
983 select ARCH_HAS_HOLES_MEMORYMODEL
985 Support for TI's OMAP platform (OMAP1/2/3/4).
990 select ARCH_REQUIRE_GPIOLIB
994 select GENERIC_CLOCKEVENTS
997 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1000 bool "VIA/WonderMedia 85xx"
1003 select ARCH_HAS_CPUFREQ
1004 select GENERIC_CLOCKEVENTS
1005 select ARCH_REQUIRE_GPIOLIB
1007 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1010 bool "Xilinx Zynq ARM Cortex A9 Platform"
1012 select GENERIC_CLOCKEVENTS
1013 select CLKDEV_LOOKUP
1017 select MIGHT_HAVE_CACHE_L2X0
1020 Support for Xilinx Zynq ARM Cortex A9 Platform
1024 # This is sorted alphabetically by mach-* pathname. However, plat-*
1025 # Kconfigs may be included either alphabetically (according to the
1026 # plat- suffix) or along side the corresponding mach-* source.
1028 source "arch/arm/mach-mvebu/Kconfig"
1030 source "arch/arm/mach-at91/Kconfig"
1032 source "arch/arm/mach-bcmring/Kconfig"
1034 source "arch/arm/mach-clps711x/Kconfig"
1036 source "arch/arm/mach-cns3xxx/Kconfig"
1038 source "arch/arm/mach-davinci/Kconfig"
1040 source "arch/arm/mach-dove/Kconfig"
1042 source "arch/arm/mach-ep93xx/Kconfig"
1044 source "arch/arm/mach-footbridge/Kconfig"
1046 source "arch/arm/mach-gemini/Kconfig"
1048 source "arch/arm/mach-h720x/Kconfig"
1050 source "arch/arm/mach-integrator/Kconfig"
1052 source "arch/arm/mach-iop32x/Kconfig"
1054 source "arch/arm/mach-iop33x/Kconfig"
1056 source "arch/arm/mach-iop13xx/Kconfig"
1058 source "arch/arm/mach-ixp4xx/Kconfig"
1060 source "arch/arm/mach-kirkwood/Kconfig"
1062 source "arch/arm/mach-ks8695/Kconfig"
1064 source "arch/arm/mach-msm/Kconfig"
1066 source "arch/arm/mach-mv78xx0/Kconfig"
1068 source "arch/arm/plat-mxc/Kconfig"
1070 source "arch/arm/mach-mxs/Kconfig"
1072 source "arch/arm/mach-netx/Kconfig"
1074 source "arch/arm/mach-nomadik/Kconfig"
1075 source "arch/arm/plat-nomadik/Kconfig"
1077 source "arch/arm/plat-omap/Kconfig"
1079 source "arch/arm/mach-omap1/Kconfig"
1081 source "arch/arm/mach-omap2/Kconfig"
1083 source "arch/arm/mach-orion5x/Kconfig"
1085 source "arch/arm/mach-pxa/Kconfig"
1086 source "arch/arm/plat-pxa/Kconfig"
1088 source "arch/arm/mach-mmp/Kconfig"
1090 source "arch/arm/mach-realview/Kconfig"
1092 source "arch/arm/mach-sa1100/Kconfig"
1094 source "arch/arm/plat-samsung/Kconfig"
1095 source "arch/arm/plat-s3c24xx/Kconfig"
1097 source "arch/arm/plat-spear/Kconfig"
1099 source "arch/arm/mach-s3c24xx/Kconfig"
1101 source "arch/arm/mach-s3c2412/Kconfig"
1102 source "arch/arm/mach-s3c2440/Kconfig"
1106 source "arch/arm/mach-s3c64xx/Kconfig"
1109 source "arch/arm/mach-s5p64x0/Kconfig"
1111 source "arch/arm/mach-s5pc100/Kconfig"
1113 source "arch/arm/mach-s5pv210/Kconfig"
1115 source "arch/arm/mach-exynos/Kconfig"
1117 source "arch/arm/mach-shmobile/Kconfig"
1119 source "arch/arm/mach-prima2/Kconfig"
1121 source "arch/arm/mach-tegra/Kconfig"
1123 source "arch/arm/mach-u300/Kconfig"
1125 source "arch/arm/mach-ux500/Kconfig"
1127 source "arch/arm/mach-versatile/Kconfig"
1129 source "arch/arm/mach-vexpress/Kconfig"
1130 source "arch/arm/plat-versatile/Kconfig"
1132 source "arch/arm/mach-vt8500/Kconfig"
1134 source "arch/arm/mach-w90x900/Kconfig"
1136 # Definitions to make life easier
1142 select GENERIC_CLOCKEVENTS
1147 select GENERIC_IRQ_CHIP
1154 config PLAT_VERSATILE
1157 config ARM_TIMER_SP804
1160 select HAVE_SCHED_CLOCK
1162 source arch/arm/mm/Kconfig
1166 default 16 if ARCH_EP93XX
1170 bool "Enable iWMMXt support"
1171 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1172 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1174 Enable support for iWMMXt context switching at run time if
1175 running on a CPU that supports it.
1179 depends on CPU_XSCALE
1182 config MULTI_IRQ_HANDLER
1185 Allow each machine to specify it's own IRQ handler at run time.
1188 source "arch/arm/Kconfig-nommu"
1191 config ARM_ERRATA_326103
1192 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1195 Executing a SWP instruction to read-only memory does not set bit 11
1196 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1197 treat the access as a read, preventing a COW from occurring and
1198 causing the faulting task to livelock.
1200 config ARM_ERRATA_411920
1201 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1202 depends on CPU_V6 || CPU_V6K
1204 Invalidation of the Instruction Cache operation can
1205 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1206 It does not affect the MPCore. This option enables the ARM Ltd.
1207 recommended workaround.
1209 config ARM_ERRATA_430973
1210 bool "ARM errata: Stale prediction on replaced interworking branch"
1213 This option enables the workaround for the 430973 Cortex-A8
1214 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1215 interworking branch is replaced with another code sequence at the
1216 same virtual address, whether due to self-modifying code or virtual
1217 to physical address re-mapping, Cortex-A8 does not recover from the
1218 stale interworking branch prediction. This results in Cortex-A8
1219 executing the new code sequence in the incorrect ARM or Thumb state.
1220 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1221 and also flushes the branch target cache at every context switch.
1222 Note that setting specific bits in the ACTLR register may not be
1223 available in non-secure mode.
1225 config ARM_ERRATA_458693
1226 bool "ARM errata: Processor deadlock when a false hazard is created"
1229 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1230 erratum. For very specific sequences of memory operations, it is
1231 possible for a hazard condition intended for a cache line to instead
1232 be incorrectly associated with a different cache line. This false
1233 hazard might then cause a processor deadlock. The workaround enables
1234 the L1 caching of the NEON accesses and disables the PLD instruction
1235 in the ACTLR register. Note that setting specific bits in the ACTLR
1236 register may not be available in non-secure mode.
1238 config ARM_ERRATA_460075
1239 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1242 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1243 erratum. Any asynchronous access to the L2 cache may encounter a
1244 situation in which recent store transactions to the L2 cache are lost
1245 and overwritten with stale memory contents from external memory. The
1246 workaround disables the write-allocate mode for the L2 cache via the
1247 ACTLR register. Note that setting specific bits in the ACTLR register
1248 may not be available in non-secure mode.
1250 config ARM_ERRATA_742230
1251 bool "ARM errata: DMB operation may be faulty"
1252 depends on CPU_V7 && SMP
1254 This option enables the workaround for the 742230 Cortex-A9
1255 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1256 between two write operations may not ensure the correct visibility
1257 ordering of the two writes. This workaround sets a specific bit in
1258 the diagnostic register of the Cortex-A9 which causes the DMB
1259 instruction to behave as a DSB, ensuring the correct behaviour of
1262 config ARM_ERRATA_742231
1263 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1264 depends on CPU_V7 && SMP
1266 This option enables the workaround for the 742231 Cortex-A9
1267 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1268 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1269 accessing some data located in the same cache line, may get corrupted
1270 data due to bad handling of the address hazard when the line gets
1271 replaced from one of the CPUs at the same time as another CPU is
1272 accessing it. This workaround sets specific bits in the diagnostic
1273 register of the Cortex-A9 which reduces the linefill issuing
1274 capabilities of the processor.
1276 config PL310_ERRATA_588369
1277 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1278 depends on CACHE_L2X0
1280 The PL310 L2 cache controller implements three types of Clean &
1281 Invalidate maintenance operations: by Physical Address
1282 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1283 They are architecturally defined to behave as the execution of a
1284 clean operation followed immediately by an invalidate operation,
1285 both performing to the same memory location. This functionality
1286 is not correctly implemented in PL310 as clean lines are not
1287 invalidated as a result of these operations.
1289 config ARM_ERRATA_720789
1290 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1293 This option enables the workaround for the 720789 Cortex-A9 (prior to
1294 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1295 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1296 As a consequence of this erratum, some TLB entries which should be
1297 invalidated are not, resulting in an incoherency in the system page
1298 tables. The workaround changes the TLB flushing routines to invalidate
1299 entries regardless of the ASID.
1301 config PL310_ERRATA_727915
1302 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1303 depends on CACHE_L2X0
1305 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1306 operation (offset 0x7FC). This operation runs in background so that
1307 PL310 can handle normal accesses while it is in progress. Under very
1308 rare circumstances, due to this erratum, write data can be lost when
1309 PL310 treats a cacheable write transaction during a Clean &
1310 Invalidate by Way operation.
1312 config ARM_ERRATA_743622
1313 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1316 This option enables the workaround for the 743622 Cortex-A9
1317 (r2p*) erratum. Under very rare conditions, a faulty
1318 optimisation in the Cortex-A9 Store Buffer may lead to data
1319 corruption. This workaround sets a specific bit in the diagnostic
1320 register of the Cortex-A9 which disables the Store Buffer
1321 optimisation, preventing the defect from occurring. This has no
1322 visible impact on the overall performance or power consumption of the
1325 config ARM_ERRATA_751472
1326 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1329 This option enables the workaround for the 751472 Cortex-A9 (prior
1330 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1331 completion of a following broadcasted operation if the second
1332 operation is received by a CPU before the ICIALLUIS has completed,
1333 potentially leading to corrupted entries in the cache or TLB.
1335 config PL310_ERRATA_753970
1336 bool "PL310 errata: cache sync operation may be faulty"
1337 depends on CACHE_PL310
1339 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1341 Under some condition the effect of cache sync operation on
1342 the store buffer still remains when the operation completes.
1343 This means that the store buffer is always asked to drain and
1344 this prevents it from merging any further writes. The workaround
1345 is to replace the normal offset of cache sync operation (0x730)
1346 by another offset targeting an unmapped PL310 register 0x740.
1347 This has the same effect as the cache sync operation: store buffer
1348 drain and waiting for all buffers empty.
1350 config ARM_ERRATA_754322
1351 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1354 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1355 r3p*) erratum. A speculative memory access may cause a page table walk
1356 which starts prior to an ASID switch but completes afterwards. This
1357 can populate the micro-TLB with a stale entry which may be hit with
1358 the new ASID. This workaround places two dsb instructions in the mm
1359 switching code so that no page table walks can cross the ASID switch.
1361 config ARM_ERRATA_754327
1362 bool "ARM errata: no automatic Store Buffer drain"
1363 depends on CPU_V7 && SMP
1365 This option enables the workaround for the 754327 Cortex-A9 (prior to
1366 r2p0) erratum. The Store Buffer does not have any automatic draining
1367 mechanism and therefore a livelock may occur if an external agent
1368 continuously polls a memory location waiting to observe an update.
1369 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1370 written polling loops from denying visibility of updates to memory.
1372 config ARM_ERRATA_364296
1373 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1374 depends on CPU_V6 && !SMP
1376 This options enables the workaround for the 364296 ARM1136
1377 r0p2 erratum (possible cache data corruption with
1378 hit-under-miss enabled). It sets the undocumented bit 31 in
1379 the auxiliary control register and the FI bit in the control
1380 register, thus disabling hit-under-miss without putting the
1381 processor into full low interrupt latency mode. ARM11MPCore
1384 config ARM_ERRATA_764369
1385 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1386 depends on CPU_V7 && SMP
1388 This option enables the workaround for erratum 764369
1389 affecting Cortex-A9 MPCore with two or more processors (all
1390 current revisions). Under certain timing circumstances, a data
1391 cache line maintenance operation by MVA targeting an Inner
1392 Shareable memory region may fail to proceed up to either the
1393 Point of Coherency or to the Point of Unification of the
1394 system. This workaround adds a DSB instruction before the
1395 relevant cache maintenance functions and sets a specific bit
1396 in the diagnostic control register of the SCU.
1398 config PL310_ERRATA_769419
1399 bool "PL310 errata: no automatic Store Buffer drain"
1400 depends on CACHE_L2X0
1402 On revisions of the PL310 prior to r3p2, the Store Buffer does
1403 not automatically drain. This can cause normal, non-cacheable
1404 writes to be retained when the memory system is idle, leading
1405 to suboptimal I/O performance for drivers using coherent DMA.
1406 This option adds a write barrier to the cpu_idle loop so that,
1407 on systems with an outer cache, the store buffer is drained
1412 source "arch/arm/common/Kconfig"
1422 Find out whether you have ISA slots on your motherboard. ISA is the
1423 name of a bus system, i.e. the way the CPU talks to the other stuff
1424 inside your box. Other bus systems are PCI, EISA, MicroChannel
1425 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1426 newer boards don't support it. If you have ISA, say Y, otherwise N.
1428 # Select ISA DMA controller support
1433 # Select ISA DMA interface
1438 bool "PCI support" if MIGHT_HAVE_PCI
1440 Find out whether you have a PCI motherboard. PCI is the name of a
1441 bus system, i.e. the way the CPU talks to the other stuff inside
1442 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1443 VESA. If you have PCI, say Y, otherwise N.
1449 config PCI_NANOENGINE
1450 bool "BSE nanoEngine PCI support"
1451 depends on SA1100_NANOENGINE
1453 Enable PCI on the BSE nanoEngine board.
1458 # Select the host bridge type
1459 config PCI_HOST_VIA82C505
1461 depends on PCI && ARCH_SHARK
1464 config PCI_HOST_ITE8152
1466 depends on PCI && MACH_ARMCORE
1470 source "drivers/pci/Kconfig"
1472 source "drivers/pcmcia/Kconfig"
1476 menu "Kernel Features"
1481 This option should be selected by machines which have an SMP-
1484 The only effect of this option is to make the SMP-related
1485 options available to the user for configuration.
1488 bool "Symmetric Multi-Processing"
1489 depends on CPU_V6K || CPU_V7
1490 depends on GENERIC_CLOCKEVENTS
1493 select USE_GENERIC_SMP_HELPERS
1494 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1496 This enables support for systems with more than one CPU. If you have
1497 a system with only one CPU, like most personal computers, say N. If
1498 you have a system with more than one CPU, say Y.
1500 If you say N here, the kernel will run on single and multiprocessor
1501 machines, but will use only one CPU of a multiprocessor machine. If
1502 you say Y here, the kernel will run on many, but not all, single
1503 processor machines. On a single processor machine, the kernel will
1504 run faster if you say N here.
1506 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1507 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1508 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1510 If you don't know what to do here, say N.
1513 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1514 depends on EXPERIMENTAL
1515 depends on SMP && !XIP_KERNEL
1518 SMP kernels contain instructions which fail on non-SMP processors.
1519 Enabling this option allows the kernel to modify itself to make
1520 these instructions safe. Disabling it allows about 1K of space
1523 If you don't know what to do here, say Y.
1525 config ARM_CPU_TOPOLOGY
1526 bool "Support cpu topology definition"
1527 depends on SMP && CPU_V7
1530 Support ARM cpu topology definition. The MPIDR register defines
1531 affinity between processors which is then used to describe the cpu
1532 topology of an ARM System.
1535 bool "Multi-core scheduler support"
1536 depends on ARM_CPU_TOPOLOGY
1538 Multi-core scheduler support improves the CPU scheduler's decision
1539 making when dealing with multi-core CPU chips at a cost of slightly
1540 increased overhead in some places. If unsure say N here.
1543 bool "SMT scheduler support"
1544 depends on ARM_CPU_TOPOLOGY
1546 Improves the CPU scheduler's decision making when dealing with
1547 MultiThreading at a cost of slightly increased overhead in some
1548 places. If unsure say N here.
1553 This option enables support for the ARM system coherency unit
1555 config ARM_ARCH_TIMER
1556 bool "Architected timer support"
1559 This option enables support for the ARM architected timer
1565 This options enables support for the ARM timer and watchdog unit
1568 prompt "Memory split"
1571 Select the desired split between kernel and user memory.
1573 If you are not absolutely sure what you are doing, leave this
1577 bool "3G/1G user/kernel split"
1579 bool "2G/2G user/kernel split"
1581 bool "1G/3G user/kernel split"
1586 default 0x40000000 if VMSPLIT_1G
1587 default 0x80000000 if VMSPLIT_2G
1591 int "Maximum number of CPUs (2-32)"
1597 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1598 depends on SMP && HOTPLUG && EXPERIMENTAL
1600 Say Y here to experiment with turning CPUs off and on. CPUs
1601 can be controlled through /sys/devices/system/cpu.
1604 bool "Use local timer interrupts"
1607 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1609 Enable support for local timers on SMP platforms, rather then the
1610 legacy IPI broadcast method. Local timers allows the system
1611 accounting to be spread across the timer interval, preventing a
1612 "thundering herd" at every timer tick.
1616 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1617 default 355 if ARCH_U8500
1618 default 264 if MACH_H4700
1619 default 512 if SOC_OMAP5
1622 Maximum number of GPIOs in the system.
1624 If unsure, leave the default value.
1626 source kernel/Kconfig.preempt
1630 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1631 ARCH_S5PV210 || ARCH_EXYNOS4
1632 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1633 default AT91_TIMER_HZ if ARCH_AT91
1634 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1637 config THUMB2_KERNEL
1638 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1639 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1641 select ARM_ASM_UNIFIED
1644 By enabling this option, the kernel will be compiled in
1645 Thumb-2 mode. A compiler/assembler that understand the unified
1646 ARM-Thumb syntax is needed.
1650 config THUMB2_AVOID_R_ARM_THM_JUMP11
1651 bool "Work around buggy Thumb-2 short branch relocations in gas"
1652 depends on THUMB2_KERNEL && MODULES
1655 Various binutils versions can resolve Thumb-2 branches to
1656 locally-defined, preemptible global symbols as short-range "b.n"
1657 branch instructions.
1659 This is a problem, because there's no guarantee the final
1660 destination of the symbol, or any candidate locations for a
1661 trampoline, are within range of the branch. For this reason, the
1662 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1663 relocation in modules at all, and it makes little sense to add
1666 The symptom is that the kernel fails with an "unsupported
1667 relocation" error when loading some modules.
1669 Until fixed tools are available, passing
1670 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1671 code which hits this problem, at the cost of a bit of extra runtime
1672 stack usage in some cases.
1674 The problem is described in more detail at:
1675 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1677 Only Thumb-2 kernels are affected.
1679 Unless you are sure your tools don't have this problem, say Y.
1681 config ARM_ASM_UNIFIED
1685 bool "Use the ARM EABI to compile the kernel"
1687 This option allows for the kernel to be compiled using the latest
1688 ARM ABI (aka EABI). This is only useful if you are using a user
1689 space environment that is also compiled with EABI.
1691 Since there are major incompatibilities between the legacy ABI and
1692 EABI, especially with regard to structure member alignment, this
1693 option also changes the kernel syscall calling convention to
1694 disambiguate both ABIs and allow for backward compatibility support
1695 (selected with CONFIG_OABI_COMPAT).
1697 To use this you need GCC version 4.0.0 or later.
1700 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1701 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1704 This option preserves the old syscall interface along with the
1705 new (ARM EABI) one. It also provides a compatibility layer to
1706 intercept syscalls that have structure arguments which layout
1707 in memory differs between the legacy ABI and the new ARM EABI
1708 (only for non "thumb" binaries). This option adds a tiny
1709 overhead to all syscalls and produces a slightly larger kernel.
1710 If you know you'll be using only pure EABI user space then you
1711 can say N here. If this option is not selected and you attempt
1712 to execute a legacy ABI binary then the result will be
1713 UNPREDICTABLE (in fact it can be predicted that it won't work
1714 at all). If in doubt say Y.
1716 config ARCH_HAS_HOLES_MEMORYMODEL
1719 config ARCH_SPARSEMEM_ENABLE
1722 config ARCH_SPARSEMEM_DEFAULT
1723 def_bool ARCH_SPARSEMEM_ENABLE
1725 config ARCH_SELECT_MEMORY_MODEL
1726 def_bool ARCH_SPARSEMEM_ENABLE
1728 config HAVE_ARCH_PFN_VALID
1729 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1732 bool "High Memory Support"
1735 The address space of ARM processors is only 4 Gigabytes large
1736 and it has to accommodate user address space, kernel address
1737 space as well as some memory mapped IO. That means that, if you
1738 have a large amount of physical memory and/or IO, not all of the
1739 memory can be "permanently mapped" by the kernel. The physical
1740 memory that is not permanently mapped is called "high memory".
1742 Depending on the selected kernel/user memory split, minimum
1743 vmalloc space and actual amount of RAM, you may not need this
1744 option which should result in a slightly faster kernel.
1749 bool "Allocate 2nd-level pagetables from highmem"
1752 config HW_PERF_EVENTS
1753 bool "Enable hardware performance counter support for perf events"
1754 depends on PERF_EVENTS
1757 Enable hardware performance counter support for perf events. If
1758 disabled, perf events will use software events only.
1762 config FORCE_MAX_ZONEORDER
1763 int "Maximum zone order" if ARCH_SHMOBILE
1764 range 11 64 if ARCH_SHMOBILE
1765 default "9" if SA1111
1768 The kernel memory allocator divides physically contiguous memory
1769 blocks into "zones", where each zone is a power of two number of
1770 pages. This option selects the largest power of two that the kernel
1771 keeps in the memory allocator. If you need to allocate very large
1772 blocks of physically contiguous memory, then you may need to
1773 increase this value.
1775 This config option is actually maximum order plus one. For example,
1776 a value of 11 means that the largest free memory block is 2^10 pages.
1779 bool "Timer and CPU usage LEDs"
1780 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1781 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1782 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1783 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1784 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1785 ARCH_AT91 || ARCH_DAVINCI || \
1786 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1788 If you say Y here, the LEDs on your machine will be used
1789 to provide useful information about your current system status.
1791 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1792 be able to select which LEDs are active using the options below. If
1793 you are compiling a kernel for the EBSA-110 or the LART however, the
1794 red LED will simply flash regularly to indicate that the system is
1795 still functional. It is safe to say Y here if you have a CATS
1796 system, but the driver will do nothing.
1799 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1800 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1801 || MACH_OMAP_PERSEUS2
1803 depends on !GENERIC_CLOCKEVENTS
1804 default y if ARCH_EBSA110
1806 If you say Y here, one of the system LEDs (the green one on the
1807 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1808 will flash regularly to indicate that the system is still
1809 operational. This is mainly useful to kernel hackers who are
1810 debugging unstable kernels.
1812 The LART uses the same LED for both Timer LED and CPU usage LED
1813 functions. You may choose to use both, but the Timer LED function
1814 will overrule the CPU usage LED.
1817 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1819 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1820 || MACH_OMAP_PERSEUS2
1823 If you say Y here, the red LED will be used to give a good real
1824 time indication of CPU usage, by lighting whenever the idle task
1825 is not currently executing.
1827 The LART uses the same LED for both Timer LED and CPU usage LED
1828 functions. You may choose to use both, but the Timer LED function
1829 will overrule the CPU usage LED.
1831 config ALIGNMENT_TRAP
1833 depends on CPU_CP15_MMU
1834 default y if !ARCH_EBSA110
1835 select HAVE_PROC_CPU if PROC_FS
1837 ARM processors cannot fetch/store information which is not
1838 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1839 address divisible by 4. On 32-bit ARM processors, these non-aligned
1840 fetch/store instructions will be emulated in software if you say
1841 here, which has a severe performance impact. This is necessary for
1842 correct operation of some network protocols. With an IP-only
1843 configuration it is safe to say N, otherwise say Y.
1845 config UACCESS_WITH_MEMCPY
1846 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1847 depends on MMU && EXPERIMENTAL
1848 default y if CPU_FEROCEON
1850 Implement faster copy_to_user and clear_user methods for CPU
1851 cores where a 8-word STM instruction give significantly higher
1852 memory write throughput than a sequence of individual 32bit stores.
1854 A possible side effect is a slight increase in scheduling latency
1855 between threads sharing the same address space if they invoke
1856 such copy operations with large buffers.
1858 However, if the CPU data cache is using a write-allocate mode,
1859 this option is unlikely to provide any performance gain.
1863 prompt "Enable seccomp to safely compute untrusted bytecode"
1865 This kernel feature is useful for number crunching applications
1866 that may need to compute untrusted bytecode during their
1867 execution. By using pipes or other transports made available to
1868 the process as file descriptors supporting the read/write
1869 syscalls, it's possible to isolate those applications in
1870 their own address space using seccomp. Once seccomp is
1871 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1872 and the task is only allowed to execute a few safe syscalls
1873 defined by each seccomp mode.
1875 config CC_STACKPROTECTOR
1876 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1877 depends on EXPERIMENTAL
1879 This option turns on the -fstack-protector GCC feature. This
1880 feature puts, at the beginning of functions, a canary value on
1881 the stack just before the return address, and validates
1882 the value just before actually returning. Stack based buffer
1883 overflows (that need to overwrite this return address) now also
1884 overwrite the canary, which gets detected and the attack is then
1885 neutralized via a kernel panic.
1886 This feature requires gcc version 4.2 or above.
1888 config DEPRECATED_PARAM_STRUCT
1889 bool "Provide old way to pass kernel parameters"
1891 This was deprecated in 2001 and announced to live on for 5 years.
1892 Some old boot loaders still use this way.
1899 bool "Flattened Device Tree support"
1901 select OF_EARLY_FLATTREE
1904 Include support for flattened device tree machine descriptions.
1906 # Compressed boot loader in ROM. Yes, we really want to ask about
1907 # TEXT and BSS so we preserve their values in the config files.
1908 config ZBOOT_ROM_TEXT
1909 hex "Compressed ROM boot loader base address"
1912 The physical address at which the ROM-able zImage is to be
1913 placed in the target. Platforms which normally make use of
1914 ROM-able zImage formats normally set this to a suitable
1915 value in their defconfig file.
1917 If ZBOOT_ROM is not enabled, this has no effect.
1919 config ZBOOT_ROM_BSS
1920 hex "Compressed ROM boot loader BSS address"
1923 The base address of an area of read/write memory in the target
1924 for the ROM-able zImage which must be available while the
1925 decompressor is running. It must be large enough to hold the
1926 entire decompressed kernel plus an additional 128 KiB.
1927 Platforms which normally make use of ROM-able zImage formats
1928 normally set this to a suitable value in their defconfig file.
1930 If ZBOOT_ROM is not enabled, this has no effect.
1933 bool "Compressed boot loader in ROM/flash"
1934 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1936 Say Y here if you intend to execute your compressed kernel image
1937 (zImage) directly from ROM or flash. If unsure, say N.
1940 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1941 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1942 default ZBOOT_ROM_NONE
1944 Include experimental SD/MMC loading code in the ROM-able zImage.
1945 With this enabled it is possible to write the ROM-able zImage
1946 kernel image to an MMC or SD card and boot the kernel straight
1947 from the reset vector. At reset the processor Mask ROM will load
1948 the first part of the ROM-able zImage which in turn loads the
1949 rest the kernel image to RAM.
1951 config ZBOOT_ROM_NONE
1952 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1954 Do not load image from SD or MMC
1956 config ZBOOT_ROM_MMCIF
1957 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1959 Load image from MMCIF hardware block.
1961 config ZBOOT_ROM_SH_MOBILE_SDHI
1962 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1964 Load image from SDHI hardware block
1968 config ARM_APPENDED_DTB
1969 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1970 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1972 With this option, the boot code will look for a device tree binary
1973 (DTB) appended to zImage
1974 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1976 This is meant as a backward compatibility convenience for those
1977 systems with a bootloader that can't be upgraded to accommodate
1978 the documented boot protocol using a device tree.
1980 Beware that there is very little in terms of protection against
1981 this option being confused by leftover garbage in memory that might
1982 look like a DTB header after a reboot if no actual DTB is appended
1983 to zImage. Do not leave this option active in a production kernel
1984 if you don't intend to always append a DTB. Proper passing of the
1985 location into r2 of a bootloader provided DTB is always preferable
1988 config ARM_ATAG_DTB_COMPAT
1989 bool "Supplement the appended DTB with traditional ATAG information"
1990 depends on ARM_APPENDED_DTB
1992 Some old bootloaders can't be updated to a DTB capable one, yet
1993 they provide ATAGs with memory configuration, the ramdisk address,
1994 the kernel cmdline string, etc. Such information is dynamically
1995 provided by the bootloader and can't always be stored in a static
1996 DTB. To allow a device tree enabled kernel to be used with such
1997 bootloaders, this option allows zImage to extract the information
1998 from the ATAG list and store it at run time into the appended DTB.
2001 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2002 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2004 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2005 bool "Use bootloader kernel arguments if available"
2007 Uses the command-line options passed by the boot loader instead of
2008 the device tree bootargs property. If the boot loader doesn't provide
2009 any, the device tree bootargs property will be used.
2011 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2012 bool "Extend with bootloader kernel arguments"
2014 The command-line arguments provided by the boot loader will be
2015 appended to the the device tree bootargs property.
2020 string "Default kernel command string"
2023 On some architectures (EBSA110 and CATS), there is currently no way
2024 for the boot loader to pass arguments to the kernel. For these
2025 architectures, you should supply some command-line options at build
2026 time by entering them here. As a minimum, you should specify the
2027 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2030 prompt "Kernel command line type" if CMDLINE != ""
2031 default CMDLINE_FROM_BOOTLOADER
2033 config CMDLINE_FROM_BOOTLOADER
2034 bool "Use bootloader kernel arguments if available"
2036 Uses the command-line options passed by the boot loader. If
2037 the boot loader doesn't provide any, the default kernel command
2038 string provided in CMDLINE will be used.
2040 config CMDLINE_EXTEND
2041 bool "Extend bootloader kernel arguments"
2043 The command-line arguments provided by the boot loader will be
2044 appended to the default kernel command string.
2046 config CMDLINE_FORCE
2047 bool "Always use the default kernel command string"
2049 Always use the default kernel command string, even if the boot
2050 loader passes other arguments to the kernel.
2051 This is useful if you cannot or don't want to change the
2052 command-line options your boot loader passes to the kernel.
2056 bool "Kernel Execute-In-Place from ROM"
2057 depends on !ZBOOT_ROM && !ARM_LPAE
2059 Execute-In-Place allows the kernel to run from non-volatile storage
2060 directly addressable by the CPU, such as NOR flash. This saves RAM
2061 space since the text section of the kernel is not loaded from flash
2062 to RAM. Read-write sections, such as the data section and stack,
2063 are still copied to RAM. The XIP kernel is not compressed since
2064 it has to run directly from flash, so it will take more space to
2065 store it. The flash address used to link the kernel object files,
2066 and for storing it, is configuration dependent. Therefore, if you
2067 say Y here, you must know the proper physical address where to
2068 store the kernel image depending on your own flash memory usage.
2070 Also note that the make target becomes "make xipImage" rather than
2071 "make zImage" or "make Image". The final kernel binary to put in
2072 ROM memory will be arch/arm/boot/xipImage.
2076 config XIP_PHYS_ADDR
2077 hex "XIP Kernel Physical Location"
2078 depends on XIP_KERNEL
2079 default "0x00080000"
2081 This is the physical address in your flash memory the kernel will
2082 be linked for and stored to. This address is dependent on your
2086 bool "Kexec system call (EXPERIMENTAL)"
2087 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2089 kexec is a system call that implements the ability to shutdown your
2090 current kernel, and to start another kernel. It is like a reboot
2091 but it is independent of the system firmware. And like a reboot
2092 you can start any kernel with it, not just Linux.
2094 It is an ongoing process to be certain the hardware in a machine
2095 is properly shutdown, so do not be surprised if this code does not
2096 initially work for you. It may help to enable device hotplugging
2100 bool "Export atags in procfs"
2104 Should the atags used to boot the kernel be exported in an "atags"
2105 file in procfs. Useful with kexec.
2108 bool "Build kdump crash kernel (EXPERIMENTAL)"
2109 depends on EXPERIMENTAL
2111 Generate crash dump after being started by kexec. This should
2112 be normally only set in special crash dump kernels which are
2113 loaded in the main kernel with kexec-tools into a specially
2114 reserved region and then later executed after a crash by
2115 kdump/kexec. The crash dump kernel must be compiled to a
2116 memory address not used by the main kernel
2118 For more details see Documentation/kdump/kdump.txt
2120 config AUTO_ZRELADDR
2121 bool "Auto calculation of the decompressed kernel image address"
2122 depends on !ZBOOT_ROM && !ARCH_U300
2124 ZRELADDR is the physical address where the decompressed kernel
2125 image will be placed. If AUTO_ZRELADDR is selected, the address
2126 will be determined at run-time by masking the current IP with
2127 0xf8000000. This assumes the zImage being placed in the first 128MB
2128 from start of memory.
2132 menu "CPU Power Management"
2136 source "drivers/cpufreq/Kconfig"
2139 tristate "CPUfreq driver for i.MX CPUs"
2140 depends on ARCH_MXC && CPU_FREQ
2141 select CPU_FREQ_TABLE
2143 This enables the CPUfreq driver for i.MX CPUs.
2145 config CPU_FREQ_SA1100
2148 config CPU_FREQ_SA1110
2151 config CPU_FREQ_INTEGRATOR
2152 tristate "CPUfreq driver for ARM Integrator CPUs"
2153 depends on ARCH_INTEGRATOR && CPU_FREQ
2156 This enables the CPUfreq driver for ARM Integrator CPUs.
2158 For details, take a look at <file:Documentation/cpu-freq>.
2164 depends on CPU_FREQ && ARCH_PXA && PXA25x
2166 select CPU_FREQ_TABLE
2167 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2172 Internal configuration node for common cpufreq on Samsung SoC
2174 config CPU_FREQ_S3C24XX
2175 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2176 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2179 This enables the CPUfreq driver for the Samsung S3C24XX family
2182 For details, take a look at <file:Documentation/cpu-freq>.
2186 config CPU_FREQ_S3C24XX_PLL
2187 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2188 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2190 Compile in support for changing the PLL frequency from the
2191 S3C24XX series CPUfreq driver. The PLL takes time to settle
2192 after a frequency change, so by default it is not enabled.
2194 This also means that the PLL tables for the selected CPU(s) will
2195 be built which may increase the size of the kernel image.
2197 config CPU_FREQ_S3C24XX_DEBUG
2198 bool "Debug CPUfreq Samsung driver core"
2199 depends on CPU_FREQ_S3C24XX
2201 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2203 config CPU_FREQ_S3C24XX_IODEBUG
2204 bool "Debug CPUfreq Samsung driver IO timing"
2205 depends on CPU_FREQ_S3C24XX
2207 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2209 config CPU_FREQ_S3C24XX_DEBUGFS
2210 bool "Export debugfs for CPUFreq"
2211 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2213 Export status information via debugfs.
2217 source "drivers/cpuidle/Kconfig"
2221 menu "Floating point emulation"
2223 comment "At least one emulation must be selected"
2226 bool "NWFPE math emulation"
2227 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2229 Say Y to include the NWFPE floating point emulator in the kernel.
2230 This is necessary to run most binaries. Linux does not currently
2231 support floating point hardware so you need to say Y here even if
2232 your machine has an FPA or floating point co-processor podule.
2234 You may say N here if you are going to load the Acorn FPEmulator
2235 early in the bootup.
2238 bool "Support extended precision"
2239 depends on FPE_NWFPE
2241 Say Y to include 80-bit support in the kernel floating-point
2242 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2243 Note that gcc does not generate 80-bit operations by default,
2244 so in most cases this option only enlarges the size of the
2245 floating point emulator without any good reason.
2247 You almost surely want to say N here.
2250 bool "FastFPE math emulation (EXPERIMENTAL)"
2251 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2253 Say Y here to include the FAST floating point emulator in the kernel.
2254 This is an experimental much faster emulator which now also has full
2255 precision for the mantissa. It does not support any exceptions.
2256 It is very simple, and approximately 3-6 times faster than NWFPE.
2258 It should be sufficient for most programs. It may be not suitable
2259 for scientific calculations, but you have to check this for yourself.
2260 If you do not feel you need a faster FP emulation you should better
2264 bool "VFP-format floating point maths"
2265 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2267 Say Y to include VFP support code in the kernel. This is needed
2268 if your hardware includes a VFP unit.
2270 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2271 release notes and additional status information.
2273 Say N if your target does not have VFP hardware.
2281 bool "Advanced SIMD (NEON) Extension support"
2282 depends on VFPv3 && CPU_V7
2284 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2289 menu "Userspace binary formats"
2291 source "fs/Kconfig.binfmt"
2294 tristate "RISC OS personality"
2297 Say Y here to include the kernel code necessary if you want to run
2298 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2299 experimental; if this sounds frightening, say N and sleep in peace.
2300 You can also say M here to compile this support as a module (which
2301 will be called arthur).
2305 menu "Power management options"
2307 source "kernel/power/Kconfig"
2309 config ARCH_SUSPEND_POSSIBLE
2310 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2311 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2312 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2315 config ARM_CPU_SUSPEND
2320 source "net/Kconfig"
2322 source "drivers/Kconfig"
2326 source "arch/arm/Kconfig.debug"
2328 source "security/Kconfig"
2330 source "crypto/Kconfig"
2332 source "lib/Kconfig"