1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID
7 select ARCH_HAS_DEBUG_VIRTUAL
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_SET_MEMORY
11 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
12 select ARCH_HAS_STRICT_MODULE_RWX if MMU
13 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
14 select ARCH_HAVE_CUSTOM_GPIO_H
15 select ARCH_HAS_GCOV_PROFILE_ALL
16 select ARCH_MIGHT_HAVE_PC_PARPORT
17 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
18 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
19 select ARCH_SUPPORTS_ATOMIC_RMW
20 select ARCH_USE_BUILTIN_BSWAP
21 select ARCH_USE_CMPXCHG_LOCKREF
22 select ARCH_WANT_IPC_PARSE_VERSION
23 select BUILDTIME_EXTABLE_SORT if MMU
24 select CLONE_BACKWARDS
25 select CPU_PM if (SUSPEND || CPU_IDLE)
26 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
27 select DMA_NOOP_OPS if !MMU
29 select EDAC_ATOMIC_SCRUB
30 select GENERIC_ALLOCATOR
31 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
32 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
33 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
34 select GENERIC_CPU_AUTOPROBE
35 select GENERIC_EARLY_IOREMAP
36 select GENERIC_IDLE_POLL_SETUP
37 select GENERIC_IRQ_PROBE
38 select GENERIC_IRQ_SHOW
39 select GENERIC_IRQ_SHOW_LEVEL
40 select GENERIC_PCI_IOMAP
41 select GENERIC_SCHED_CLOCK
42 select GENERIC_SMP_IDLE_THREAD
43 select GENERIC_STRNCPY_FROM_USER
44 select GENERIC_STRNLEN_USER
45 select HANDLE_DOMAIN_IRQ
46 select HARDIRQS_SW_RESEND
47 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
48 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
49 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
50 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
51 select HAVE_ARCH_MMAP_RND_BITS if MMU
52 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
53 select HAVE_ARCH_TRACEHOOK
54 select HAVE_ARM_SMCCC if CPU_V7
55 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
56 select HAVE_CC_STACKPROTECTOR
57 select HAVE_CONTEXT_TRACKING
58 select HAVE_C_RECORDMCOUNT
59 select HAVE_DEBUG_KMEMLEAK
60 select HAVE_DMA_API_DEBUG
61 select HAVE_DMA_CONTIGUOUS if MMU
62 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
63 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
64 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
65 select HAVE_EXIT_THREAD
66 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
67 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
68 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
69 select HAVE_GCC_PLUGINS
70 select HAVE_GENERIC_DMA_COHERENT
71 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
72 select HAVE_IDE if PCI || ISA || PCMCIA
73 select HAVE_IRQ_TIME_ACCOUNTING
74 select HAVE_KERNEL_GZIP
75 select HAVE_KERNEL_LZ4
76 select HAVE_KERNEL_LZMA
77 select HAVE_KERNEL_LZO
79 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
80 select HAVE_KRETPROBES if (HAVE_KPROBES)
82 select HAVE_MOD_ARCH_SPECIFIC
84 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
85 select HAVE_OPTPROBES if !THUMB2_KERNEL
86 select HAVE_PERF_EVENTS
88 select HAVE_PERF_USER_STACK_DUMP
89 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
90 select HAVE_REGS_AND_STACK_ACCESS_API
91 select HAVE_SYSCALL_TRACEPOINTS
93 select HAVE_VIRT_CPU_ACCOUNTING_GEN
94 select IRQ_FORCED_THREADING
95 select MODULES_USE_ELF_REL
97 select OF_EARLY_FLATTREE if OF
98 select OF_RESERVED_MEM if OF
100 select OLD_SIGSUSPEND3
101 select PERF_USE_VMALLOC
103 select SYS_SUPPORTS_APM_EMULATION
104 # Above selects are sorted alphabetically; please add new ones
105 # according to that. Thanks.
107 The ARM series is a line of low-power-consumption RISC chip designs
108 licensed by ARM Ltd and targeted at embedded applications and
109 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
110 manufactured, but legacy ARM-based PC hardware remains popular in
111 Europe. There is an ARM Linux project with a web page at
112 <http://www.arm.linux.org.uk/>.
114 config ARM_HAS_SG_CHAIN
115 select ARCH_HAS_SG_CHAIN
118 config NEED_SG_DMA_LENGTH
121 config ARM_DMA_USE_IOMMU
123 select ARM_HAS_SG_CHAIN
124 select NEED_SG_DMA_LENGTH
128 config ARM_DMA_IOMMU_ALIGNMENT
129 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
133 DMA mapping framework by default aligns all buffers to the smallest
134 PAGE_SIZE order which is greater than or equal to the requested buffer
135 size. This works well for buffers up to a few hundreds kilobytes, but
136 for larger buffers it just a waste of address space. Drivers which has
137 relatively small addressing window (like 64Mib) might run out of
138 virtual space with just a few allocations.
140 With this parameter you can specify the maximum PAGE_SIZE order for
141 DMA IOMMU buffers. Larger buffers will be aligned only to this
142 specified order. The order is expressed as a power of two multiplied
147 config MIGHT_HAVE_PCI
150 config SYS_SUPPORTS_APM_EMULATION
155 select GENERIC_ALLOCATOR
166 The Extended Industry Standard Architecture (EISA) bus was
167 developed as an open alternative to the IBM MicroChannel bus.
169 The EISA bus provided some of the features of the IBM MicroChannel
170 bus while maintaining backward compatibility with cards made for
171 the older ISA bus. The EISA bus saw limited use between 1988 and
172 1995 when it was made obsolete by the PCI bus.
174 Say Y here if you are building a kernel for an EISA-based machine.
181 config STACKTRACE_SUPPORT
185 config LOCKDEP_SUPPORT
189 config TRACE_IRQFLAGS_SUPPORT
193 config RWSEM_XCHGADD_ALGORITHM
197 config ARCH_HAS_ILOG2_U32
200 config ARCH_HAS_ILOG2_U64
203 config ARCH_HAS_BANDGAP
206 config FIX_EARLYCON_MEM
209 config GENERIC_HWEIGHT
213 config GENERIC_CALIBRATE_DELAY
217 config ARCH_MAY_HAVE_PC_FDC
223 config NEED_DMA_MAP_STATE
226 config ARCH_SUPPORTS_UPROBES
229 config ARCH_HAS_DMA_SET_COHERENT_MASK
232 config GENERIC_ISA_DMA
238 config NEED_RET_TO_USER
244 config ARM_PATCH_PHYS_VIRT
245 bool "Patch physical to virtual translations at runtime" if EMBEDDED
247 depends on !XIP_KERNEL && MMU
249 Patch phys-to-virt and virt-to-phys translation functions at
250 boot and module load time according to the position of the
251 kernel in system memory.
253 This can only be used with non-XIP MMU kernels where the base
254 of physical memory is at a 16MB boundary.
256 Only disable this option if you know that you do not require
257 this feature (eg, building a kernel for a single machine) and
258 you need to shrink the kernel to the minimal size.
260 config NEED_MACH_IO_H
263 Select this when mach/io.h is required to provide special
264 definitions for this platform. The need for mach/io.h should
265 be avoided when possible.
267 config NEED_MACH_MEMORY_H
270 Select this when mach/memory.h is required to provide special
271 definitions for this platform. The need for mach/memory.h should
272 be avoided when possible.
275 hex "Physical address of main memory" if MMU
276 depends on !ARM_PATCH_PHYS_VIRT
277 default DRAM_BASE if !MMU
278 default 0x00000000 if ARCH_EBSA110 || \
284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
285 default 0x20000000 if ARCH_S5PV210
286 default 0xc0000000 if ARCH_SA1100
288 Please provide the physical address corresponding to the
289 location of main memory in your system.
295 config PGTABLE_LEVELS
297 default 3 if ARM_LPAE
300 source "init/Kconfig"
302 source "kernel/Kconfig.freezer"
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
311 support by paged memory management. If unsure, say 'Y'.
313 config ARCH_MMAP_RND_BITS_MIN
316 config ARCH_MMAP_RND_BITS_MAX
317 default 14 if PAGE_OFFSET=0x40000000
318 default 15 if PAGE_OFFSET=0x80000000
322 # The "ARM system type" choice list is ordered alphabetically by option
323 # text. Please add new entries in the option alphabetic order.
326 prompt "ARM system type"
327 default ARM_SINGLE_ARMV7M if !MMU
328 default ARCH_MULTIPLATFORM if MMU
330 config ARCH_MULTIPLATFORM
331 bool "Allow multiple platforms to be selected"
333 select ARM_HAS_SG_CHAIN
334 select ARM_PATCH_PHYS_VIRT
338 select GENERIC_CLOCKEVENTS
339 select MIGHT_HAVE_PCI
340 select MULTI_IRQ_HANDLER
341 select PCI_DOMAINS if PCI
345 config ARM_SINGLE_ARMV7M
346 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
353 select GENERIC_CLOCKEVENTS
360 select ARCH_USES_GETTIMEOFFSET
363 select NEED_MACH_IO_H
364 select NEED_MACH_MEMORY_H
367 This is an evaluation board for the StrongARM processor available
368 from Digital. It has limited hardware on-board, including an
369 Ethernet interface, two PCMCIA sockets, two serial ports and a
374 select ARCH_SPARSEMEM_ENABLE
376 imply ARM_PATCH_PHYS_VIRT
382 select GENERIC_CLOCKEVENTS
385 This enables support for the Cirrus EP93xx series of CPUs.
387 config ARCH_FOOTBRIDGE
391 select GENERIC_CLOCKEVENTS
393 select NEED_MACH_IO_H if !MMU
394 select NEED_MACH_MEMORY_H
396 Support for systems based on the DC21285 companion chip
397 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
400 bool "Hilscher NetX based"
404 select GENERIC_CLOCKEVENTS
406 This enables support for systems based on the Hilscher NetX Soc
412 select NEED_MACH_MEMORY_H
413 select NEED_RET_TO_USER
419 Support for Intel's IOP13XX (XScale) family of processors.
427 select NEED_RET_TO_USER
431 Support for Intel's 80219 and IOP32X (XScale) family of
440 select NEED_RET_TO_USER
444 Support for Intel's IOP33X (XScale) family of processors.
449 select ARCH_HAS_DMA_SET_COHERENT_MASK
450 select ARCH_SUPPORTS_BIG_ENDIAN
453 select DMABOUNCE if PCI
454 select GENERIC_CLOCKEVENTS
456 select MIGHT_HAVE_PCI
457 select NEED_MACH_IO_H
458 select USB_EHCI_BIG_ENDIAN_DESC
459 select USB_EHCI_BIG_ENDIAN_MMIO
461 Support for Intel's IXP4XX (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
468 select MIGHT_HAVE_PCI
469 select MULTI_IRQ_HANDLER
473 select PLAT_ORION_LEGACY
475 select PM_GENERIC_DOMAINS if PM
477 Support for the Marvell Dove SoC 88AP510
480 bool "Micrel/Kendin KS8695"
483 select GENERIC_CLOCKEVENTS
485 select NEED_MACH_MEMORY_H
487 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
488 System-on-Chip devices.
491 bool "Nuvoton W90X900 CPU"
495 select GENERIC_CLOCKEVENTS
498 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
499 At present, the w90x900 has been renamed nuc900, regarding
500 the ARM series product line, you can login the following
501 link address to know more.
503 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
504 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
510 select CLKSRC_LPC32XX
513 select GENERIC_CLOCKEVENTS
515 select MULTI_IRQ_HANDLER
519 Support for the NXP LPC32XX family of processors
522 bool "PXA2xx/PXA3xx-based"
525 select ARM_CPU_SUSPEND if PM
532 select CPU_XSCALE if !CPU_XSC3
533 select GENERIC_CLOCKEVENTS
538 select MULTI_IRQ_HANDLER
542 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
548 select ARCH_MAY_HAVE_PC_FDC
549 select ARCH_SPARSEMEM_ENABLE
550 select ARCH_USES_GETTIMEOFFSET
554 select HAVE_PATA_PLATFORM
556 select NEED_MACH_IO_H
557 select NEED_MACH_MEMORY_H
560 On the Acorn Risc-PC, Linux can support the internal IDE disk and
561 CD-ROM interface, serial and parallel port, and the floppy drive.
566 select ARCH_SPARSEMEM_ENABLE
570 select TIMER_OF if OF
573 select GENERIC_CLOCKEVENTS
578 select MULTI_IRQ_HANDLER
579 select NEED_MACH_MEMORY_H
582 Support for StrongARM 11x0 based boards.
585 bool "Samsung S3C24XX SoCs"
588 select CLKSRC_SAMSUNG_PWM
589 select GENERIC_CLOCKEVENTS
592 select HAVE_S3C2410_I2C if I2C
593 select HAVE_S3C2410_WATCHDOG if WATCHDOG
594 select HAVE_S3C_RTC if RTC_CLASS
595 select MULTI_IRQ_HANDLER
596 select NEED_MACH_IO_H
599 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
600 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
601 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
602 Samsung SMDK2410 development board (and derivatives).
606 select ARCH_HAS_HOLES_MEMORYMODEL
609 select GENERIC_ALLOCATOR
610 select GENERIC_CLOCKEVENTS
611 select GENERIC_IRQ_CHIP
617 Support for TI's DaVinci platform.
622 select ARCH_HAS_HOLES_MEMORYMODEL
626 select GENERIC_CLOCKEVENTS
627 select GENERIC_IRQ_CHIP
631 select MULTI_IRQ_HANDLER
632 select NEED_MACH_IO_H if PCCARD
633 select NEED_MACH_MEMORY_H
636 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
640 menu "Multiple platform selection"
641 depends on ARCH_MULTIPLATFORM
643 comment "CPU Core family selection"
646 bool "ARMv4 based platforms (FA526)"
647 depends on !ARCH_MULTI_V6_V7
648 select ARCH_MULTI_V4_V5
651 config ARCH_MULTI_V4T
652 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
653 depends on !ARCH_MULTI_V6_V7
654 select ARCH_MULTI_V4_V5
655 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
656 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
657 CPU_ARM925T || CPU_ARM940T)
660 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
661 depends on !ARCH_MULTI_V6_V7
662 select ARCH_MULTI_V4_V5
663 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
664 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
665 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
667 config ARCH_MULTI_V4_V5
671 bool "ARMv6 based platforms (ARM11)"
672 select ARCH_MULTI_V6_V7
676 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
678 select ARCH_MULTI_V6_V7
682 config ARCH_MULTI_V6_V7
684 select MIGHT_HAVE_CACHE_L2X0
686 config ARCH_MULTI_CPU_AUTO
687 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
693 bool "Dummy Virtual Machine"
694 depends on ARCH_MULTI_V7
697 select ARM_GIC_V2M if PCI
699 select ARM_GIC_V3_ITS if PCI
701 select HAVE_ARM_ARCH_TIMER
704 # This is sorted alphabetically by mach-* pathname. However, plat-*
705 # Kconfigs may be included either alphabetically (according to the
706 # plat- suffix) or along side the corresponding mach-* source.
708 source "arch/arm/mach-mvebu/Kconfig"
710 source "arch/arm/mach-actions/Kconfig"
712 source "arch/arm/mach-alpine/Kconfig"
714 source "arch/arm/mach-artpec/Kconfig"
716 source "arch/arm/mach-asm9260/Kconfig"
718 source "arch/arm/mach-at91/Kconfig"
720 source "arch/arm/mach-axxia/Kconfig"
722 source "arch/arm/mach-bcm/Kconfig"
724 source "arch/arm/mach-berlin/Kconfig"
726 source "arch/arm/mach-clps711x/Kconfig"
728 source "arch/arm/mach-cns3xxx/Kconfig"
730 source "arch/arm/mach-davinci/Kconfig"
732 source "arch/arm/mach-digicolor/Kconfig"
734 source "arch/arm/mach-dove/Kconfig"
736 source "arch/arm/mach-ep93xx/Kconfig"
738 source "arch/arm/mach-footbridge/Kconfig"
740 source "arch/arm/mach-gemini/Kconfig"
742 source "arch/arm/mach-highbank/Kconfig"
744 source "arch/arm/mach-hisi/Kconfig"
746 source "arch/arm/mach-integrator/Kconfig"
748 source "arch/arm/mach-iop32x/Kconfig"
750 source "arch/arm/mach-iop33x/Kconfig"
752 source "arch/arm/mach-iop13xx/Kconfig"
754 source "arch/arm/mach-ixp4xx/Kconfig"
756 source "arch/arm/mach-keystone/Kconfig"
758 source "arch/arm/mach-ks8695/Kconfig"
760 source "arch/arm/mach-meson/Kconfig"
762 source "arch/arm/mach-moxart/Kconfig"
764 source "arch/arm/mach-aspeed/Kconfig"
766 source "arch/arm/mach-mv78xx0/Kconfig"
768 source "arch/arm/mach-imx/Kconfig"
770 source "arch/arm/mach-mediatek/Kconfig"
772 source "arch/arm/mach-mxs/Kconfig"
774 source "arch/arm/mach-netx/Kconfig"
776 source "arch/arm/mach-nomadik/Kconfig"
778 source "arch/arm/mach-nspire/Kconfig"
780 source "arch/arm/plat-omap/Kconfig"
782 source "arch/arm/mach-omap1/Kconfig"
784 source "arch/arm/mach-omap2/Kconfig"
786 source "arch/arm/mach-orion5x/Kconfig"
788 source "arch/arm/mach-picoxcell/Kconfig"
790 source "arch/arm/mach-pxa/Kconfig"
791 source "arch/arm/plat-pxa/Kconfig"
793 source "arch/arm/mach-mmp/Kconfig"
795 source "arch/arm/mach-oxnas/Kconfig"
797 source "arch/arm/mach-qcom/Kconfig"
799 source "arch/arm/mach-realview/Kconfig"
801 source "arch/arm/mach-rockchip/Kconfig"
803 source "arch/arm/mach-sa1100/Kconfig"
805 source "arch/arm/mach-socfpga/Kconfig"
807 source "arch/arm/mach-spear/Kconfig"
809 source "arch/arm/mach-sti/Kconfig"
811 source "arch/arm/mach-stm32/Kconfig"
813 source "arch/arm/mach-s3c24xx/Kconfig"
815 source "arch/arm/mach-s3c64xx/Kconfig"
817 source "arch/arm/mach-s5pv210/Kconfig"
819 source "arch/arm/mach-exynos/Kconfig"
820 source "arch/arm/plat-samsung/Kconfig"
822 source "arch/arm/mach-shmobile/Kconfig"
824 source "arch/arm/mach-sunxi/Kconfig"
826 source "arch/arm/mach-prima2/Kconfig"
828 source "arch/arm/mach-tango/Kconfig"
830 source "arch/arm/mach-tegra/Kconfig"
832 source "arch/arm/mach-u300/Kconfig"
834 source "arch/arm/mach-uniphier/Kconfig"
836 source "arch/arm/mach-ux500/Kconfig"
838 source "arch/arm/mach-versatile/Kconfig"
840 source "arch/arm/mach-vexpress/Kconfig"
841 source "arch/arm/plat-versatile/Kconfig"
843 source "arch/arm/mach-vt8500/Kconfig"
845 source "arch/arm/mach-w90x900/Kconfig"
847 source "arch/arm/mach-zx/Kconfig"
849 source "arch/arm/mach-zynq/Kconfig"
851 # ARMv7-M architecture
853 bool "Energy Micro efm32"
854 depends on ARM_SINGLE_ARMV7M
857 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
861 bool "NXP LPC18xx/LPC43xx"
862 depends on ARM_SINGLE_ARMV7M
863 select ARCH_HAS_RESET_CONTROLLER
865 select CLKSRC_LPC32XX
868 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
869 high performance microcontrollers.
872 bool "ARM MPS2 platform"
873 depends on ARM_SINGLE_ARMV7M
877 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
878 with a range of available cores like Cortex-M3/M4/M7.
880 Please, note that depends which Application Note is used memory map
881 for the platform may vary, so adjustment of RAM base might be needed.
883 # Definitions to make life easier
889 select GENERIC_CLOCKEVENTS
895 select GENERIC_IRQ_CHIP
898 config PLAT_ORION_LEGACY
905 config PLAT_VERSATILE
908 source "arch/arm/firmware/Kconfig"
910 source arch/arm/mm/Kconfig
913 bool "Enable iWMMXt support"
914 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
915 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
917 Enable support for iWMMXt context switching at run time if
918 running on a CPU that supports it.
920 config MULTI_IRQ_HANDLER
923 Allow each machine to specify it's own IRQ handler at run time.
926 source "arch/arm/Kconfig-nommu"
929 config PJ4B_ERRATA_4742
930 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
931 depends on CPU_PJ4B && MACH_ARMADA_370
934 When coming out of either a Wait for Interrupt (WFI) or a Wait for
935 Event (WFE) IDLE states, a specific timing sensitivity exists between
936 the retiring WFI/WFE instructions and the newly issued subsequent
937 instructions. This sensitivity can result in a CPU hang scenario.
939 The software must insert either a Data Synchronization Barrier (DSB)
940 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
943 config ARM_ERRATA_326103
944 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
947 Executing a SWP instruction to read-only memory does not set bit 11
948 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
949 treat the access as a read, preventing a COW from occurring and
950 causing the faulting task to livelock.
952 config ARM_ERRATA_411920
953 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
954 depends on CPU_V6 || CPU_V6K
956 Invalidation of the Instruction Cache operation can
957 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
958 It does not affect the MPCore. This option enables the ARM Ltd.
959 recommended workaround.
961 config ARM_ERRATA_430973
962 bool "ARM errata: Stale prediction on replaced interworking branch"
965 This option enables the workaround for the 430973 Cortex-A8
966 r1p* erratum. If a code sequence containing an ARM/Thumb
967 interworking branch is replaced with another code sequence at the
968 same virtual address, whether due to self-modifying code or virtual
969 to physical address re-mapping, Cortex-A8 does not recover from the
970 stale interworking branch prediction. This results in Cortex-A8
971 executing the new code sequence in the incorrect ARM or Thumb state.
972 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
973 and also flushes the branch target cache at every context switch.
974 Note that setting specific bits in the ACTLR register may not be
975 available in non-secure mode.
977 config ARM_ERRATA_458693
978 bool "ARM errata: Processor deadlock when a false hazard is created"
980 depends on !ARCH_MULTIPLATFORM
982 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
983 erratum. For very specific sequences of memory operations, it is
984 possible for a hazard condition intended for a cache line to instead
985 be incorrectly associated with a different cache line. This false
986 hazard might then cause a processor deadlock. The workaround enables
987 the L1 caching of the NEON accesses and disables the PLD instruction
988 in the ACTLR register. Note that setting specific bits in the ACTLR
989 register may not be available in non-secure mode.
991 config ARM_ERRATA_460075
992 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
994 depends on !ARCH_MULTIPLATFORM
996 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
997 erratum. Any asynchronous access to the L2 cache may encounter a
998 situation in which recent store transactions to the L2 cache are lost
999 and overwritten with stale memory contents from external memory. The
1000 workaround disables the write-allocate mode for the L2 cache via the
1001 ACTLR register. Note that setting specific bits in the ACTLR register
1002 may not be available in non-secure mode.
1004 config ARM_ERRATA_742230
1005 bool "ARM errata: DMB operation may be faulty"
1006 depends on CPU_V7 && SMP
1007 depends on !ARCH_MULTIPLATFORM
1009 This option enables the workaround for the 742230 Cortex-A9
1010 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1011 between two write operations may not ensure the correct visibility
1012 ordering of the two writes. This workaround sets a specific bit in
1013 the diagnostic register of the Cortex-A9 which causes the DMB
1014 instruction to behave as a DSB, ensuring the correct behaviour of
1017 config ARM_ERRATA_742231
1018 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1019 depends on CPU_V7 && SMP
1020 depends on !ARCH_MULTIPLATFORM
1022 This option enables the workaround for the 742231 Cortex-A9
1023 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1024 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1025 accessing some data located in the same cache line, may get corrupted
1026 data due to bad handling of the address hazard when the line gets
1027 replaced from one of the CPUs at the same time as another CPU is
1028 accessing it. This workaround sets specific bits in the diagnostic
1029 register of the Cortex-A9 which reduces the linefill issuing
1030 capabilities of the processor.
1032 config ARM_ERRATA_643719
1033 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1034 depends on CPU_V7 && SMP
1037 This option enables the workaround for the 643719 Cortex-A9 (prior to
1038 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1039 register returns zero when it should return one. The workaround
1040 corrects this value, ensuring cache maintenance operations which use
1041 it behave as intended and avoiding data corruption.
1043 config ARM_ERRATA_720789
1044 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1047 This option enables the workaround for the 720789 Cortex-A9 (prior to
1048 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1049 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1050 As a consequence of this erratum, some TLB entries which should be
1051 invalidated are not, resulting in an incoherency in the system page
1052 tables. The workaround changes the TLB flushing routines to invalidate
1053 entries regardless of the ASID.
1055 config ARM_ERRATA_743622
1056 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1058 depends on !ARCH_MULTIPLATFORM
1060 This option enables the workaround for the 743622 Cortex-A9
1061 (r2p*) erratum. Under very rare conditions, a faulty
1062 optimisation in the Cortex-A9 Store Buffer may lead to data
1063 corruption. This workaround sets a specific bit in the diagnostic
1064 register of the Cortex-A9 which disables the Store Buffer
1065 optimisation, preventing the defect from occurring. This has no
1066 visible impact on the overall performance or power consumption of the
1069 config ARM_ERRATA_751472
1070 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1072 depends on !ARCH_MULTIPLATFORM
1074 This option enables the workaround for the 751472 Cortex-A9 (prior
1075 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1076 completion of a following broadcasted operation if the second
1077 operation is received by a CPU before the ICIALLUIS has completed,
1078 potentially leading to corrupted entries in the cache or TLB.
1080 config ARM_ERRATA_754322
1081 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1084 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1085 r3p*) erratum. A speculative memory access may cause a page table walk
1086 which starts prior to an ASID switch but completes afterwards. This
1087 can populate the micro-TLB with a stale entry which may be hit with
1088 the new ASID. This workaround places two dsb instructions in the mm
1089 switching code so that no page table walks can cross the ASID switch.
1091 config ARM_ERRATA_754327
1092 bool "ARM errata: no automatic Store Buffer drain"
1093 depends on CPU_V7 && SMP
1095 This option enables the workaround for the 754327 Cortex-A9 (prior to
1096 r2p0) erratum. The Store Buffer does not have any automatic draining
1097 mechanism and therefore a livelock may occur if an external agent
1098 continuously polls a memory location waiting to observe an update.
1099 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1100 written polling loops from denying visibility of updates to memory.
1102 config ARM_ERRATA_364296
1103 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1106 This options enables the workaround for the 364296 ARM1136
1107 r0p2 erratum (possible cache data corruption with
1108 hit-under-miss enabled). It sets the undocumented bit 31 in
1109 the auxiliary control register and the FI bit in the control
1110 register, thus disabling hit-under-miss without putting the
1111 processor into full low interrupt latency mode. ARM11MPCore
1114 config ARM_ERRATA_764369
1115 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1116 depends on CPU_V7 && SMP
1118 This option enables the workaround for erratum 764369
1119 affecting Cortex-A9 MPCore with two or more processors (all
1120 current revisions). Under certain timing circumstances, a data
1121 cache line maintenance operation by MVA targeting an Inner
1122 Shareable memory region may fail to proceed up to either the
1123 Point of Coherency or to the Point of Unification of the
1124 system. This workaround adds a DSB instruction before the
1125 relevant cache maintenance functions and sets a specific bit
1126 in the diagnostic control register of the SCU.
1128 config ARM_ERRATA_775420
1129 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1132 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1133 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1134 operation aborts with MMU exception, it might cause the processor
1135 to deadlock. This workaround puts DSB before executing ISB if
1136 an abort may occur on cache maintenance.
1138 config ARM_ERRATA_798181
1139 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1140 depends on CPU_V7 && SMP
1142 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1143 adequately shooting down all use of the old entries. This
1144 option enables the Linux kernel workaround for this erratum
1145 which sends an IPI to the CPUs that are running the same ASID
1146 as the one being invalidated.
1148 config ARM_ERRATA_773022
1149 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1152 This option enables the workaround for the 773022 Cortex-A15
1153 (up to r0p4) erratum. In certain rare sequences of code, the
1154 loop buffer may deliver incorrect instructions. This
1155 workaround disables the loop buffer to avoid the erratum.
1157 config ARM_ERRATA_818325_852422
1158 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1161 This option enables the workaround for:
1162 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1163 instruction might deadlock. Fixed in r0p1.
1164 - Cortex-A12 852422: Execution of a sequence of instructions might
1165 lead to either a data corruption or a CPU deadlock. Not fixed in
1166 any Cortex-A12 cores yet.
1167 This workaround for all both errata involves setting bit[12] of the
1168 Feature Register. This bit disables an optimisation applied to a
1169 sequence of 2 instructions that use opposing condition codes.
1171 config ARM_ERRATA_821420
1172 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1175 This option enables the workaround for the 821420 Cortex-A12
1176 (all revs) erratum. In very rare timing conditions, a sequence
1177 of VMOV to Core registers instructions, for which the second
1178 one is in the shadow of a branch or abort, can lead to a
1179 deadlock when the VMOV instructions are issued out-of-order.
1181 config ARM_ERRATA_825619
1182 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1185 This option enables the workaround for the 825619 Cortex-A12
1186 (all revs) erratum. Within rare timing constraints, executing a
1187 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1188 and Device/Strongly-Ordered loads and stores might cause deadlock
1190 config ARM_ERRATA_852421
1191 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1194 This option enables the workaround for the 852421 Cortex-A17
1195 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1196 execution of a DMB ST instruction might fail to properly order
1197 stores from GroupA and stores from GroupB.
1199 config ARM_ERRATA_852423
1200 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1203 This option enables the workaround for:
1204 - Cortex-A17 852423: Execution of a sequence of instructions might
1205 lead to either a data corruption or a CPU deadlock. Not fixed in
1206 any Cortex-A17 cores yet.
1207 This is identical to Cortex-A12 erratum 852422. It is a separate
1208 config option from the A12 erratum due to the way errata are checked
1213 source "arch/arm/common/Kconfig"
1220 Find out whether you have ISA slots on your motherboard. ISA is the
1221 name of a bus system, i.e. the way the CPU talks to the other stuff
1222 inside your box. Other bus systems are PCI, EISA, MicroChannel
1223 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1224 newer boards don't support it. If you have ISA, say Y, otherwise N.
1226 # Select ISA DMA controller support
1231 # Select ISA DMA interface
1236 bool "PCI support" if MIGHT_HAVE_PCI
1238 Find out whether you have a PCI motherboard. PCI is the name of a
1239 bus system, i.e. the way the CPU talks to the other stuff inside
1240 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1241 VESA. If you have PCI, say Y, otherwise N.
1247 config PCI_DOMAINS_GENERIC
1248 def_bool PCI_DOMAINS
1250 config PCI_NANOENGINE
1251 bool "BSE nanoEngine PCI support"
1252 depends on SA1100_NANOENGINE
1254 Enable PCI on the BSE nanoEngine board.
1259 config PCI_HOST_ITE8152
1261 depends on PCI && MACH_ARMCORE
1265 source "drivers/pci/Kconfig"
1267 source "drivers/pcmcia/Kconfig"
1271 menu "Kernel Features"
1276 This option should be selected by machines which have an SMP-
1279 The only effect of this option is to make the SMP-related
1280 options available to the user for configuration.
1283 bool "Symmetric Multi-Processing"
1284 depends on CPU_V6K || CPU_V7
1285 depends on GENERIC_CLOCKEVENTS
1287 depends on MMU || ARM_MPU
1290 This enables support for systems with more than one CPU. If you have
1291 a system with only one CPU, say N. If you have a system with more
1292 than one CPU, say Y.
1294 If you say N here, the kernel will run on uni- and multiprocessor
1295 machines, but will use only one CPU of a multiprocessor machine. If
1296 you say Y here, the kernel will run on many, but not all,
1297 uniprocessor machines. On a uniprocessor machine, the kernel
1298 will run faster if you say N here.
1300 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1301 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1302 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1304 If you don't know what to do here, say N.
1307 bool "Allow booting SMP kernel on uniprocessor systems"
1308 depends on SMP && !XIP_KERNEL && MMU
1311 SMP kernels contain instructions which fail on non-SMP processors.
1312 Enabling this option allows the kernel to modify itself to make
1313 these instructions safe. Disabling it allows about 1K of space
1316 If you don't know what to do here, say Y.
1318 config ARM_CPU_TOPOLOGY
1319 bool "Support cpu topology definition"
1320 depends on SMP && CPU_V7
1323 Support ARM cpu topology definition. The MPIDR register defines
1324 affinity between processors which is then used to describe the cpu
1325 topology of an ARM System.
1328 bool "Multi-core scheduler support"
1329 depends on ARM_CPU_TOPOLOGY
1331 Multi-core scheduler support improves the CPU scheduler's decision
1332 making when dealing with multi-core CPU chips at a cost of slightly
1333 increased overhead in some places. If unsure say N here.
1336 bool "SMT scheduler support"
1337 depends on ARM_CPU_TOPOLOGY
1339 Improves the CPU scheduler's decision making when dealing with
1340 MultiThreading at a cost of slightly increased overhead in some
1341 places. If unsure say N here.
1346 This option enables support for the ARM system coherency unit
1348 config HAVE_ARM_ARCH_TIMER
1349 bool "Architected timer support"
1351 select ARM_ARCH_TIMER
1352 select GENERIC_CLOCKEVENTS
1354 This option enables support for the ARM architected timer
1358 select TIMER_OF if OF
1360 This options enables support for the ARM timer and watchdog unit
1363 bool "Multi-Cluster Power Management"
1364 depends on CPU_V7 && SMP
1366 This option provides the common power management infrastructure
1367 for (multi-)cluster based systems, such as big.LITTLE based
1370 config MCPM_QUAD_CLUSTER
1374 To avoid wasting resources unnecessarily, MCPM only supports up
1375 to 2 clusters by default.
1376 Platforms with 3 or 4 clusters that use MCPM must select this
1377 option to allow the additional clusters to be managed.
1380 bool "big.LITTLE support (Experimental)"
1381 depends on CPU_V7 && SMP
1384 This option enables support selections for the big.LITTLE
1385 system architecture.
1388 bool "big.LITTLE switcher support"
1389 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1392 The big.LITTLE "switcher" provides the core functionality to
1393 transparently handle transition between a cluster of A15's
1394 and a cluster of A7's in a big.LITTLE system.
1396 config BL_SWITCHER_DUMMY_IF
1397 tristate "Simple big.LITTLE switcher user interface"
1398 depends on BL_SWITCHER && DEBUG_KERNEL
1400 This is a simple and dummy char dev interface to control
1401 the big.LITTLE switcher core code. It is meant for
1402 debugging purposes only.
1405 prompt "Memory split"
1409 Select the desired split between kernel and user memory.
1411 If you are not absolutely sure what you are doing, leave this
1415 bool "3G/1G user/kernel split"
1416 config VMSPLIT_3G_OPT
1417 depends on !ARM_LPAE
1418 bool "3G/1G user/kernel split (for full 1G low memory)"
1420 bool "2G/2G user/kernel split"
1422 bool "1G/3G user/kernel split"
1427 default PHYS_OFFSET if !MMU
1428 default 0x40000000 if VMSPLIT_1G
1429 default 0x80000000 if VMSPLIT_2G
1430 default 0xB0000000 if VMSPLIT_3G_OPT
1434 int "Maximum number of CPUs (2-32)"
1440 bool "Support for hot-pluggable CPUs"
1443 Say Y here to experiment with turning CPUs off and on. CPUs
1444 can be controlled through /sys/devices/system/cpu.
1447 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1448 depends on HAVE_ARM_SMCCC
1451 Say Y here if you want Linux to communicate with system firmware
1452 implementing the PSCI specification for CPU-centric power
1453 management operations described in ARM document number ARM DEN
1454 0022A ("Power State Coordination Interface System Software on
1457 # The GPIO number here must be sorted by descending number. In case of
1458 # a multiplatform kernel, we just want the highest value required by the
1459 # selected platforms.
1462 default 2048 if ARCH_SOCFPGA
1463 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1465 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1466 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1467 default 416 if ARCH_SUNXI
1468 default 392 if ARCH_U8500
1469 default 352 if ARCH_VT8500
1470 default 288 if ARCH_ROCKCHIP
1471 default 264 if MACH_H4700
1474 Maximum number of GPIOs in the system.
1476 If unsure, leave the default value.
1478 source kernel/Kconfig.preempt
1482 default 200 if ARCH_EBSA110
1483 default 128 if SOC_AT91RM9200
1487 depends on HZ_FIXED = 0
1488 prompt "Timer frequency"
1512 default HZ_FIXED if HZ_FIXED != 0
1513 default 100 if HZ_100
1514 default 200 if HZ_200
1515 default 250 if HZ_250
1516 default 300 if HZ_300
1517 default 500 if HZ_500
1521 def_bool HIGH_RES_TIMERS
1523 config THUMB2_KERNEL
1524 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1525 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1526 default y if CPU_THUMBONLY
1527 select ARM_ASM_UNIFIED
1530 By enabling this option, the kernel will be compiled in
1531 Thumb-2 mode. A compiler/assembler that understand the unified
1532 ARM-Thumb syntax is needed.
1536 config THUMB2_AVOID_R_ARM_THM_JUMP11
1537 bool "Work around buggy Thumb-2 short branch relocations in gas"
1538 depends on THUMB2_KERNEL && MODULES
1541 Various binutils versions can resolve Thumb-2 branches to
1542 locally-defined, preemptible global symbols as short-range "b.n"
1543 branch instructions.
1545 This is a problem, because there's no guarantee the final
1546 destination of the symbol, or any candidate locations for a
1547 trampoline, are within range of the branch. For this reason, the
1548 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1549 relocation in modules at all, and it makes little sense to add
1552 The symptom is that the kernel fails with an "unsupported
1553 relocation" error when loading some modules.
1555 Until fixed tools are available, passing
1556 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1557 code which hits this problem, at the cost of a bit of extra runtime
1558 stack usage in some cases.
1560 The problem is described in more detail at:
1561 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1563 Only Thumb-2 kernels are affected.
1565 Unless you are sure your tools don't have this problem, say Y.
1567 config ARM_ASM_UNIFIED
1570 config ARM_PATCH_IDIV
1571 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1572 depends on CPU_32v7 && !XIP_KERNEL
1575 The ARM compiler inserts calls to __aeabi_idiv() and
1576 __aeabi_uidiv() when it needs to perform division on signed
1577 and unsigned integers. Some v7 CPUs have support for the sdiv
1578 and udiv instructions that can be used to implement those
1581 Enabling this option allows the kernel to modify itself to
1582 replace the first two instructions of these library functions
1583 with the sdiv or udiv plus "bx lr" instructions when the CPU
1584 it is running on supports them. Typically this will be faster
1585 and less power intensive than running the original library
1586 code to do integer division.
1589 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1590 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1592 This option allows for the kernel to be compiled using the latest
1593 ARM ABI (aka EABI). This is only useful if you are using a user
1594 space environment that is also compiled with EABI.
1596 Since there are major incompatibilities between the legacy ABI and
1597 EABI, especially with regard to structure member alignment, this
1598 option also changes the kernel syscall calling convention to
1599 disambiguate both ABIs and allow for backward compatibility support
1600 (selected with CONFIG_OABI_COMPAT).
1602 To use this you need GCC version 4.0.0 or later.
1605 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1606 depends on AEABI && !THUMB2_KERNEL
1608 This option preserves the old syscall interface along with the
1609 new (ARM EABI) one. It also provides a compatibility layer to
1610 intercept syscalls that have structure arguments which layout
1611 in memory differs between the legacy ABI and the new ARM EABI
1612 (only for non "thumb" binaries). This option adds a tiny
1613 overhead to all syscalls and produces a slightly larger kernel.
1615 The seccomp filter system will not be available when this is
1616 selected, since there is no way yet to sensibly distinguish
1617 between calling conventions during filtering.
1619 If you know you'll be using only pure EABI user space then you
1620 can say N here. If this option is not selected and you attempt
1621 to execute a legacy ABI binary then the result will be
1622 UNPREDICTABLE (in fact it can be predicted that it won't work
1623 at all). If in doubt say N.
1625 config ARCH_HAS_HOLES_MEMORYMODEL
1628 config ARCH_SPARSEMEM_ENABLE
1631 config ARCH_SPARSEMEM_DEFAULT
1632 def_bool ARCH_SPARSEMEM_ENABLE
1634 config ARCH_SELECT_MEMORY_MODEL
1635 def_bool ARCH_SPARSEMEM_ENABLE
1637 config HAVE_ARCH_PFN_VALID
1638 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1640 config HAVE_GENERIC_GUP
1645 bool "High Memory Support"
1648 The address space of ARM processors is only 4 Gigabytes large
1649 and it has to accommodate user address space, kernel address
1650 space as well as some memory mapped IO. That means that, if you
1651 have a large amount of physical memory and/or IO, not all of the
1652 memory can be "permanently mapped" by the kernel. The physical
1653 memory that is not permanently mapped is called "high memory".
1655 Depending on the selected kernel/user memory split, minimum
1656 vmalloc space and actual amount of RAM, you may not need this
1657 option which should result in a slightly faster kernel.
1662 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1666 The VM uses one page of physical memory for each page table.
1667 For systems with a lot of processes, this can use a lot of
1668 precious low memory, eventually leading to low memory being
1669 consumed by page tables. Setting this option will allow
1670 user-space 2nd level page tables to reside in high memory.
1672 config CPU_SW_DOMAIN_PAN
1673 bool "Enable use of CPU domains to implement privileged no-access"
1674 depends on MMU && !ARM_LPAE
1677 Increase kernel security by ensuring that normal kernel accesses
1678 are unable to access userspace addresses. This can help prevent
1679 use-after-free bugs becoming an exploitable privilege escalation
1680 by ensuring that magic values (such as LIST_POISON) will always
1681 fault when dereferenced.
1683 CPUs with low-vector mappings use a best-efforts implementation.
1684 Their lower 1MB needs to remain accessible for the vectors, but
1685 the remainder of userspace will become appropriately inaccessible.
1687 config HW_PERF_EVENTS
1691 config SYS_SUPPORTS_HUGETLBFS
1695 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1699 config ARCH_WANT_GENERAL_HUGETLB
1702 config ARM_MODULE_PLTS
1703 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1706 Allocate PLTs when loading modules so that jumps and calls whose
1707 targets are too far away for their relative offsets to be encoded
1708 in the instructions themselves can be bounced via veneers in the
1709 module's PLT. This allows modules to be allocated in the generic
1710 vmalloc area after the dedicated module memory area has been
1711 exhausted. The modules will use slightly more memory, but after
1712 rounding up to page size, the actual memory footprint is usually
1715 Say y if you are getting out of memory errors while loading modules
1719 config FORCE_MAX_ZONEORDER
1720 int "Maximum zone order"
1721 default "12" if SOC_AM33XX
1722 default "9" if SA1111 || ARCH_EFM32
1725 The kernel memory allocator divides physically contiguous memory
1726 blocks into "zones", where each zone is a power of two number of
1727 pages. This option selects the largest power of two that the kernel
1728 keeps in the memory allocator. If you need to allocate very large
1729 blocks of physically contiguous memory, then you may need to
1730 increase this value.
1732 This config option is actually maximum order plus one. For example,
1733 a value of 11 means that the largest free memory block is 2^10 pages.
1735 config ALIGNMENT_TRAP
1737 depends on CPU_CP15_MMU
1738 default y if !ARCH_EBSA110
1739 select HAVE_PROC_CPU if PROC_FS
1741 ARM processors cannot fetch/store information which is not
1742 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1743 address divisible by 4. On 32-bit ARM processors, these non-aligned
1744 fetch/store instructions will be emulated in software if you say
1745 here, which has a severe performance impact. This is necessary for
1746 correct operation of some network protocols. With an IP-only
1747 configuration it is safe to say N, otherwise say Y.
1749 config UACCESS_WITH_MEMCPY
1750 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1752 default y if CPU_FEROCEON
1754 Implement faster copy_to_user and clear_user methods for CPU
1755 cores where a 8-word STM instruction give significantly higher
1756 memory write throughput than a sequence of individual 32bit stores.
1758 A possible side effect is a slight increase in scheduling latency
1759 between threads sharing the same address space if they invoke
1760 such copy operations with large buffers.
1762 However, if the CPU data cache is using a write-allocate mode,
1763 this option is unlikely to provide any performance gain.
1767 prompt "Enable seccomp to safely compute untrusted bytecode"
1769 This kernel feature is useful for number crunching applications
1770 that may need to compute untrusted bytecode during their
1771 execution. By using pipes or other transports made available to
1772 the process as file descriptors supporting the read/write
1773 syscalls, it's possible to isolate those applications in
1774 their own address space using seccomp. Once seccomp is
1775 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1776 and the task is only allowed to execute a few safe syscalls
1777 defined by each seccomp mode.
1786 bool "Enable paravirtualization code"
1788 This changes the kernel so it can modify itself when it is run
1789 under a hypervisor, potentially improving performance significantly
1790 over full virtualization.
1792 config PARAVIRT_TIME_ACCOUNTING
1793 bool "Paravirtual steal time accounting"
1797 Select this option to enable fine granularity task steal time
1798 accounting. Time spent executing other tasks in parallel with
1799 the current vCPU is discounted from the vCPU power. To account for
1800 that, there can be a small performance impact.
1802 If in doubt, say N here.
1809 bool "Xen guest support on ARM"
1810 depends on ARM && AEABI && OF
1811 depends on CPU_V7 && !CPU_V6
1812 depends on !GENERIC_ATOMIC64
1814 select ARCH_DMA_ADDR_T_64BIT
1819 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1826 bool "Flattened Device Tree support"
1830 Include support for flattened device tree machine descriptions.
1833 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1836 This is the traditional way of passing data to the kernel at boot
1837 time. If you are solely relying on the flattened device tree (or
1838 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1839 to remove ATAGS support from your kernel binary. If unsure,
1842 config DEPRECATED_PARAM_STRUCT
1843 bool "Provide old way to pass kernel parameters"
1846 This was deprecated in 2001 and announced to live on for 5 years.
1847 Some old boot loaders still use this way.
1849 # Compressed boot loader in ROM. Yes, we really want to ask about
1850 # TEXT and BSS so we preserve their values in the config files.
1851 config ZBOOT_ROM_TEXT
1852 hex "Compressed ROM boot loader base address"
1855 The physical address at which the ROM-able zImage is to be
1856 placed in the target. Platforms which normally make use of
1857 ROM-able zImage formats normally set this to a suitable
1858 value in their defconfig file.
1860 If ZBOOT_ROM is not enabled, this has no effect.
1862 config ZBOOT_ROM_BSS
1863 hex "Compressed ROM boot loader BSS address"
1866 The base address of an area of read/write memory in the target
1867 for the ROM-able zImage which must be available while the
1868 decompressor is running. It must be large enough to hold the
1869 entire decompressed kernel plus an additional 128 KiB.
1870 Platforms which normally make use of ROM-able zImage formats
1871 normally set this to a suitable value in their defconfig file.
1873 If ZBOOT_ROM is not enabled, this has no effect.
1876 bool "Compressed boot loader in ROM/flash"
1877 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1878 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1880 Say Y here if you intend to execute your compressed kernel image
1881 (zImage) directly from ROM or flash. If unsure, say N.
1883 config ARM_APPENDED_DTB
1884 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1887 With this option, the boot code will look for a device tree binary
1888 (DTB) appended to zImage
1889 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1891 This is meant as a backward compatibility convenience for those
1892 systems with a bootloader that can't be upgraded to accommodate
1893 the documented boot protocol using a device tree.
1895 Beware that there is very little in terms of protection against
1896 this option being confused by leftover garbage in memory that might
1897 look like a DTB header after a reboot if no actual DTB is appended
1898 to zImage. Do not leave this option active in a production kernel
1899 if you don't intend to always append a DTB. Proper passing of the
1900 location into r2 of a bootloader provided DTB is always preferable
1903 config ARM_ATAG_DTB_COMPAT
1904 bool "Supplement the appended DTB with traditional ATAG information"
1905 depends on ARM_APPENDED_DTB
1907 Some old bootloaders can't be updated to a DTB capable one, yet
1908 they provide ATAGs with memory configuration, the ramdisk address,
1909 the kernel cmdline string, etc. Such information is dynamically
1910 provided by the bootloader and can't always be stored in a static
1911 DTB. To allow a device tree enabled kernel to be used with such
1912 bootloaders, this option allows zImage to extract the information
1913 from the ATAG list and store it at run time into the appended DTB.
1916 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1917 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920 bool "Use bootloader kernel arguments if available"
1922 Uses the command-line options passed by the boot loader instead of
1923 the device tree bootargs property. If the boot loader doesn't provide
1924 any, the device tree bootargs property will be used.
1926 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1927 bool "Extend with bootloader kernel arguments"
1929 The command-line arguments provided by the boot loader will be
1930 appended to the the device tree bootargs property.
1935 string "Default kernel command string"
1938 On some architectures (EBSA110 and CATS), there is currently no way
1939 for the boot loader to pass arguments to the kernel. For these
1940 architectures, you should supply some command-line options at build
1941 time by entering them here. As a minimum, you should specify the
1942 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1945 prompt "Kernel command line type" if CMDLINE != ""
1946 default CMDLINE_FROM_BOOTLOADER
1949 config CMDLINE_FROM_BOOTLOADER
1950 bool "Use bootloader kernel arguments if available"
1952 Uses the command-line options passed by the boot loader. If
1953 the boot loader doesn't provide any, the default kernel command
1954 string provided in CMDLINE will be used.
1956 config CMDLINE_EXTEND
1957 bool "Extend bootloader kernel arguments"
1959 The command-line arguments provided by the boot loader will be
1960 appended to the default kernel command string.
1962 config CMDLINE_FORCE
1963 bool "Always use the default kernel command string"
1965 Always use the default kernel command string, even if the boot
1966 loader passes other arguments to the kernel.
1967 This is useful if you cannot or don't want to change the
1968 command-line options your boot loader passes to the kernel.
1972 bool "Kernel Execute-In-Place from ROM"
1973 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1975 Execute-In-Place allows the kernel to run from non-volatile storage
1976 directly addressable by the CPU, such as NOR flash. This saves RAM
1977 space since the text section of the kernel is not loaded from flash
1978 to RAM. Read-write sections, such as the data section and stack,
1979 are still copied to RAM. The XIP kernel is not compressed since
1980 it has to run directly from flash, so it will take more space to
1981 store it. The flash address used to link the kernel object files,
1982 and for storing it, is configuration dependent. Therefore, if you
1983 say Y here, you must know the proper physical address where to
1984 store the kernel image depending on your own flash memory usage.
1986 Also note that the make target becomes "make xipImage" rather than
1987 "make zImage" or "make Image". The final kernel binary to put in
1988 ROM memory will be arch/arm/boot/xipImage.
1992 config XIP_PHYS_ADDR
1993 hex "XIP Kernel Physical Location"
1994 depends on XIP_KERNEL
1995 default "0x00080000"
1997 This is the physical address in your flash memory the kernel will
1998 be linked for and stored to. This address is dependent on your
2001 config XIP_DEFLATED_DATA
2002 bool "Store kernel .data section compressed in ROM"
2003 depends on XIP_KERNEL
2006 Before the kernel is actually executed, its .data section has to be
2007 copied to RAM from ROM. This option allows for storing that data
2008 in compressed form and decompressed to RAM rather than merely being
2009 copied, saving some precious ROM space. A possible drawback is a
2010 slightly longer boot delay.
2013 bool "Kexec system call (EXPERIMENTAL)"
2014 depends on (!SMP || PM_SLEEP_SMP)
2018 kexec is a system call that implements the ability to shutdown your
2019 current kernel, and to start another kernel. It is like a reboot
2020 but it is independent of the system firmware. And like a reboot
2021 you can start any kernel with it, not just Linux.
2023 It is an ongoing process to be certain the hardware in a machine
2024 is properly shutdown, so do not be surprised if this code does not
2025 initially work for you.
2028 bool "Export atags in procfs"
2029 depends on ATAGS && KEXEC
2032 Should the atags used to boot the kernel be exported in an "atags"
2033 file in procfs. Useful with kexec.
2036 bool "Build kdump crash kernel (EXPERIMENTAL)"
2038 Generate crash dump after being started by kexec. This should
2039 be normally only set in special crash dump kernels which are
2040 loaded in the main kernel with kexec-tools into a specially
2041 reserved region and then later executed after a crash by
2042 kdump/kexec. The crash dump kernel must be compiled to a
2043 memory address not used by the main kernel
2045 For more details see Documentation/kdump/kdump.txt
2047 config AUTO_ZRELADDR
2048 bool "Auto calculation of the decompressed kernel image address"
2050 ZRELADDR is the physical address where the decompressed kernel
2051 image will be placed. If AUTO_ZRELADDR is selected, the address
2052 will be determined at run-time by masking the current IP with
2053 0xf8000000. This assumes the zImage being placed in the first 128MB
2054 from start of memory.
2060 bool "UEFI runtime support"
2061 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2063 select EFI_PARAMS_FROM_FDT
2066 select EFI_RUNTIME_WRAPPERS
2068 This option provides support for runtime services provided
2069 by UEFI firmware (such as non-volatile variables, realtime
2070 clock, and platform reset). A UEFI stub is also provided to
2071 allow the kernel to be booted as an EFI application. This
2072 is only useful for kernels that may run on systems that have
2076 bool "Enable support for SMBIOS (DMI) tables"
2080 This enables SMBIOS/DMI feature for systems.
2082 This option is only useful on systems that have UEFI firmware.
2083 However, even with this option, the resultant kernel should
2084 continue to boot on existing non-UEFI platforms.
2086 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2087 i.e., the the practice of identifying the platform via DMI to
2088 decide whether certain workarounds for buggy hardware and/or
2089 firmware need to be enabled. This would require the DMI subsystem
2090 to be enabled much earlier than we do on ARM, which is non-trivial.
2094 menu "CPU Power Management"
2096 source "drivers/cpufreq/Kconfig"
2098 source "drivers/cpuidle/Kconfig"
2102 menu "Floating point emulation"
2104 comment "At least one emulation must be selected"
2107 bool "NWFPE math emulation"
2108 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2110 Say Y to include the NWFPE floating point emulator in the kernel.
2111 This is necessary to run most binaries. Linux does not currently
2112 support floating point hardware so you need to say Y here even if
2113 your machine has an FPA or floating point co-processor podule.
2115 You may say N here if you are going to load the Acorn FPEmulator
2116 early in the bootup.
2119 bool "Support extended precision"
2120 depends on FPE_NWFPE
2122 Say Y to include 80-bit support in the kernel floating-point
2123 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2124 Note that gcc does not generate 80-bit operations by default,
2125 so in most cases this option only enlarges the size of the
2126 floating point emulator without any good reason.
2128 You almost surely want to say N here.
2131 bool "FastFPE math emulation (EXPERIMENTAL)"
2132 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2134 Say Y here to include the FAST floating point emulator in the kernel.
2135 This is an experimental much faster emulator which now also has full
2136 precision for the mantissa. It does not support any exceptions.
2137 It is very simple, and approximately 3-6 times faster than NWFPE.
2139 It should be sufficient for most programs. It may be not suitable
2140 for scientific calculations, but you have to check this for yourself.
2141 If you do not feel you need a faster FP emulation you should better
2145 bool "VFP-format floating point maths"
2146 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2148 Say Y to include VFP support code in the kernel. This is needed
2149 if your hardware includes a VFP unit.
2151 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2152 release notes and additional status information.
2154 Say N if your target does not have VFP hardware.
2162 bool "Advanced SIMD (NEON) Extension support"
2163 depends on VFPv3 && CPU_V7
2165 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2168 config KERNEL_MODE_NEON
2169 bool "Support for NEON in kernel mode"
2170 depends on NEON && AEABI
2172 Say Y to include support for NEON in kernel mode.
2176 menu "Userspace binary formats"
2178 source "fs/Kconfig.binfmt"
2182 menu "Power management options"
2184 source "kernel/power/Kconfig"
2186 config ARCH_SUSPEND_POSSIBLE
2187 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2188 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2191 config ARM_CPU_SUSPEND
2192 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2193 depends on ARCH_SUSPEND_POSSIBLE
2195 config ARCH_HIBERNATION_POSSIBLE
2198 default y if ARCH_SUSPEND_POSSIBLE
2202 source "net/Kconfig"
2204 source "drivers/Kconfig"
2206 source "drivers/firmware/Kconfig"
2210 source "arch/arm/Kconfig.debug"
2212 source "security/Kconfig"
2214 source "crypto/Kconfig"
2216 source "arch/arm/crypto/Kconfig"
2219 source "lib/Kconfig"
2221 source "arch/arm/kvm/Kconfig"