arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select EDAC_SUPPORT
  19         select EDAC_ATOMIC_SCRUB
  20         select GENERIC_ALLOCATOR
  21         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  22         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  23         select GENERIC_IDLE_POLL_SETUP
  24         select GENERIC_IRQ_PROBE
  25         select GENERIC_IRQ_SHOW
  26         select GENERIC_IRQ_SHOW_LEVEL
  27         select GENERIC_PCI_IOMAP
  28         select GENERIC_SCHED_CLOCK
  29         select GENERIC_SMP_IDLE_THREAD
  30         select GENERIC_STRNCPY_FROM_USER
  31         select GENERIC_STRNLEN_USER
  32         select HANDLE_DOMAIN_IRQ
  33         select HARDIRQS_SW_RESEND
  34         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  35         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  36         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
  37         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
  38         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  39         select HAVE_ARCH_TRACEHOOK
  40         select HAVE_BPF_JIT
  41         select HAVE_CC_STACKPROTECTOR
  42         select HAVE_CONTEXT_TRACKING
  43         select HAVE_C_RECORDMCOUNT
  44         select HAVE_DEBUG_KMEMLEAK
  45         select HAVE_DMA_API_DEBUG
  46         select HAVE_DMA_ATTRS
  47         select HAVE_DMA_CONTIGUOUS if MMU
  48         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
  49         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  50         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  51         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  52         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  53         select HAVE_GENERIC_DMA_COHERENT
  54         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  55         select HAVE_IDE if PCI || ISA || PCMCIA
  56         select HAVE_IRQ_TIME_ACCOUNTING
  57         select HAVE_KERNEL_GZIP
  58         select HAVE_KERNEL_LZ4
  59         select HAVE_KERNEL_LZMA
  60         select HAVE_KERNEL_LZO
  61         select HAVE_KERNEL_XZ
  62         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  63         select HAVE_KRETPROBES if (HAVE_KPROBES)
  64         select HAVE_MEMBLOCK
  65         select HAVE_MOD_ARCH_SPECIFIC
  66         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  67         select HAVE_OPTPROBES if !THUMB2_KERNEL
  68         select HAVE_PERF_EVENTS
  69         select HAVE_PERF_REGS
  70         select HAVE_PERF_USER_STACK_DUMP
  71         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  72         select HAVE_REGS_AND_STACK_ACCESS_API
  73         select HAVE_SYSCALL_TRACEPOINTS
  74         select HAVE_UID16
  75         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  76         select IRQ_FORCED_THREADING
  77         select MODULES_USE_ELF_REL
  78         select NO_BOOTMEM
  79         select OLD_SIGACTION
  80         select OLD_SIGSUSPEND3
  81         select PERF_USE_VMALLOC
  82         select RTC_LIB
  83         select SYS_SUPPORTS_APM_EMULATION
  84         # Above selects are sorted alphabetically; please add new ones
  85         # according to that.  Thanks.
  86         help
  87           The ARM series is a line of low-power-consumption RISC chip designs
  88           licensed by ARM Ltd and targeted at embedded applications and
  89           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  90           manufactured, but legacy ARM-based PC hardware remains popular in
  91           Europe.  There is an ARM Linux project with a web page at
  92           <http://www.arm.linux.org.uk/>.
  93
  94 config ARM_HAS_SG_CHAIN
  95         select ARCH_HAS_SG_CHAIN
  96         bool
  97
  98 config NEED_SG_DMA_LENGTH
  99         bool
 100
 101 config ARM_DMA_USE_IOMMU
 102         bool
 103         select ARM_HAS_SG_CHAIN
 104         select NEED_SG_DMA_LENGTH
 105
 106 if ARM_DMA_USE_IOMMU
 107
 108 config ARM_DMA_IOMMU_ALIGNMENT
 109         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 110         range 4 9
 111         default 8
 112         help
 113           DMA mapping framework by default aligns all buffers to the smallest
 114           PAGE_SIZE order which is greater than or equal to the requested buffer
 115           size. This works well for buffers up to a few hundreds kilobytes, but
 116           for larger buffers it just a waste of address space. Drivers which has
 117           relatively small addressing window (like 64Mib) might run out of
 118           virtual space with just a few allocations.
 119
 120           With this parameter you can specify the maximum PAGE_SIZE order for
 121           DMA IOMMU buffers. Larger buffers will be aligned only to this
 122           specified order. The order is expressed as a power of two multiplied
 123           by the PAGE_SIZE.
 124
 125 endif
 126
 127 config MIGHT_HAVE_PCI
 128         bool
 129
 130 config SYS_SUPPORTS_APM_EMULATION
 131         bool
 132
 133 config HAVE_TCM
 134         bool
 135         select GENERIC_ALLOCATOR
 136
 137 config HAVE_PROC_CPU
 138         bool
 139
 140 config NO_IOPORT_MAP
 141         bool
 142
 143 config EISA
 144         bool
 145         ---help---
 146           The Extended Industry Standard Architecture (EISA) bus was
 147           developed as an open alternative to the IBM MicroChannel bus.
 148
 149           The EISA bus provided some of the features of the IBM MicroChannel
 150           bus while maintaining backward compatibility with cards made for
 151           the older ISA bus.  The EISA bus saw limited use between 1988 and
 152           1995 when it was made obsolete by the PCI bus.
 153
 154           Say Y here if you are building a kernel for an EISA-based machine.
 155
 156           Otherwise, say N.
 157
 158 config SBUS
 159         bool
 160
 161 config STACKTRACE_SUPPORT
 162         bool
 163         default y
 164
 165 config HAVE_LATENCYTOP_SUPPORT
 166         bool
 167         depends on !SMP
 168         default y
 169
 170 config LOCKDEP_SUPPORT
 171         bool
 172         default y
 173
 174 config TRACE_IRQFLAGS_SUPPORT
 175         bool
 176         default !CPU_V7M
 177
 178 config RWSEM_XCHGADD_ALGORITHM
 179         bool
 180         default y
 181
 182 config ARCH_HAS_ILOG2_U32
 183         bool
 184
 185 config ARCH_HAS_ILOG2_U64
 186         bool
 187
 188 config ARCH_HAS_BANDGAP
 189         bool
 190
 191 config FIX_EARLYCON_MEM
 192         def_bool y if MMU
 193
 194 config GENERIC_HWEIGHT
 195         bool
 196         default y
 197
 198 config GENERIC_CALIBRATE_DELAY
 199         bool
 200         default y
 201
 202 config ARCH_MAY_HAVE_PC_FDC
 203         bool
 204
 205 config ZONE_DMA
 206         bool
 207
 208 config NEED_DMA_MAP_STATE
 209        def_bool y
 210
 211 config ARCH_SUPPORTS_UPROBES
 212         def_bool y
 213
 214 config ARCH_HAS_DMA_SET_COHERENT_MASK
 215         bool
 216
 217 config GENERIC_ISA_DMA
 218         bool
 219
 220 config FIQ
 221         bool
 222
 223 config NEED_RET_TO_USER
 224         bool
 225
 226 config ARCH_MTD_XIP
 227         bool
 228
 229 config VECTORS_BASE
 230         hex
 231         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 232         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 233         default 0x00000000
 234         help
 235           The base address of exception vectors.  This must be two pages
 236           in size.
 237
 238 config ARM_PATCH_PHYS_VIRT
 239         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 240         default y
 241         depends on !XIP_KERNEL && MMU
 242         depends on !ARCH_REALVIEW || !SPARSEMEM
 243         help
 244           Patch phys-to-virt and virt-to-phys translation functions at
 245           boot and module load time according to the position of the
 246           kernel in system memory.
 247
 248           This can only be used with non-XIP MMU kernels where the base
 249           of physical memory is at a 16MB boundary.
 250
 251           Only disable this option if you know that you do not require
 252           this feature (eg, building a kernel for a single machine) and
 253           you need to shrink the kernel to the minimal size.
 254
 255 config NEED_MACH_IO_H
 256         bool
 257         help
 258           Select this when mach/io.h is required to provide special
 259           definitions for this platform.  The need for mach/io.h should
 260           be avoided when possible.
 261
 262 config NEED_MACH_MEMORY_H
 263         bool
 264         help
 265           Select this when mach/memory.h is required to provide special
 266           definitions for this platform.  The need for mach/memory.h should
 267           be avoided when possible.
 268
 269 config PHYS_OFFSET
 270         hex "Physical address of main memory" if MMU
 271         depends on !ARM_PATCH_PHYS_VIRT
 272         default DRAM_BASE if !MMU
 273         default 0x00000000 if ARCH_EBSA110 || \
 274                         ARCH_FOOTBRIDGE || \
 275                         ARCH_INTEGRATOR || \
 276                         ARCH_IOP13XX || \
 277                         ARCH_KS8695 || \
 278                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 279         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 280         default 0x20000000 if ARCH_S5PV210
 281         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 282         default 0xc0000000 if ARCH_SA1100
 283         help
 284           Please provide the physical address corresponding to the
 285           location of main memory in your system.
 286
 287 config GENERIC_BUG
 288         def_bool y
 289         depends on BUG
 290
 291 config PGTABLE_LEVELS
 292         int
 293         default 3 if ARM_LPAE
 294         default 2
 295
 296 source "init/Kconfig"
 297
 298 source "kernel/Kconfig.freezer"
 299
 300 menu "System Type"
 301
 302 config MMU
 303         bool "MMU-based Paged Memory Management Support"
 304         default y
 305         help
 306           Select if you want MMU-based virtualised addressing space
 307           support by paged memory management. If unsure, say 'Y'.
 308
 309 #
 310 # The "ARM system type" choice list is ordered alphabetically by option
 311 # text.  Please add new entries in the option alphabetic order.
 312 #
 313 choice
 314         prompt "ARM system type"
 315         default ARCH_VERSATILE if !MMU
 316         default ARCH_MULTIPLATFORM if MMU
 317
 318 config ARCH_MULTIPLATFORM
 319         bool "Allow multiple platforms to be selected"
 320         depends on MMU
 321         select ARCH_WANT_OPTIONAL_GPIOLIB
 322         select ARM_HAS_SG_CHAIN
 323         select ARM_PATCH_PHYS_VIRT
 324         select AUTO_ZRELADDR
 325         select CLKSRC_OF
 326         select COMMON_CLK
 327         select GENERIC_CLOCKEVENTS
 328         select MIGHT_HAVE_PCI
 329         select MULTI_IRQ_HANDLER
 330         select SPARSE_IRQ
 331         select USE_OF
 332
 333 config ARM_SINGLE_ARMV7M
 334         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 335         depends on !MMU
 336         select ARCH_WANT_OPTIONAL_GPIOLIB
 337         select ARM_NVIC
 338         select AUTO_ZRELADDR
 339         select CLKSRC_OF
 340         select COMMON_CLK
 341         select CPU_V7M
 342         select GENERIC_CLOCKEVENTS
 343         select NO_IOPORT_MAP
 344         select SPARSE_IRQ
 345         select USE_OF
 346
 347 config ARCH_REALVIEW
 348         bool "ARM Ltd. RealView family"
 349         select ARCH_WANT_OPTIONAL_GPIOLIB
 350         select ARM_AMBA
 351         select ARM_TIMER_SP804
 352         select COMMON_CLK
 353         select COMMON_CLK_VERSATILE
 354         select GENERIC_CLOCKEVENTS
 355         select GPIO_PL061 if GPIOLIB
 356         select ICST
 357         select NEED_MACH_MEMORY_H
 358         select PLAT_VERSATILE
 359         select PLAT_VERSATILE_SCHED_CLOCK
 360         help
 361           This enables support for ARM Ltd RealView boards.
 362
 363 config ARCH_VERSATILE
 364         bool "ARM Ltd. Versatile family"
 365         select ARCH_WANT_OPTIONAL_GPIOLIB
 366         select ARM_AMBA
 367         select ARM_TIMER_SP804
 368         select ARM_VIC
 369         select CLKDEV_LOOKUP
 370         select GENERIC_CLOCKEVENTS
 371         select HAVE_MACH_CLKDEV
 372         select ICST
 373         select PLAT_VERSATILE
 374         select PLAT_VERSATILE_CLOCK
 375         select PLAT_VERSATILE_SCHED_CLOCK
 376         select VERSATILE_FPGA_IRQ
 377         help
 378           This enables support for ARM Ltd Versatile board.
 379
 380 config ARCH_CLPS711X
 381         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 382         select ARCH_REQUIRE_GPIOLIB
 383         select AUTO_ZRELADDR
 384         select CLKSRC_MMIO
 385         select COMMON_CLK
 386         select CPU_ARM720T
 387         select GENERIC_CLOCKEVENTS
 388         select MFD_SYSCON
 389         select SOC_BUS
 390         help
 391           Support for Cirrus Logic 711x/721x/731x based boards.
 392
 393 config ARCH_GEMINI
 394         bool "Cortina Systems Gemini"
 395         select ARCH_REQUIRE_GPIOLIB
 396         select CLKSRC_MMIO
 397         select CPU_FA526
 398         select GENERIC_CLOCKEVENTS
 399         help
 400           Support for the Cortina Systems Gemini family SoCs
 401
 402 config ARCH_EBSA110
 403         bool "EBSA-110"
 404         select ARCH_USES_GETTIMEOFFSET
 405         select CPU_SA110
 406         select ISA
 407         select NEED_MACH_IO_H
 408         select NEED_MACH_MEMORY_H
 409         select NO_IOPORT_MAP
 410         help
 411           This is an evaluation board for the StrongARM processor available
 412           from Digital. It has limited hardware on-board, including an
 413           Ethernet interface, two PCMCIA sockets, two serial ports and a
 414           parallel port.
 415
 416 config ARCH_EP93XX
 417         bool "EP93xx-based"
 418         select ARCH_HAS_HOLES_MEMORYMODEL
 419         select ARCH_REQUIRE_GPIOLIB
 420         select ARM_AMBA
 421         select ARM_PATCH_PHYS_VIRT
 422         select ARM_VIC
 423         select AUTO_ZRELADDR
 424         select CLKDEV_LOOKUP
 425         select CLKSRC_MMIO
 426         select CPU_ARM920T
 427         select GENERIC_CLOCKEVENTS
 428         help
 429           This enables support for the Cirrus EP93xx series of CPUs.
 430
 431 config ARCH_FOOTBRIDGE
 432         bool "FootBridge"
 433         select CPU_SA110
 434         select FOOTBRIDGE
 435         select GENERIC_CLOCKEVENTS
 436         select HAVE_IDE
 437         select NEED_MACH_IO_H if !MMU
 438         select NEED_MACH_MEMORY_H
 439         help
 440           Support for systems based on the DC21285 companion chip
 441           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 442
 443 config ARCH_NETX
 444         bool "Hilscher NetX based"
 445         select ARM_VIC
 446         select CLKSRC_MMIO
 447         select CPU_ARM926T
 448         select GENERIC_CLOCKEVENTS
 449         help
 450           This enables support for systems based on the Hilscher NetX Soc
 451
 452 config ARCH_IOP13XX
 453         bool "IOP13xx-based"
 454         depends on MMU
 455         select CPU_XSC3
 456         select NEED_MACH_MEMORY_H
 457         select NEED_RET_TO_USER
 458         select PCI
 459         select PLAT_IOP
 460         select VMSPLIT_1G
 461         select SPARSE_IRQ
 462         help
 463           Support for Intel's IOP13XX (XScale) family of processors.
 464
 465 config ARCH_IOP32X
 466         bool "IOP32x-based"
 467         depends on MMU
 468         select ARCH_REQUIRE_GPIOLIB
 469         select CPU_XSCALE
 470         select GPIO_IOP
 471         select NEED_RET_TO_USER
 472         select PCI
 473         select PLAT_IOP
 474         help
 475           Support for Intel's 80219 and IOP32X (XScale) family of
 476           processors.
 477
 478 config ARCH_IOP33X
 479         bool "IOP33x-based"
 480         depends on MMU
 481         select ARCH_REQUIRE_GPIOLIB
 482         select CPU_XSCALE
 483         select GPIO_IOP
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         help
 488           Support for Intel's IOP33X (XScale) family of processors.
 489
 490 config ARCH_IXP4XX
 491         bool "IXP4xx-based"
 492         depends on MMU
 493         select ARCH_HAS_DMA_SET_COHERENT_MASK
 494         select ARCH_REQUIRE_GPIOLIB
 495         select ARCH_SUPPORTS_BIG_ENDIAN
 496         select CLKSRC_MMIO
 497         select CPU_XSCALE
 498         select DMABOUNCE if PCI
 499         select GENERIC_CLOCKEVENTS
 500         select MIGHT_HAVE_PCI
 501         select NEED_MACH_IO_H
 502         select USB_EHCI_BIG_ENDIAN_DESC
 503         select USB_EHCI_BIG_ENDIAN_MMIO
 504         help
 505           Support for Intel's IXP4XX (XScale) family of processors.
 506
 507 config ARCH_DOVE
 508         bool "Marvell Dove"
 509         select ARCH_REQUIRE_GPIOLIB
 510         select CPU_PJ4
 511         select GENERIC_CLOCKEVENTS
 512         select MIGHT_HAVE_PCI
 513         select MVEBU_MBUS
 514         select PINCTRL
 515         select PINCTRL_DOVE
 516         select PLAT_ORION_LEGACY
 517         help
 518           Support for the Marvell Dove SoC 88AP510
 519
 520 config ARCH_MV78XX0
 521         bool "Marvell MV78xx0"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_FEROCEON
 524         select GENERIC_CLOCKEVENTS
 525         select MVEBU_MBUS
 526         select PCI
 527         select PLAT_ORION_LEGACY
 528         help
 529           Support for the following Marvell MV78xx0 series SoCs:
 530           MV781x0, MV782x0.
 531
 532 config ARCH_ORION5X
 533         bool "Marvell Orion"
 534         depends on MMU
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select MVEBU_MBUS
 539         select PCI
 540         select PLAT_ORION_LEGACY
 541         select MULTI_IRQ_HANDLER
 542         help
 543           Support for the following Marvell Orion 5x series SoCs:
 544           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 545           Orion-2 (5281), Orion-1-90 (6183).
 546
 547 config ARCH_MMP
 548         bool "Marvell PXA168/910/MMP2"
 549         depends on MMU
 550         select ARCH_REQUIRE_GPIOLIB
 551         select CLKDEV_LOOKUP
 552         select GENERIC_ALLOCATOR
 553         select GENERIC_CLOCKEVENTS
 554         select GPIO_PXA
 555         select IRQ_DOMAIN
 556         select MULTI_IRQ_HANDLER
 557         select PINCTRL
 558         select PLAT_PXA
 559         select SPARSE_IRQ
 560         help
 561           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 562
 563 config ARCH_KS8695
 564         bool "Micrel/Kendin KS8695"
 565         select ARCH_REQUIRE_GPIOLIB
 566         select CLKSRC_MMIO
 567         select CPU_ARM922T
 568         select GENERIC_CLOCKEVENTS
 569         select NEED_MACH_MEMORY_H
 570         help
 571           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 572           System-on-Chip devices.
 573
 574 config ARCH_W90X900
 575         bool "Nuvoton W90X900 CPU"
 576         select ARCH_REQUIRE_GPIOLIB
 577         select CLKDEV_LOOKUP
 578         select CLKSRC_MMIO
 579         select CPU_ARM926T
 580         select GENERIC_CLOCKEVENTS
 581         help
 582           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 583           At present, the w90x900 has been renamed nuc900, regarding
 584           the ARM series product line, you can login the following
 585           link address to know more.
 586
 587           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 588                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 589
 590 config ARCH_LPC32XX
 591         bool "NXP LPC32XX"
 592         select ARCH_REQUIRE_GPIOLIB
 593         select ARM_AMBA
 594         select CLKDEV_LOOKUP
 595         select CLKSRC_MMIO
 596         select CPU_ARM926T
 597         select GENERIC_CLOCKEVENTS
 598         select HAVE_IDE
 599         select USE_OF
 600         help
 601           Support for the NXP LPC32XX family of processors
 602
 603 config ARCH_PXA
 604         bool "PXA2xx/PXA3xx-based"
 605         depends on MMU
 606         select ARCH_MTD_XIP
 607         select ARCH_REQUIRE_GPIOLIB
 608         select ARM_CPU_SUSPEND if PM
 609         select AUTO_ZRELADDR
 610         select COMMON_CLK
 611         select CLKDEV_LOOKUP
 612         select CLKSRC_MMIO
 613         select CLKSRC_OF
 614         select GENERIC_CLOCKEVENTS
 615         select GPIO_PXA
 616         select HAVE_IDE
 617         select IRQ_DOMAIN
 618         select MULTI_IRQ_HANDLER
 619         select PLAT_PXA
 620         select SPARSE_IRQ
 621         help
 622           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 623
 624 config ARCH_SHMOBILE_LEGACY
 625         bool "Renesas ARM SoCs (non-multiplatform)"
 626         select ARCH_SHMOBILE
 627         select ARM_PATCH_PHYS_VIRT if MMU
 628         select CLKDEV_LOOKUP
 629         select CPU_V7
 630         select GENERIC_CLOCKEVENTS
 631         select HAVE_ARM_SCU if SMP
 632         select HAVE_ARM_TWD if SMP
 633         select HAVE_SMP
 634         select MIGHT_HAVE_CACHE_L2X0
 635         select MULTI_IRQ_HANDLER
 636         select NO_IOPORT_MAP
 637         select PINCTRL
 638         select PM_GENERIC_DOMAINS if PM
 639         select SH_CLK_CPG
 640         select SPARSE_IRQ
 641         help
 642           Support for Renesas ARM SoC platforms using a non-multiplatform
 643           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 644           and RZ families.
 645
 646 config ARCH_RPC
 647         bool "RiscPC"
 648         depends on MMU
 649         select ARCH_ACORN
 650         select ARCH_MAY_HAVE_PC_FDC
 651         select ARCH_SPARSEMEM_ENABLE
 652         select ARCH_USES_GETTIMEOFFSET
 653         select CPU_SA110
 654         select FIQ
 655         select HAVE_IDE
 656         select HAVE_PATA_PLATFORM
 657         select ISA_DMA_API
 658         select NEED_MACH_IO_H
 659         select NEED_MACH_MEMORY_H
 660         select NO_IOPORT_MAP
 661         select VIRT_TO_BUS
 662         help
 663           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 664           CD-ROM interface, serial and parallel port, and the floppy drive.
 665
 666 config ARCH_SA1100
 667         bool "SA1100-based"
 668         select ARCH_MTD_XIP
 669         select ARCH_REQUIRE_GPIOLIB
 670         select ARCH_SPARSEMEM_ENABLE
 671         select CLKDEV_LOOKUP
 672         select CLKSRC_MMIO
 673         select CPU_FREQ
 674         select CPU_SA1100
 675         select GENERIC_CLOCKEVENTS
 676         select HAVE_IDE
 677         select IRQ_DOMAIN
 678         select ISA
 679         select MULTI_IRQ_HANDLER
 680         select NEED_MACH_MEMORY_H
 681         select SPARSE_IRQ
 682         help
 683           Support for StrongARM 11x0 based boards.
 684
 685 config ARCH_S3C24XX
 686         bool "Samsung S3C24XX SoCs"
 687         select ARCH_REQUIRE_GPIOLIB
 688         select ATAGS
 689         select CLKDEV_LOOKUP
 690         select CLKSRC_SAMSUNG_PWM
 691         select GENERIC_CLOCKEVENTS
 692         select GPIO_SAMSUNG
 693         select HAVE_S3C2410_I2C if I2C
 694         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 695         select HAVE_S3C_RTC if RTC_CLASS
 696         select MULTI_IRQ_HANDLER
 697         select NEED_MACH_IO_H
 698         select SAMSUNG_ATAGS
 699         help
 700           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 701           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 702           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 703           Samsung SMDK2410 development board (and derivatives).
 704
 705 config ARCH_S3C64XX
 706         bool "Samsung S3C64XX"
 707         select ARCH_REQUIRE_GPIOLIB
 708         select ARM_AMBA
 709         select ARM_VIC
 710         select ATAGS
 711         select CLKDEV_LOOKUP
 712         select CLKSRC_SAMSUNG_PWM
 713         select COMMON_CLK_SAMSUNG
 714         select CPU_V6K
 715         select GENERIC_CLOCKEVENTS
 716         select GPIO_SAMSUNG
 717         select HAVE_S3C2410_I2C if I2C
 718         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 719         select HAVE_TCM
 720         select NO_IOPORT_MAP
 721         select PLAT_SAMSUNG
 722         select PM_GENERIC_DOMAINS if PM
 723         select S3C_DEV_NAND
 724         select S3C_GPIO_TRACK
 725         select SAMSUNG_ATAGS
 726         select SAMSUNG_WAKEMASK
 727         select SAMSUNG_WDT_RESET
 728         help
 729           Samsung S3C64XX series based systems
 730
 731 config ARCH_DAVINCI
 732         bool "TI DaVinci"
 733         select ARCH_HAS_HOLES_MEMORYMODEL
 734         select ARCH_REQUIRE_GPIOLIB
 735         select CLKDEV_LOOKUP
 736         select GENERIC_ALLOCATOR
 737         select GENERIC_CLOCKEVENTS
 738         select GENERIC_IRQ_CHIP
 739         select HAVE_IDE
 740         select TI_PRIV_EDMA
 741         select USE_OF
 742         select ZONE_DMA
 743         help
 744           Support for TI's DaVinci platform.
 745
 746 config ARCH_OMAP1
 747         bool "TI OMAP1"
 748         depends on MMU
 749         select ARCH_HAS_HOLES_MEMORYMODEL
 750         select ARCH_OMAP
 751         select ARCH_REQUIRE_GPIOLIB
 752         select CLKDEV_LOOKUP
 753         select CLKSRC_MMIO
 754         select GENERIC_CLOCKEVENTS
 755         select GENERIC_IRQ_CHIP
 756         select HAVE_IDE
 757         select IRQ_DOMAIN
 758         select MULTI_IRQ_HANDLER
 759         select NEED_MACH_IO_H if PCCARD
 760         select NEED_MACH_MEMORY_H
 761         select SPARSE_IRQ
 762         help
 763           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 764
 765 endchoice
 766
 767 menu "Multiple platform selection"
 768         depends on ARCH_MULTIPLATFORM
 769
 770 comment "CPU Core family selection"
 771
 772 config ARCH_MULTI_V4
 773         bool "ARMv4 based platforms (FA526)"
 774         depends on !ARCH_MULTI_V6_V7
 775         select ARCH_MULTI_V4_V5
 776         select CPU_FA526
 777
 778 config ARCH_MULTI_V4T
 779         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 780         depends on !ARCH_MULTI_V6_V7
 781         select ARCH_MULTI_V4_V5
 782         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 783                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 784                 CPU_ARM925T || CPU_ARM940T)
 785
 786 config ARCH_MULTI_V5
 787         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 788         depends on !ARCH_MULTI_V6_V7
 789         select ARCH_MULTI_V4_V5
 790         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 791                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 792                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 793
 794 config ARCH_MULTI_V4_V5
 795         bool
 796
 797 config ARCH_MULTI_V6
 798         bool "ARMv6 based platforms (ARM11)"
 799         select ARCH_MULTI_V6_V7
 800         select CPU_V6K
 801
 802 config ARCH_MULTI_V7
 803         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 804         default y
 805         select ARCH_MULTI_V6_V7
 806         select CPU_V7
 807         select HAVE_SMP
 808
 809 config ARCH_MULTI_V6_V7
 810         bool
 811         select MIGHT_HAVE_CACHE_L2X0
 812
 813 config ARCH_MULTI_CPU_AUTO
 814         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 815         select ARCH_MULTI_V5
 816
 817 endmenu
 818
 819 config ARCH_VIRT
 820         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 821         select ARM_AMBA
 822         select ARM_GIC
 823         select ARM_PSCI
 824         select HAVE_ARM_ARCH_TIMER
 825
 826 #
 827 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 828 # Kconfigs may be included either alphabetically (according to the
 829 # plat- suffix) or along side the corresponding mach-* source.
 830 #
 831 source "arch/arm/mach-mvebu/Kconfig"
 832
 833 source "arch/arm/mach-alpine/Kconfig"
 834
 835 source "arch/arm/mach-asm9260/Kconfig"
 836
 837 source "arch/arm/mach-at91/Kconfig"
 838
 839 source "arch/arm/mach-axxia/Kconfig"
 840
 841 source "arch/arm/mach-bcm/Kconfig"
 842
 843 source "arch/arm/mach-berlin/Kconfig"
 844
 845 source "arch/arm/mach-clps711x/Kconfig"
 846
 847 source "arch/arm/mach-cns3xxx/Kconfig"
 848
 849 source "arch/arm/mach-davinci/Kconfig"
 850
 851 source "arch/arm/mach-digicolor/Kconfig"
 852
 853 source "arch/arm/mach-dove/Kconfig"
 854
 855 source "arch/arm/mach-ep93xx/Kconfig"
 856
 857 source "arch/arm/mach-footbridge/Kconfig"
 858
 859 source "arch/arm/mach-gemini/Kconfig"
 860
 861 source "arch/arm/mach-highbank/Kconfig"
 862
 863 source "arch/arm/mach-hisi/Kconfig"
 864
 865 source "arch/arm/mach-integrator/Kconfig"
 866
 867 source "arch/arm/mach-iop32x/Kconfig"
 868
 869 source "arch/arm/mach-iop33x/Kconfig"
 870
 871 source "arch/arm/mach-iop13xx/Kconfig"
 872
 873 source "arch/arm/mach-ixp4xx/Kconfig"
 874
 875 source "arch/arm/mach-keystone/Kconfig"
 876
 877 source "arch/arm/mach-ks8695/Kconfig"
 878
 879 source "arch/arm/mach-meson/Kconfig"
 880
 881 source "arch/arm/mach-moxart/Kconfig"
 882
 883 source "arch/arm/mach-mv78xx0/Kconfig"
 884
 885 source "arch/arm/mach-imx/Kconfig"
 886
 887 source "arch/arm/mach-mediatek/Kconfig"
 888
 889 source "arch/arm/mach-mxs/Kconfig"
 890
 891 source "arch/arm/mach-netx/Kconfig"
 892
 893 source "arch/arm/mach-nomadik/Kconfig"
 894
 895 source "arch/arm/mach-nspire/Kconfig"
 896
 897 source "arch/arm/plat-omap/Kconfig"
 898
 899 source "arch/arm/mach-omap1/Kconfig"
 900
 901 source "arch/arm/mach-omap2/Kconfig"
 902
 903 source "arch/arm/mach-orion5x/Kconfig"
 904
 905 source "arch/arm/mach-picoxcell/Kconfig"
 906
 907 source "arch/arm/mach-pxa/Kconfig"
 908 source "arch/arm/plat-pxa/Kconfig"
 909
 910 source "arch/arm/mach-mmp/Kconfig"
 911
 912 source "arch/arm/mach-qcom/Kconfig"
 913
 914 source "arch/arm/mach-realview/Kconfig"
 915
 916 source "arch/arm/mach-rockchip/Kconfig"
 917
 918 source "arch/arm/mach-sa1100/Kconfig"
 919
 920 source "arch/arm/mach-socfpga/Kconfig"
 921
 922 source "arch/arm/mach-spear/Kconfig"
 923
 924 source "arch/arm/mach-sti/Kconfig"
 925
 926 source "arch/arm/mach-s3c24xx/Kconfig"
 927
 928 source "arch/arm/mach-s3c64xx/Kconfig"
 929
 930 source "arch/arm/mach-s5pv210/Kconfig"
 931
 932 source "arch/arm/mach-exynos/Kconfig"
 933 source "arch/arm/plat-samsung/Kconfig"
 934
 935 source "arch/arm/mach-shmobile/Kconfig"
 936
 937 source "arch/arm/mach-sunxi/Kconfig"
 938
 939 source "arch/arm/mach-prima2/Kconfig"
 940
 941 source "arch/arm/mach-tegra/Kconfig"
 942
 943 source "arch/arm/mach-u300/Kconfig"
 944
 945 source "arch/arm/mach-uniphier/Kconfig"
 946
 947 source "arch/arm/mach-ux500/Kconfig"
 948
 949 source "arch/arm/mach-versatile/Kconfig"
 950
 951 source "arch/arm/mach-vexpress/Kconfig"
 952 source "arch/arm/plat-versatile/Kconfig"
 953
 954 source "arch/arm/mach-vt8500/Kconfig"
 955
 956 source "arch/arm/mach-w90x900/Kconfig"
 957
 958 source "arch/arm/mach-zx/Kconfig"
 959
 960 source "arch/arm/mach-zynq/Kconfig"
 961
 962 # ARMv7-M architecture
 963 config ARCH_EFM32
 964         bool "Energy Micro efm32"
 965         depends on ARM_SINGLE_ARMV7M
 966         select ARCH_REQUIRE_GPIOLIB
 967         help
 968           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 969           processors.
 970
 971 config ARCH_LPC18XX
 972         bool "NXP LPC18xx/LPC43xx"
 973         depends on ARM_SINGLE_ARMV7M
 974         select ARCH_HAS_RESET_CONTROLLER
 975         select ARM_AMBA
 976         select CLKSRC_LPC32XX
 977         select PINCTRL
 978         help
 979           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 980           high performance microcontrollers.
 981
 982 config ARCH_STM32
 983         bool "STMicrolectronics STM32"
 984         depends on ARM_SINGLE_ARMV7M
 985         select ARCH_HAS_RESET_CONTROLLER
 986         select ARMV7M_SYSTICK
 987         select CLKSRC_STM32
 988         select RESET_CONTROLLER
 989         help
 990           Support for STMicroelectronics STM32 processors.
 991
 992 # Definitions to make life easier
 993 config ARCH_ACORN
 994         bool
 995
 996 config PLAT_IOP
 997         bool
 998         select GENERIC_CLOCKEVENTS
 999
1000 config PLAT_ORION
1001         bool
1002         select CLKSRC_MMIO
1003         select COMMON_CLK
1004         select GENERIC_IRQ_CHIP
1005         select IRQ_DOMAIN
1006
1007 config PLAT_ORION_LEGACY
1008         bool
1009         select PLAT_ORION
1010
1011 config PLAT_PXA
1012         bool
1013
1014 config PLAT_VERSATILE
1015         bool
1016
1017 source "arch/arm/firmware/Kconfig"
1018
1019 source arch/arm/mm/Kconfig
1020
1021 config IWMMXT
1022         bool "Enable iWMMXt support"
1023         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1024         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1025         help
1026           Enable support for iWMMXt context switching at run time if
1027           running on a CPU that supports it.
1028
1029 config MULTI_IRQ_HANDLER
1030         bool
1031         help
1032           Allow each machine to specify it's own IRQ handler at run time.
1033
1034 if !MMU
1035 source "arch/arm/Kconfig-nommu"
1036 endif
1037
1038 config PJ4B_ERRATA_4742
1039         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1040         depends on CPU_PJ4B && MACH_ARMADA_370
1041         default y
1042         help
1043           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1044           Event (WFE) IDLE states, a specific timing sensitivity exists between
1045           the retiring WFI/WFE instructions and the newly issued subsequent
1046           instructions.  This sensitivity can result in a CPU hang scenario.
1047           Workaround:
1048           The software must insert either a Data Synchronization Barrier (DSB)
1049           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1050           instruction
1051
1052 config ARM_ERRATA_326103
1053         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1054         depends on CPU_V6
1055         help
1056           Executing a SWP instruction to read-only memory does not set bit 11
1057           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1058           treat the access as a read, preventing a COW from occurring and
1059           causing the faulting task to livelock.
1060
1061 config ARM_ERRATA_411920
1062         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1063         depends on CPU_V6 || CPU_V6K
1064         help
1065           Invalidation of the Instruction Cache operation can
1066           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1067           It does not affect the MPCore. This option enables the ARM Ltd.
1068           recommended workaround.
1069
1070 config ARM_ERRATA_430973
1071         bool "ARM errata: Stale prediction on replaced interworking branch"
1072         depends on CPU_V7
1073         help
1074           This option enables the workaround for the 430973 Cortex-A8
1075           r1p* erratum. If a code sequence containing an ARM/Thumb
1076           interworking branch is replaced with another code sequence at the
1077           same virtual address, whether due to self-modifying code or virtual
1078           to physical address re-mapping, Cortex-A8 does not recover from the
1079           stale interworking branch prediction. This results in Cortex-A8
1080           executing the new code sequence in the incorrect ARM or Thumb state.
1081           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1082           and also flushes the branch target cache at every context switch.
1083           Note that setting specific bits in the ACTLR register may not be
1084           available in non-secure mode.
1085
1086 config ARM_ERRATA_458693
1087         bool "ARM errata: Processor deadlock when a false hazard is created"
1088         depends on CPU_V7
1089         depends on !ARCH_MULTIPLATFORM
1090         help
1091           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1092           erratum. For very specific sequences of memory operations, it is
1093           possible for a hazard condition intended for a cache line to instead
1094           be incorrectly associated with a different cache line. This false
1095           hazard might then cause a processor deadlock. The workaround enables
1096           the L1 caching of the NEON accesses and disables the PLD instruction
1097           in the ACTLR register. Note that setting specific bits in the ACTLR
1098           register may not be available in non-secure mode.
1099
1100 config ARM_ERRATA_460075
1101         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1102         depends on CPU_V7
1103         depends on !ARCH_MULTIPLATFORM
1104         help
1105           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1106           erratum. Any asynchronous access to the L2 cache may encounter a
1107           situation in which recent store transactions to the L2 cache are lost
1108           and overwritten with stale memory contents from external memory. The
1109           workaround disables the write-allocate mode for the L2 cache via the
1110           ACTLR register. Note that setting specific bits in the ACTLR register
1111           may not be available in non-secure mode.
1112
1113 config ARM_ERRATA_742230
1114         bool "ARM errata: DMB operation may be faulty"
1115         depends on CPU_V7 && SMP
1116         depends on !ARCH_MULTIPLATFORM
1117         help
1118           This option enables the workaround for the 742230 Cortex-A9
1119           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1120           between two write operations may not ensure the correct visibility
1121           ordering of the two writes. This workaround sets a specific bit in
1122           the diagnostic register of the Cortex-A9 which causes the DMB
1123           instruction to behave as a DSB, ensuring the correct behaviour of
1124           the two writes.
1125
1126 config ARM_ERRATA_742231
1127         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1128         depends on CPU_V7 && SMP
1129         depends on !ARCH_MULTIPLATFORM
1130         help
1131           This option enables the workaround for the 742231 Cortex-A9
1132           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1133           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1134           accessing some data located in the same cache line, may get corrupted
1135           data due to bad handling of the address hazard when the line gets
1136           replaced from one of the CPUs at the same time as another CPU is
1137           accessing it. This workaround sets specific bits in the diagnostic
1138           register of the Cortex-A9 which reduces the linefill issuing
1139           capabilities of the processor.
1140
1141 config ARM_ERRATA_643719
1142         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1143         depends on CPU_V7 && SMP
1144         default y
1145         help
1146           This option enables the workaround for the 643719 Cortex-A9 (prior to
1147           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1148           register returns zero when it should return one. The workaround
1149           corrects this value, ensuring cache maintenance operations which use
1150           it behave as intended and avoiding data corruption.
1151
1152 config ARM_ERRATA_720789
1153         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1154         depends on CPU_V7
1155         help
1156           This option enables the workaround for the 720789 Cortex-A9 (prior to
1157           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1158           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1159           As a consequence of this erratum, some TLB entries which should be
1160           invalidated are not, resulting in an incoherency in the system page
1161           tables. The workaround changes the TLB flushing routines to invalidate
1162           entries regardless of the ASID.
1163
1164 config ARM_ERRATA_743622
1165         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1166         depends on CPU_V7
1167         depends on !ARCH_MULTIPLATFORM
1168         help
1169           This option enables the workaround for the 743622 Cortex-A9
1170           (r2p*) erratum. Under very rare conditions, a faulty
1171           optimisation in the Cortex-A9 Store Buffer may lead to data
1172           corruption. This workaround sets a specific bit in the diagnostic
1173           register of the Cortex-A9 which disables the Store Buffer
1174           optimisation, preventing the defect from occurring. This has no
1175           visible impact on the overall performance or power consumption of the
1176           processor.
1177
1178 config ARM_ERRATA_751472
1179         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1180         depends on CPU_V7
1181         depends on !ARCH_MULTIPLATFORM
1182         help
1183           This option enables the workaround for the 751472 Cortex-A9 (prior
1184           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1185           completion of a following broadcasted operation if the second
1186           operation is received by a CPU before the ICIALLUIS has completed,
1187           potentially leading to corrupted entries in the cache or TLB.
1188
1189 config ARM_ERRATA_754322
1190         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1191         depends on CPU_V7
1192         help
1193           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1194           r3p*) erratum. A speculative memory access may cause a page table walk
1195           which starts prior to an ASID switch but completes afterwards. This
1196           can populate the micro-TLB with a stale entry which may be hit with
1197           the new ASID. This workaround places two dsb instructions in the mm
1198           switching code so that no page table walks can cross the ASID switch.
1199
1200 config ARM_ERRATA_754327
1201         bool "ARM errata: no automatic Store Buffer drain"
1202         depends on CPU_V7 && SMP
1203         help
1204           This option enables the workaround for the 754327 Cortex-A9 (prior to
1205           r2p0) erratum. The Store Buffer does not have any automatic draining
1206           mechanism and therefore a livelock may occur if an external agent
1207           continuously polls a memory location waiting to observe an update.
1208           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1209           written polling loops from denying visibility of updates to memory.
1210
1211 config ARM_ERRATA_364296
1212         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1213         depends on CPU_V6
1214         help
1215           This options enables the workaround for the 364296 ARM1136
1216           r0p2 erratum (possible cache data corruption with
1217           hit-under-miss enabled). It sets the undocumented bit 31 in
1218           the auxiliary control register and the FI bit in the control
1219           register, thus disabling hit-under-miss without putting the
1220           processor into full low interrupt latency mode. ARM11MPCore
1221           is not affected.
1222
1223 config ARM_ERRATA_764369
1224         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1225         depends on CPU_V7 && SMP
1226         help
1227           This option enables the workaround for erratum 764369
1228           affecting Cortex-A9 MPCore with two or more processors (all
1229           current revisions). Under certain timing circumstances, a data
1230           cache line maintenance operation by MVA targeting an Inner
1231           Shareable memory region may fail to proceed up to either the
1232           Point of Coherency or to the Point of Unification of the
1233           system. This workaround adds a DSB instruction before the
1234           relevant cache maintenance functions and sets a specific bit
1235           in the diagnostic control register of the SCU.
1236
1237 config ARM_ERRATA_775420
1238        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1239        depends on CPU_V7
1240        help
1241          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1242          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1243          operation aborts with MMU exception, it might cause the processor
1244          to deadlock. This workaround puts DSB before executing ISB if
1245          an abort may occur on cache maintenance.
1246
1247 config ARM_ERRATA_798181
1248         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1249         depends on CPU_V7 && SMP
1250         help
1251           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1252           adequately shooting down all use of the old entries. This
1253           option enables the Linux kernel workaround for this erratum
1254           which sends an IPI to the CPUs that are running the same ASID
1255           as the one being invalidated.
1256
1257 config ARM_ERRATA_773022
1258         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1259         depends on CPU_V7
1260         help
1261           This option enables the workaround for the 773022 Cortex-A15
1262           (up to r0p4) erratum. In certain rare sequences of code, the
1263           loop buffer may deliver incorrect instructions. This
1264           workaround disables the loop buffer to avoid the erratum.
1265
1266 endmenu
1267
1268 source "arch/arm/common/Kconfig"
1269
1270 menu "Bus support"
1271
1272 config ISA
1273         bool
1274         help
1275           Find out whether you have ISA slots on your motherboard.  ISA is the
1276           name of a bus system, i.e. the way the CPU talks to the other stuff
1277           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1278           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1279           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1280
1281 # Select ISA DMA controller support
1282 config ISA_DMA
1283         bool
1284         select ISA_DMA_API
1285
1286 # Select ISA DMA interface
1287 config ISA_DMA_API
1288         bool
1289
1290 config PCI
1291         bool "PCI support" if MIGHT_HAVE_PCI
1292         help
1293           Find out whether you have a PCI motherboard. PCI is the name of a
1294           bus system, i.e. the way the CPU talks to the other stuff inside
1295           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1296           VESA. If you have PCI, say Y, otherwise N.
1297
1298 config PCI_DOMAINS
1299         bool
1300         depends on PCI
1301
1302 config PCI_DOMAINS_GENERIC
1303         def_bool PCI_DOMAINS
1304
1305 config PCI_NANOENGINE
1306         bool "BSE nanoEngine PCI support"
1307         depends on SA1100_NANOENGINE
1308         help
1309           Enable PCI on the BSE nanoEngine board.
1310
1311 config PCI_SYSCALL
1312         def_bool PCI
1313
1314 config PCI_HOST_ITE8152
1315         bool
1316         depends on PCI && MACH_ARMCORE
1317         default y
1318         select DMABOUNCE
1319
1320 source "drivers/pci/Kconfig"
1321 source "drivers/pci/pcie/Kconfig"
1322
1323 source "drivers/pcmcia/Kconfig"
1324
1325 endmenu
1326
1327 menu "Kernel Features"
1328
1329 config HAVE_SMP
1330         bool
1331         help
1332           This option should be selected by machines which have an SMP-
1333           capable CPU.
1334
1335           The only effect of this option is to make the SMP-related
1336           options available to the user for configuration.
1337
1338 config SMP
1339         bool "Symmetric Multi-Processing"
1340         depends on CPU_V6K || CPU_V7
1341         depends on GENERIC_CLOCKEVENTS
1342         depends on HAVE_SMP
1343         depends on MMU || ARM_MPU
1344         select IRQ_WORK
1345         help
1346           This enables support for systems with more than one CPU. If you have
1347           a system with only one CPU, say N. If you have a system with more
1348           than one CPU, say Y.
1349
1350           If you say N here, the kernel will run on uni- and multiprocessor
1351           machines, but will use only one CPU of a multiprocessor machine. If
1352           you say Y here, the kernel will run on many, but not all,
1353           uniprocessor machines. On a uniprocessor machine, the kernel
1354           will run faster if you say N here.
1355
1356           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1357           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1358           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1359
1360           If you don't know what to do here, say N.
1361
1362 config SMP_ON_UP
1363         bool "Allow booting SMP kernel on uniprocessor systems"
1364         depends on SMP && !XIP_KERNEL && MMU
1365         default y
1366         help
1367           SMP kernels contain instructions which fail on non-SMP processors.
1368           Enabling this option allows the kernel to modify itself to make
1369           these instructions safe.  Disabling it allows about 1K of space
1370           savings.
1371
1372           If you don't know what to do here, say Y.
1373
1374 config ARM_CPU_TOPOLOGY
1375         bool "Support cpu topology definition"
1376         depends on SMP && CPU_V7
1377         default y
1378         help
1379           Support ARM cpu topology definition. The MPIDR register defines
1380           affinity between processors which is then used to describe the cpu
1381           topology of an ARM System.
1382
1383 config SCHED_MC
1384         bool "Multi-core scheduler support"
1385         depends on ARM_CPU_TOPOLOGY
1386         help
1387           Multi-core scheduler support improves the CPU scheduler's decision
1388           making when dealing with multi-core CPU chips at a cost of slightly
1389           increased overhead in some places. If unsure say N here.
1390
1391 config SCHED_SMT
1392         bool "SMT scheduler support"
1393         depends on ARM_CPU_TOPOLOGY
1394         help
1395           Improves the CPU scheduler's decision making when dealing with
1396           MultiThreading at a cost of slightly increased overhead in some
1397           places. If unsure say N here.
1398
1399 config HAVE_ARM_SCU
1400         bool
1401         help
1402           This option enables support for the ARM system coherency unit
1403
1404 config HAVE_ARM_ARCH_TIMER
1405         bool "Architected timer support"
1406         depends on CPU_V7
1407         select ARM_ARCH_TIMER
1408         select GENERIC_CLOCKEVENTS
1409         help
1410           This option enables support for the ARM architected timer
1411
1412 config HAVE_ARM_TWD
1413         bool
1414         depends on SMP
1415         select CLKSRC_OF if OF
1416         help
1417           This options enables support for the ARM timer and watchdog unit
1418
1419 config MCPM
1420         bool "Multi-Cluster Power Management"
1421         depends on CPU_V7 && SMP
1422         help
1423           This option provides the common power management infrastructure
1424           for (multi-)cluster based systems, such as big.LITTLE based
1425           systems.
1426
1427 config MCPM_QUAD_CLUSTER
1428         bool
1429         depends on MCPM
1430         help
1431           To avoid wasting resources unnecessarily, MCPM only supports up
1432           to 2 clusters by default.
1433           Platforms with 3 or 4 clusters that use MCPM must select this
1434           option to allow the additional clusters to be managed.
1435
1436 config BIG_LITTLE
1437         bool "big.LITTLE support (Experimental)"
1438         depends on CPU_V7 && SMP
1439         select MCPM
1440         help
1441           This option enables support selections for the big.LITTLE
1442           system architecture.
1443
1444 config BL_SWITCHER
1445         bool "big.LITTLE switcher support"
1446         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1447         select ARM_CPU_SUSPEND
1448         select CPU_PM
1449         help
1450           The big.LITTLE "switcher" provides the core functionality to
1451           transparently handle transition between a cluster of A15's
1452           and a cluster of A7's in a big.LITTLE system.
1453
1454 config BL_SWITCHER_DUMMY_IF
1455         tristate "Simple big.LITTLE switcher user interface"
1456         depends on BL_SWITCHER && DEBUG_KERNEL
1457         help
1458           This is a simple and dummy char dev interface to control
1459           the big.LITTLE switcher core code.  It is meant for
1460           debugging purposes only.
1461
1462 choice
1463         prompt "Memory split"
1464         depends on MMU
1465         default VMSPLIT_3G
1466         help
1467           Select the desired split between kernel and user memory.
1468
1469           If you are not absolutely sure what you are doing, leave this
1470           option alone!
1471
1472         config VMSPLIT_3G
1473                 bool "3G/1G user/kernel split"
1474         config VMSPLIT_2G
1475                 bool "2G/2G user/kernel split"
1476         config VMSPLIT_1G
1477                 bool "1G/3G user/kernel split"
1478 endchoice
1479
1480 config PAGE_OFFSET
1481         hex
1482         default PHYS_OFFSET if !MMU
1483         default 0x40000000 if VMSPLIT_1G
1484         default 0x80000000 if VMSPLIT_2G
1485         default 0xC0000000
1486
1487 config NR_CPUS
1488         int "Maximum number of CPUs (2-32)"
1489         range 2 32
1490         depends on SMP
1491         default "4"
1492
1493 config HOTPLUG_CPU
1494         bool "Support for hot-pluggable CPUs"
1495         depends on SMP
1496         help
1497           Say Y here to experiment with turning CPUs off and on.  CPUs
1498           can be controlled through /sys/devices/system/cpu.
1499
1500 config ARM_PSCI
1501         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1502         depends on CPU_V7
1503         select ARM_PSCI_FW
1504         help
1505           Say Y here if you want Linux to communicate with system firmware
1506           implementing the PSCI specification for CPU-centric power
1507           management operations described in ARM document number ARM DEN
1508           0022A ("Power State Coordination Interface System Software on
1509           ARM processors").
1510
1511 # The GPIO number here must be sorted by descending number. In case of
1512 # a multiplatform kernel, we just want the highest value required by the
1513 # selected platforms.
1514 config ARCH_NR_GPIO
1515         int
1516         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1517                 ARCH_ZYNQ
1518         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1519                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1520         default 416 if ARCH_SUNXI
1521         default 392 if ARCH_U8500
1522         default 352 if ARCH_VT8500
1523         default 288 if ARCH_ROCKCHIP
1524         default 264 if MACH_H4700
1525         default 0
1526         help
1527           Maximum number of GPIOs in the system.
1528
1529           If unsure, leave the default value.
1530
1531 source kernel/Kconfig.preempt
1532
1533 config HZ_FIXED
1534         int
1535         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1536                 ARCH_S5PV210 || ARCH_EXYNOS4
1537         default 128 if SOC_AT91RM9200
1538         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1539         default 0
1540
1541 choice
1542         depends on HZ_FIXED = 0
1543         prompt "Timer frequency"
1544
1545 config HZ_100
1546         bool "100 Hz"
1547
1548 config HZ_200
1549         bool "200 Hz"
1550
1551 config HZ_250
1552         bool "250 Hz"
1553
1554 config HZ_300
1555         bool "300 Hz"
1556
1557 config HZ_500
1558         bool "500 Hz"
1559
1560 config HZ_1000
1561         bool "1000 Hz"
1562
1563 endchoice
1564
1565 config HZ
1566         int
1567         default HZ_FIXED if HZ_FIXED != 0
1568         default 100 if HZ_100
1569         default 200 if HZ_200
1570         default 250 if HZ_250
1571         default 300 if HZ_300
1572         default 500 if HZ_500
1573         default 1000
1574
1575 config SCHED_HRTICK
1576         def_bool HIGH_RES_TIMERS
1577
1578 config THUMB2_KERNEL
1579         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1580         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1581         default y if CPU_THUMBONLY
1582         select AEABI
1583         select ARM_ASM_UNIFIED
1584         select ARM_UNWIND
1585         help
1586           By enabling this option, the kernel will be compiled in
1587           Thumb-2 mode. A compiler/assembler that understand the unified
1588           ARM-Thumb syntax is needed.
1589
1590           If unsure, say N.
1591
1592 config THUMB2_AVOID_R_ARM_THM_JUMP11
1593         bool "Work around buggy Thumb-2 short branch relocations in gas"
1594         depends on THUMB2_KERNEL && MODULES
1595         default y
1596         help
1597           Various binutils versions can resolve Thumb-2 branches to
1598           locally-defined, preemptible global symbols as short-range "b.n"
1599           branch instructions.
1600
1601           This is a problem, because there's no guarantee the final
1602           destination of the symbol, or any candidate locations for a
1603           trampoline, are within range of the branch.  For this reason, the
1604           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1605           relocation in modules at all, and it makes little sense to add
1606           support.
1607
1608           The symptom is that the kernel fails with an "unsupported
1609           relocation" error when loading some modules.
1610
1611           Until fixed tools are available, passing
1612           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1613           code which hits this problem, at the cost of a bit of extra runtime
1614           stack usage in some cases.
1615
1616           The problem is described in more detail at:
1617               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1618
1619           Only Thumb-2 kernels are affected.
1620
1621           Unless you are sure your tools don't have this problem, say Y.
1622
1623 config ARM_ASM_UNIFIED
1624         bool
1625
1626 config AEABI
1627         bool "Use the ARM EABI to compile the kernel"
1628         help
1629           This option allows for the kernel to be compiled using the latest
1630           ARM ABI (aka EABI).  This is only useful if you are using a user
1631           space environment that is also compiled with EABI.
1632
1633           Since there are major incompatibilities between the legacy ABI and
1634           EABI, especially with regard to structure member alignment, this
1635           option also changes the kernel syscall calling convention to
1636           disambiguate both ABIs and allow for backward compatibility support
1637           (selected with CONFIG_OABI_COMPAT).
1638
1639           To use this you need GCC version 4.0.0 or later.
1640
1641 config OABI_COMPAT
1642         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1643         depends on AEABI && !THUMB2_KERNEL
1644         help
1645           This option preserves the old syscall interface along with the
1646           new (ARM EABI) one. It also provides a compatibility layer to
1647           intercept syscalls that have structure arguments which layout
1648           in memory differs between the legacy ABI and the new ARM EABI
1649           (only for non "thumb" binaries). This option adds a tiny
1650           overhead to all syscalls and produces a slightly larger kernel.
1651
1652           The seccomp filter system will not be available when this is
1653           selected, since there is no way yet to sensibly distinguish
1654           between calling conventions during filtering.
1655
1656           If you know you'll be using only pure EABI user space then you
1657           can say N here. If this option is not selected and you attempt
1658           to execute a legacy ABI binary then the result will be
1659           UNPREDICTABLE (in fact it can be predicted that it won't work
1660           at all). If in doubt say N.
1661
1662 config ARCH_HAS_HOLES_MEMORYMODEL
1663         bool
1664
1665 config ARCH_SPARSEMEM_ENABLE
1666         bool
1667
1668 config ARCH_SPARSEMEM_DEFAULT
1669         def_bool ARCH_SPARSEMEM_ENABLE
1670
1671 config ARCH_SELECT_MEMORY_MODEL
1672         def_bool ARCH_SPARSEMEM_ENABLE
1673
1674 config HAVE_ARCH_PFN_VALID
1675         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1676
1677 config HAVE_GENERIC_RCU_GUP
1678         def_bool y
1679         depends on ARM_LPAE
1680
1681 config HIGHMEM
1682         bool "High Memory Support"
1683         depends on MMU
1684         help
1685           The address space of ARM processors is only 4 Gigabytes large
1686           and it has to accommodate user address space, kernel address
1687           space as well as some memory mapped IO. That means that, if you
1688           have a large amount of physical memory and/or IO, not all of the
1689           memory can be "permanently mapped" by the kernel. The physical
1690           memory that is not permanently mapped is called "high memory".
1691
1692           Depending on the selected kernel/user memory split, minimum
1693           vmalloc space and actual amount of RAM, you may not need this
1694           option which should result in a slightly faster kernel.
1695
1696           If unsure, say n.
1697
1698 config HIGHPTE
1699         bool "Allocate 2nd-level pagetables from highmem"
1700         depends on HIGHMEM
1701         help
1702           The VM uses one page of physical memory for each page table.
1703           For systems with a lot of processes, this can use a lot of
1704           precious low memory, eventually leading to low memory being
1705           consumed by page tables.  Setting this option will allow
1706           user-space 2nd level page tables to reside in high memory.
1707
1708 config CPU_SW_DOMAIN_PAN
1709         bool "Enable use of CPU domains to implement privileged no-access"
1710         depends on MMU && !ARM_LPAE
1711         default y
1712         help
1713           Increase kernel security by ensuring that normal kernel accesses
1714           are unable to access userspace addresses.  This can help prevent
1715           use-after-free bugs becoming an exploitable privilege escalation
1716           by ensuring that magic values (such as LIST_POISON) will always
1717           fault when dereferenced.
1718
1719           CPUs with low-vector mappings use a best-efforts implementation.
1720           Their lower 1MB needs to remain accessible for the vectors, but
1721           the remainder of userspace will become appropriately inaccessible.
1722
1723 config HW_PERF_EVENTS
1724         def_bool y
1725         depends on ARM_PMU
1726
1727 config SYS_SUPPORTS_HUGETLBFS
1728        def_bool y
1729        depends on ARM_LPAE
1730
1731 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1732        def_bool y
1733        depends on ARM_LPAE
1734
1735 config ARCH_WANT_GENERAL_HUGETLB
1736         def_bool y
1737
1738 config ARM_MODULE_PLTS
1739         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1740         depends on MODULES
1741         help
1742           Allocate PLTs when loading modules so that jumps and calls whose
1743           targets are too far away for their relative offsets to be encoded
1744           in the instructions themselves can be bounced via veneers in the
1745           module's PLT. This allows modules to be allocated in the generic
1746           vmalloc area after the dedicated module memory area has been
1747           exhausted. The modules will use slightly more memory, but after
1748           rounding up to page size, the actual memory footprint is usually
1749           the same.
1750
1751           Say y if you are getting out of memory errors while loading modules
1752
1753 source "mm/Kconfig"
1754
1755 config FORCE_MAX_ZONEORDER
1756         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1757         range 11 64 if ARCH_SHMOBILE_LEGACY
1758         default "12" if SOC_AM33XX
1759         default "9" if SA1111 || ARCH_EFM32
1760         default "11"
1761         help
1762           The kernel memory allocator divides physically contiguous memory
1763           blocks into "zones", where each zone is a power of two number of
1764           pages.  This option selects the largest power of two that the kernel
1765           keeps in the memory allocator.  If you need to allocate very large
1766           blocks of physically contiguous memory, then you may need to
1767           increase this value.
1768
1769           This config option is actually maximum order plus one. For example,
1770           a value of 11 means that the largest free memory block is 2^10 pages.
1771
1772 config ALIGNMENT_TRAP
1773         bool
1774         depends on CPU_CP15_MMU
1775         default y if !ARCH_EBSA110
1776         select HAVE_PROC_CPU if PROC_FS
1777         help
1778           ARM processors cannot fetch/store information which is not
1779           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1780           address divisible by 4. On 32-bit ARM processors, these non-aligned
1781           fetch/store instructions will be emulated in software if you say
1782           here, which has a severe performance impact. This is necessary for
1783           correct operation of some network protocols. With an IP-only
1784           configuration it is safe to say N, otherwise say Y.
1785
1786 config UACCESS_WITH_MEMCPY
1787         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1788         depends on MMU
1789         default y if CPU_FEROCEON
1790         help
1791           Implement faster copy_to_user and clear_user methods for CPU
1792           cores where a 8-word STM instruction give significantly higher
1793           memory write throughput than a sequence of individual 32bit stores.
1794
1795           A possible side effect is a slight increase in scheduling latency
1796           between threads sharing the same address space if they invoke
1797           such copy operations with large buffers.
1798
1799           However, if the CPU data cache is using a write-allocate mode,
1800           this option is unlikely to provide any performance gain.
1801
1802 config SECCOMP
1803         bool
1804         prompt "Enable seccomp to safely compute untrusted bytecode"
1805         ---help---
1806           This kernel feature is useful for number crunching applications
1807           that may need to compute untrusted bytecode during their
1808           execution. By using pipes or other transports made available to
1809           the process as file descriptors supporting the read/write
1810           syscalls, it's possible to isolate those applications in
1811           their own address space using seccomp. Once seccomp is
1812           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1813           and the task is only allowed to execute a few safe syscalls
1814           defined by each seccomp mode.
1815
1816 config SWIOTLB
1817         def_bool y
1818
1819 config IOMMU_HELPER
1820         def_bool SWIOTLB
1821
1822 config XEN_DOM0
1823         def_bool y
1824         depends on XEN
1825
1826 config XEN
1827         bool "Xen guest support on ARM"
1828         depends on ARM && AEABI && OF
1829         depends on CPU_V7 && !CPU_V6
1830         depends on !GENERIC_ATOMIC64
1831         depends on MMU
1832         select ARCH_DMA_ADDR_T_64BIT
1833         select ARM_PSCI
1834         select SWIOTLB_XEN
1835         help
1836           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1837
1838 endmenu
1839
1840 menu "Boot options"
1841
1842 config USE_OF
1843         bool "Flattened Device Tree support"
1844         select IRQ_DOMAIN
1845         select OF
1846         select OF_EARLY_FLATTREE
1847         select OF_RESERVED_MEM
1848         help
1849           Include support for flattened device tree machine descriptions.
1850
1851 config ATAGS
1852         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1853         default y
1854         help
1855           This is the traditional way of passing data to the kernel at boot
1856           time. If you are solely relying on the flattened device tree (or
1857           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1858           to remove ATAGS support from your kernel binary.  If unsure,
1859           leave this to y.
1860
1861 config DEPRECATED_PARAM_STRUCT
1862         bool "Provide old way to pass kernel parameters"
1863         depends on ATAGS
1864         help
1865           This was deprecated in 2001 and announced to live on for 5 years.
1866           Some old boot loaders still use this way.
1867
1868 # Compressed boot loader in ROM.  Yes, we really want to ask about
1869 # TEXT and BSS so we preserve their values in the config files.
1870 config ZBOOT_ROM_TEXT
1871         hex "Compressed ROM boot loader base address"
1872         default "0"
1873         help
1874           The physical address at which the ROM-able zImage is to be
1875           placed in the target.  Platforms which normally make use of
1876           ROM-able zImage formats normally set this to a suitable
1877           value in their defconfig file.
1878
1879           If ZBOOT_ROM is not enabled, this has no effect.
1880
1881 config ZBOOT_ROM_BSS
1882         hex "Compressed ROM boot loader BSS address"
1883         default "0"
1884         help
1885           The base address of an area of read/write memory in the target
1886           for the ROM-able zImage which must be available while the
1887           decompressor is running. It must be large enough to hold the
1888           entire decompressed kernel plus an additional 128 KiB.
1889           Platforms which normally make use of ROM-able zImage formats
1890           normally set this to a suitable value in their defconfig file.
1891
1892           If ZBOOT_ROM is not enabled, this has no effect.
1893
1894 config ZBOOT_ROM
1895         bool "Compressed boot loader in ROM/flash"
1896         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1897         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1898         help
1899           Say Y here if you intend to execute your compressed kernel image
1900           (zImage) directly from ROM or flash.  If unsure, say N.
1901
1902 config ARM_APPENDED_DTB
1903         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1904         depends on OF
1905         help
1906           With this option, the boot code will look for a device tree binary
1907           (DTB) appended to zImage
1908           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1909
1910           This is meant as a backward compatibility convenience for those
1911           systems with a bootloader that can't be upgraded to accommodate
1912           the documented boot protocol using a device tree.
1913
1914           Beware that there is very little in terms of protection against
1915           this option being confused by leftover garbage in memory that might
1916           look like a DTB header after a reboot if no actual DTB is appended
1917           to zImage.  Do not leave this option active in a production kernel
1918           if you don't intend to always append a DTB.  Proper passing of the
1919           location into r2 of a bootloader provided DTB is always preferable
1920           to this option.
1921
1922 config ARM_ATAG_DTB_COMPAT
1923         bool "Supplement the appended DTB with traditional ATAG information"
1924         depends on ARM_APPENDED_DTB
1925         help
1926           Some old bootloaders can't be updated to a DTB capable one, yet
1927           they provide ATAGs with memory configuration, the ramdisk address,
1928           the kernel cmdline string, etc.  Such information is dynamically
1929           provided by the bootloader and can't always be stored in a static
1930           DTB.  To allow a device tree enabled kernel to be used with such
1931           bootloaders, this option allows zImage to extract the information
1932           from the ATAG list and store it at run time into the appended DTB.
1933
1934 choice
1935         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1936         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1937
1938 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1939         bool "Use bootloader kernel arguments if available"
1940         help
1941           Uses the command-line options passed by the boot loader instead of
1942           the device tree bootargs property. If the boot loader doesn't provide
1943           any, the device tree bootargs property will be used.
1944
1945 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1946         bool "Extend with bootloader kernel arguments"
1947         help
1948           The command-line arguments provided by the boot loader will be
1949           appended to the the device tree bootargs property.
1950
1951 endchoice
1952
1953 config CMDLINE
1954         string "Default kernel command string"
1955         default ""
1956         help
1957           On some architectures (EBSA110 and CATS), there is currently no way
1958           for the boot loader to pass arguments to the kernel. For these
1959           architectures, you should supply some command-line options at build
1960           time by entering them here. As a minimum, you should specify the
1961           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1962
1963 choice
1964         prompt "Kernel command line type" if CMDLINE != ""
1965         default CMDLINE_FROM_BOOTLOADER
1966         depends on ATAGS
1967
1968 config CMDLINE_FROM_BOOTLOADER
1969         bool "Use bootloader kernel arguments if available"
1970         help
1971           Uses the command-line options passed by the boot loader. If
1972           the boot loader doesn't provide any, the default kernel command
1973           string provided in CMDLINE will be used.
1974
1975 config CMDLINE_EXTEND
1976         bool "Extend bootloader kernel arguments"
1977         help
1978           The command-line arguments provided by the boot loader will be
1979           appended to the default kernel command string.
1980
1981 config CMDLINE_FORCE
1982         bool "Always use the default kernel command string"
1983         help
1984           Always use the default kernel command string, even if the boot
1985           loader passes other arguments to the kernel.
1986           This is useful if you cannot or don't want to change the
1987           command-line options your boot loader passes to the kernel.
1988 endchoice
1989
1990 config XIP_KERNEL
1991         bool "Kernel Execute-In-Place from ROM"
1992         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1993         help
1994           Execute-In-Place allows the kernel to run from non-volatile storage
1995           directly addressable by the CPU, such as NOR flash. This saves RAM
1996           space since the text section of the kernel is not loaded from flash
1997           to RAM.  Read-write sections, such as the data section and stack,
1998           are still copied to RAM.  The XIP kernel is not compressed since
1999           it has to run directly from flash, so it will take more space to
2000           store it.  The flash address used to link the kernel object files,
2001           and for storing it, is configuration dependent. Therefore, if you
2002           say Y here, you must know the proper physical address where to
2003           store the kernel image depending on your own flash memory usage.
2004
2005           Also note that the make target becomes "make xipImage" rather than
2006           "make zImage" or "make Image".  The final kernel binary to put in
2007           ROM memory will be arch/arm/boot/xipImage.
2008
2009           If unsure, say N.
2010
2011 config XIP_PHYS_ADDR
2012         hex "XIP Kernel Physical Location"
2013         depends on XIP_KERNEL
2014         default "0x00080000"
2015         help
2016           This is the physical address in your flash memory the kernel will
2017           be linked for and stored to.  This address is dependent on your
2018           own flash usage.
2019
2020 config KEXEC
2021         bool "Kexec system call (EXPERIMENTAL)"
2022         depends on (!SMP || PM_SLEEP_SMP)
2023         depends on !CPU_V7M
2024         select KEXEC_CORE
2025         help
2026           kexec is a system call that implements the ability to shutdown your
2027           current kernel, and to start another kernel.  It is like a reboot
2028           but it is independent of the system firmware.   And like a reboot
2029           you can start any kernel with it, not just Linux.
2030
2031           It is an ongoing process to be certain the hardware in a machine
2032           is properly shutdown, so do not be surprised if this code does not
2033           initially work for you.
2034
2035 config ATAGS_PROC
2036         bool "Export atags in procfs"
2037         depends on ATAGS && KEXEC
2038         default y
2039         help
2040           Should the atags used to boot the kernel be exported in an "atags"
2041           file in procfs. Useful with kexec.
2042
2043 config CRASH_DUMP
2044         bool "Build kdump crash kernel (EXPERIMENTAL)"
2045         help
2046           Generate crash dump after being started by kexec. This should
2047           be normally only set in special crash dump kernels which are
2048           loaded in the main kernel with kexec-tools into a specially
2049           reserved region and then later executed after a crash by
2050           kdump/kexec. The crash dump kernel must be compiled to a
2051           memory address not used by the main kernel
2052
2053           For more details see Documentation/kdump/kdump.txt
2054
2055 config AUTO_ZRELADDR
2056         bool "Auto calculation of the decompressed kernel image address"
2057         help
2058           ZRELADDR is the physical address where the decompressed kernel
2059           image will be placed. If AUTO_ZRELADDR is selected, the address
2060           will be determined at run-time by masking the current IP with
2061           0xf8000000. This assumes the zImage being placed in the first 128MB
2062           from start of memory.
2063
2064 endmenu
2065
2066 menu "CPU Power Management"
2067
2068 source "drivers/cpufreq/Kconfig"
2069
2070 source "drivers/cpuidle/Kconfig"
2071
2072 endmenu
2073
2074 menu "Floating point emulation"
2075
2076 comment "At least one emulation must be selected"
2077
2078 config FPE_NWFPE
2079         bool "NWFPE math emulation"
2080         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2081         ---help---
2082           Say Y to include the NWFPE floating point emulator in the kernel.
2083           This is necessary to run most binaries. Linux does not currently
2084           support floating point hardware so you need to say Y here even if
2085           your machine has an FPA or floating point co-processor podule.
2086
2087           You may say N here if you are going to load the Acorn FPEmulator
2088           early in the bootup.
2089
2090 config FPE_NWFPE_XP
2091         bool "Support extended precision"
2092         depends on FPE_NWFPE
2093         help
2094           Say Y to include 80-bit support in the kernel floating-point
2095           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2096           Note that gcc does not generate 80-bit operations by default,
2097           so in most cases this option only enlarges the size of the
2098           floating point emulator without any good reason.
2099
2100           You almost surely want to say N here.
2101
2102 config FPE_FASTFPE
2103         bool "FastFPE math emulation (EXPERIMENTAL)"
2104         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2105         ---help---
2106           Say Y here to include the FAST floating point emulator in the kernel.
2107           This is an experimental much faster emulator which now also has full
2108           precision for the mantissa.  It does not support any exceptions.
2109           It is very simple, and approximately 3-6 times faster than NWFPE.
2110
2111           It should be sufficient for most programs.  It may be not suitable
2112           for scientific calculations, but you have to check this for yourself.
2113           If you do not feel you need a faster FP emulation you should better
2114           choose NWFPE.
2115
2116 config VFP
2117         bool "VFP-format floating point maths"
2118         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2119         help
2120           Say Y to include VFP support code in the kernel. This is needed
2121           if your hardware includes a VFP unit.
2122
2123           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2124           release notes and additional status information.
2125
2126           Say N if your target does not have VFP hardware.
2127
2128 config VFPv3
2129         bool
2130         depends on VFP
2131         default y if CPU_V7
2132
2133 config NEON
2134         bool "Advanced SIMD (NEON) Extension support"
2135         depends on VFPv3 && CPU_V7
2136         help
2137           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2138           Extension.
2139
2140 config KERNEL_MODE_NEON
2141         bool "Support for NEON in kernel mode"
2142         depends on NEON && AEABI
2143         help
2144           Say Y to include support for NEON in kernel mode.
2145
2146 endmenu
2147
2148 menu "Userspace binary formats"
2149
2150 source "fs/Kconfig.binfmt"
2151
2152 endmenu
2153
2154 menu "Power management options"
2155
2156 source "kernel/power/Kconfig"
2157
2158 config ARCH_SUSPEND_POSSIBLE
2159         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2160                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2161         def_bool y
2162
2163 config ARM_CPU_SUSPEND
2164         def_bool PM_SLEEP
2165
2166 config ARCH_HIBERNATION_POSSIBLE
2167         bool
2168         depends on MMU
2169         default y if ARCH_SUSPEND_POSSIBLE
2170
2171 endmenu
2172
2173 source "net/Kconfig"
2174
2175 source "drivers/Kconfig"
2176
2177 source "drivers/firmware/Kconfig"
2178
2179 source "fs/Kconfig"
2180
2181 source "arch/arm/Kconfig.debug"
2182
2183 source "security/Kconfig"
2184
2185 source "crypto/Kconfig"
2186 if CRYPTO
2187 source "arch/arm/crypto/Kconfig"
2188 endif
2189
2190 source "lib/Kconfig"
2191
2192 source "arch/arm/kvm/Kconfig"